diff options
author | Ken Xue <Ken.Xue@amd.com> | 2015-03-27 05:44:26 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2015-04-07 05:36:49 -0400 |
commit | 25a853d037a40b7ac2c317adef6442ef92d8407e (patch) | |
tree | c8cb91e2955611d3eebb84582bd5fc065d9828b4 | |
parent | d480239ba4963c7d994582ccddc9310127593e14 (diff) |
Fix inconsistent spinlock of AMD GPIO driver which can be
recognized by static analysis tool smatch. Declare constant
Variables with Sparse's suggestion.
Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 19 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl-amd.h | 12 |
2 files changed, 15 insertions, 16 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3fe9ec4d8c40..7de3b64bf142 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c | |||
@@ -29,7 +29,6 @@ | |||
29 | #include <linux/interrupt.h> | 29 | #include <linux/interrupt.h> |
30 | #include <linux/list.h> | 30 | #include <linux/list.h> |
31 | #include <linux/bitops.h> | 31 | #include <linux/bitops.h> |
32 | #include <linux/pinctrl/pinctrl.h> | ||
33 | #include <linux/pinctrl/pinconf.h> | 32 | #include <linux/pinctrl/pinconf.h> |
34 | #include <linux/pinctrl/pinconf-generic.h> | 33 | #include <linux/pinctrl/pinconf-generic.h> |
35 | 34 | ||
@@ -119,8 +118,9 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) | |||
119 | static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | 118 | static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, |
120 | unsigned debounce) | 119 | unsigned debounce) |
121 | { | 120 | { |
122 | u32 pin_reg; | ||
123 | u32 time; | 121 | u32 time; |
122 | u32 pin_reg; | ||
123 | int ret = 0; | ||
124 | unsigned long flags; | 124 | unsigned long flags; |
125 | struct amd_gpio *gpio_dev = to_amd_gpio(gc); | 125 | struct amd_gpio *gpio_dev = to_amd_gpio(gc); |
126 | 126 | ||
@@ -166,7 +166,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |||
166 | pin_reg |= BIT(DB_TMR_LARGE_OFF); | 166 | pin_reg |= BIT(DB_TMR_LARGE_OFF); |
167 | } else { | 167 | } else { |
168 | pin_reg &= ~DB_CNTRl_MASK; | 168 | pin_reg &= ~DB_CNTRl_MASK; |
169 | return -EINVAL; | 169 | ret = -EINVAL; |
170 | } | 170 | } |
171 | } else { | 171 | } else { |
172 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); | 172 | pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); |
@@ -177,7 +177,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, | |||
177 | writel(pin_reg, gpio_dev->base + offset * 4); | 177 | writel(pin_reg, gpio_dev->base + offset * 4); |
178 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | 178 | spin_unlock_irqrestore(&gpio_dev->lock, flags); |
179 | 179 | ||
180 | return 0; | 180 | return ret; |
181 | } | 181 | } |
182 | 182 | ||
183 | #ifdef CONFIG_DEBUG_FS | 183 | #ifdef CONFIG_DEBUG_FS |
@@ -463,14 +463,12 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
463 | default: | 463 | default: |
464 | dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); | 464 | dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); |
465 | ret = -EINVAL; | 465 | ret = -EINVAL; |
466 | goto exit; | ||
467 | } | 466 | } |
468 | 467 | ||
469 | pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; | 468 | pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; |
470 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); | 469 | writel(pin_reg, gpio_dev->base + (d->hwirq)*4); |
471 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | 470 | spin_unlock_irqrestore(&gpio_dev->lock, flags); |
472 | 471 | ||
473 | exit: | ||
474 | return ret; | 472 | return ret; |
475 | } | 473 | } |
476 | 474 | ||
@@ -635,8 +633,9 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |||
635 | unsigned long *configs, unsigned num_configs) | 633 | unsigned long *configs, unsigned num_configs) |
636 | { | 634 | { |
637 | int i; | 635 | int i; |
638 | u32 pin_reg; | ||
639 | u32 arg; | 636 | u32 arg; |
637 | int ret = 0; | ||
638 | u32 pin_reg; | ||
640 | unsigned long flags; | 639 | unsigned long flags; |
641 | enum pin_config_param param; | 640 | enum pin_config_param param; |
642 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); | 641 | struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); |
@@ -675,14 +674,14 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |||
675 | default: | 674 | default: |
676 | dev_err(&gpio_dev->pdev->dev, | 675 | dev_err(&gpio_dev->pdev->dev, |
677 | "Invalid config param %04x\n", param); | 676 | "Invalid config param %04x\n", param); |
678 | return -ENOTSUPP; | 677 | ret = -ENOTSUPP; |
679 | } | 678 | } |
680 | 679 | ||
681 | writel(pin_reg, gpio_dev->base + pin*4); | 680 | writel(pin_reg, gpio_dev->base + pin*4); |
682 | } | 681 | } |
683 | spin_unlock_irqrestore(&gpio_dev->lock, flags); | 682 | spin_unlock_irqrestore(&gpio_dev->lock, flags); |
684 | 683 | ||
685 | return 0; | 684 | return ret; |
686 | } | 685 | } |
687 | 686 | ||
688 | static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, | 687 | static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, |
@@ -739,7 +738,7 @@ static struct pinctrl_desc amd_pinctrl_desc = { | |||
739 | static int amd_gpio_probe(struct platform_device *pdev) | 738 | static int amd_gpio_probe(struct platform_device *pdev) |
740 | { | 739 | { |
741 | int ret = 0; | 740 | int ret = 0; |
742 | u32 irq_base; | 741 | int irq_base; |
743 | struct resource *res; | 742 | struct resource *res; |
744 | struct amd_gpio *gpio_dev; | 743 | struct amd_gpio *gpio_dev; |
745 | 744 | ||
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 37e72aa3f2ab..7bfea47dbb47 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h | |||
@@ -217,13 +217,13 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { | |||
217 | PINCTRL_PIN(177, "GPIO_177"), | 217 | PINCTRL_PIN(177, "GPIO_177"), |
218 | }; | 218 | }; |
219 | 219 | ||
220 | const unsigned i2c0_pins[] = {145, 146}; | 220 | static const unsigned i2c0_pins[] = {145, 146}; |
221 | const unsigned i2c1_pins[] = {147, 148}; | 221 | static const unsigned i2c1_pins[] = {147, 148}; |
222 | const unsigned i2c2_pins[] = {113, 114}; | 222 | static const unsigned i2c2_pins[] = {113, 114}; |
223 | const unsigned i2c3_pins[] = {19, 20}; | 223 | static const unsigned i2c3_pins[] = {19, 20}; |
224 | 224 | ||
225 | const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; | 225 | static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; |
226 | const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; | 226 | static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; |
227 | 227 | ||
228 | static const struct amd_pingroup kerncz_groups[] = { | 228 | static const struct amd_pingroup kerncz_groups[] = { |
229 | { | 229 | { |