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authorDave Airlie <airlied@redhat.com>2012-07-25 20:35:44 -0400
committerDave Airlie <airlied@redhat.com>2012-07-25 20:35:44 -0400
commit2536f7dc42556f63ee45b14e7d2d9696200f317a (patch)
tree8d920a5a95a561db6fa5933953ee5b5dff140c12
parentfcedac670c3da0d17aaa5db1708694971e8024a9 (diff)
parent715855457e6bc93e148caf8cb3b5dcabbf605b0d (diff)
Merge branch 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
* 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau: init vblank requests list drm/nv50: extend vblank semaphore to generic dmaobj + offset pair drm/nouveau: mark most of our ioctls as deprecated, move to compat layer drm/nouveau: move current gpuobj code out of nouveau_object.c drm/nouveau/gem: fix object reference leak in a failure path drm/nv50: rename INVALID_QUERY_OR_TEXTURE error to INVALID_OPERATION drm/nv84: decode PCRYPT errors drm/nouveau: dcb table quirk for fdo#50830 nouveau: Fix alignment requirements on src and dst addresses
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_abi16.c245
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_abi16.h83
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c12
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c95
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c18
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h19
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gpuobj.c (renamed from drivers/gpu/drm/nouveau/nouveau_object.c)60
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_notifier.c41
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_software.h23
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c74
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c25
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv50_software.c19
-rw-r--r--drivers/gpu/drm/nouveau/nv84_crypt.c18
-rw-r--r--drivers/gpu/drm/nouveau/nva3_copy.fuc4
-rw-r--r--drivers/gpu/drm/nouveau/nva3_copy.fuc.h94
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_copy.fuc.h87
-rw-r--r--include/drm/nouveau_drm.h94
21 files changed, 592 insertions, 429 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index fe5267d06ab5..1cece6a78f39 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -4,7 +4,7 @@
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ 6nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
7 nouveau_object.o nouveau_irq.o nouveau_notifier.o \ 7 nouveau_gpuobj.o nouveau_irq.o nouveau_notifier.o \
8 nouveau_sgdma.o nouveau_dma.o nouveau_util.o \ 8 nouveau_sgdma.o nouveau_dma.o nouveau_util.o \
9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ 9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ 10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
@@ -12,6 +12,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
12 nouveau_hdmi.o nouveau_dp.o nouveau_ramht.o \ 12 nouveau_hdmi.o nouveau_dp.o nouveau_ramht.o \
13 nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \ 13 nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \
14 nouveau_mm.o nouveau_vm.o nouveau_mxm.o nouveau_gpio.o \ 14 nouveau_mm.o nouveau_vm.o nouveau_mxm.o nouveau_gpio.o \
15 nouveau_abi16.o \
15 nv04_timer.o \ 16 nv04_timer.o \
16 nv04_mc.o nv40_mc.o nv50_mc.o \ 17 nv04_mc.o nv40_mc.o nv50_mc.o \
17 nv04_fb.o nv10_fb.o nv20_fb.o nv30_fb.o nv40_fb.o \ 18 nv04_fb.o nv10_fb.o nv20_fb.o nv30_fb.o nv40_fb.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
new file mode 100644
index 000000000000..ff23d88880e5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -0,0 +1,245 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25
26#include "nouveau_drv.h"
27#include "nouveau_dma.h"
28#include "nouveau_abi16.h"
29#include "nouveau_ramht.h"
30#include "nouveau_software.h"
31
32int
33nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
34{
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct drm_nouveau_getparam *getparam = data;
37
38 switch (getparam->param) {
39 case NOUVEAU_GETPARAM_CHIPSET_ID:
40 getparam->value = dev_priv->chipset;
41 break;
42 case NOUVEAU_GETPARAM_PCI_VENDOR:
43 getparam->value = dev->pci_vendor;
44 break;
45 case NOUVEAU_GETPARAM_PCI_DEVICE:
46 getparam->value = dev->pci_device;
47 break;
48 case NOUVEAU_GETPARAM_BUS_TYPE:
49 if (drm_pci_device_is_agp(dev))
50 getparam->value = 0;
51 else
52 if (!pci_is_pcie(dev->pdev))
53 getparam->value = 1;
54 else
55 getparam->value = 2;
56 break;
57 case NOUVEAU_GETPARAM_FB_SIZE:
58 getparam->value = dev_priv->fb_available_size;
59 break;
60 case NOUVEAU_GETPARAM_AGP_SIZE:
61 getparam->value = dev_priv->gart_info.aper_size;
62 break;
63 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
64 getparam->value = 0; /* deprecated */
65 break;
66 case NOUVEAU_GETPARAM_PTIMER_TIME:
67 getparam->value = dev_priv->engine.timer.read(dev);
68 break;
69 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
70 getparam->value = 1;
71 break;
72 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
73 getparam->value = 1;
74 break;
75 case NOUVEAU_GETPARAM_GRAPH_UNITS:
76 /* NV40 and NV50 versions are quite different, but register
77 * address is the same. User is supposed to know the card
78 * family anyway... */
79 if (dev_priv->chipset >= 0x40) {
80 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
81 break;
82 }
83 /* FALLTHRU */
84 default:
85 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
86 return -EINVAL;
87 }
88
89 return 0;
90}
91
92int
93nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS)
94{
95 return -EINVAL;
96}
97
98int
99nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
100{
101 struct drm_nouveau_private *dev_priv = dev->dev_private;
102 struct drm_nouveau_channel_alloc *init = data;
103 struct nouveau_channel *chan;
104 int ret;
105
106 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
107 return -ENODEV;
108
109 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
110 return -EINVAL;
111
112 ret = nouveau_channel_alloc(dev, &chan, file_priv,
113 init->fb_ctxdma_handle,
114 init->tt_ctxdma_handle);
115 if (ret)
116 return ret;
117 init->channel = chan->id;
118
119 if (nouveau_vram_pushbuf == 0) {
120 if (chan->dma.ib_max)
121 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
122 NOUVEAU_GEM_DOMAIN_GART;
123 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
124 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
125 else
126 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
127 } else {
128 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
129 }
130
131 if (dev_priv->card_type < NV_C0) {
132 init->subchan[0].handle = 0x00000000;
133 init->subchan[0].grclass = 0x0000;
134 init->subchan[1].handle = NvSw;
135 init->subchan[1].grclass = NV_SW;
136 init->nr_subchan = 2;
137 }
138
139 /* Named memory object area */
140 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
141 &init->notifier_handle);
142
143 if (ret == 0)
144 atomic_inc(&chan->users); /* userspace reference */
145 nouveau_channel_put(&chan);
146 return ret;
147}
148
149int
150nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS)
151{
152 struct drm_nouveau_channel_free *req = data;
153 struct nouveau_channel *chan;
154
155 chan = nouveau_channel_get(file_priv, req->channel);
156 if (IS_ERR(chan))
157 return PTR_ERR(chan);
158
159 list_del(&chan->list);
160 atomic_dec(&chan->users);
161 nouveau_channel_put(&chan);
162 return 0;
163}
164
165int
166nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS)
167{
168 struct drm_nouveau_grobj_alloc *init = data;
169 struct nouveau_channel *chan;
170 int ret;
171
172 if (init->handle == ~0)
173 return -EINVAL;
174
175 /* compatibility with userspace that assumes 506e for all chipsets */
176 if (init->class == 0x506e) {
177 init->class = nouveau_software_class(dev);
178 if (init->class == 0x906e)
179 return 0;
180 } else
181 if (init->class == 0x906e) {
182 NV_ERROR(dev, "906e not supported yet\n");
183 return -EINVAL;
184 }
185
186 chan = nouveau_channel_get(file_priv, init->channel);
187 if (IS_ERR(chan))
188 return PTR_ERR(chan);
189
190 if (nouveau_ramht_find(chan, init->handle)) {
191 ret = -EEXIST;
192 goto out;
193 }
194
195 ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
196 if (ret) {
197 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
198 ret, init->channel, init->handle);
199 }
200
201out:
202 nouveau_channel_put(&chan);
203 return ret;
204}
205
206int
207nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
208{
209 struct drm_nouveau_private *dev_priv = dev->dev_private;
210 struct drm_nouveau_notifierobj_alloc *na = data;
211 struct nouveau_channel *chan;
212 int ret;
213
214 /* completely unnecessary for these chipsets... */
215 if (unlikely(dev_priv->card_type >= NV_C0))
216 return -EINVAL;
217
218 chan = nouveau_channel_get(file_priv, na->channel);
219 if (IS_ERR(chan))
220 return PTR_ERR(chan);
221
222 ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
223 &na->offset);
224 nouveau_channel_put(&chan);
225 return ret;
226}
227
228int
229nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS)
230{
231 struct drm_nouveau_gpuobj_free *objfree = data;
232 struct nouveau_channel *chan;
233 int ret;
234
235 chan = nouveau_channel_get(file_priv, objfree->channel);
236 if (IS_ERR(chan))
237 return PTR_ERR(chan);
238
239 /* Synchronize with the user channel */
240 nouveau_channel_idle(chan);
241
242 ret = nouveau_ramht_remove(chan, objfree->handle);
243 nouveau_channel_put(&chan);
244 return ret;
245}
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h
new file mode 100644
index 000000000000..e6328b008a8c
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h
@@ -0,0 +1,83 @@
1#ifndef __NOUVEAU_ABI16_H__
2#define __NOUVEAU_ABI16_H__
3
4#define ABI16_IOCTL_ARGS \
5 struct drm_device *dev, void *data, struct drm_file *file_priv
6int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
7int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
8int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
9int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
10int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
11int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
12int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
13
14struct drm_nouveau_channel_alloc {
15 uint32_t fb_ctxdma_handle;
16 uint32_t tt_ctxdma_handle;
17
18 int channel;
19 uint32_t pushbuf_domains;
20
21 /* Notifier memory */
22 uint32_t notifier_handle;
23
24 /* DRM-enforced subchannel assignments */
25 struct {
26 uint32_t handle;
27 uint32_t grclass;
28 } subchan[8];
29 uint32_t nr_subchan;
30};
31
32struct drm_nouveau_channel_free {
33 int channel;
34};
35
36struct drm_nouveau_grobj_alloc {
37 int channel;
38 uint32_t handle;
39 int class;
40};
41
42struct drm_nouveau_notifierobj_alloc {
43 uint32_t channel;
44 uint32_t handle;
45 uint32_t size;
46 uint32_t offset;
47};
48
49struct drm_nouveau_gpuobj_free {
50 int channel;
51 uint32_t handle;
52};
53
54#define NOUVEAU_GETPARAM_PCI_VENDOR 3
55#define NOUVEAU_GETPARAM_PCI_DEVICE 4
56#define NOUVEAU_GETPARAM_BUS_TYPE 5
57#define NOUVEAU_GETPARAM_FB_SIZE 8
58#define NOUVEAU_GETPARAM_AGP_SIZE 9
59#define NOUVEAU_GETPARAM_CHIPSET_ID 11
60#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
61#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
62#define NOUVEAU_GETPARAM_PTIMER_TIME 14
63#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
64#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
65struct drm_nouveau_getparam {
66 uint64_t param;
67 uint64_t value;
68};
69
70struct drm_nouveau_setparam {
71 uint64_t param;
72 uint64_t value;
73};
74
75#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
76#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
77#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
78#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
79#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
80#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
81#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
82
83#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 2f11e16a81a9..a0a3fe3c016b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -6091,6 +6091,18 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6091 } 6091 }
6092 } 6092 }
6093 6093
6094 /* fdo#50830: connector indices for VGA and DVI-I are backwards */
6095 if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) {
6096 if (idx == 0 && *conn == 0x02000300)
6097 *conn = 0x02011300;
6098 else
6099 if (idx == 1 && *conn == 0x04011310)
6100 *conn = 0x04000310;
6101 else
6102 if (idx == 2 && *conn == 0x02011312)
6103 *conn = 0x02000312;
6104 }
6105
6094 return true; 6106 return true;
6095} 6107}
6096 6108
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 629d8a2df5bd..debd90225a88 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -395,98 +395,3 @@ nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
395 nouveau_channel_put(&chan); 395 nouveau_channel_put(&chan);
396 } 396 }
397} 397}
398
399
400/***********************************
401 * ioctls wrapping the functions
402 ***********************************/
403
404static int
405nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
406 struct drm_file *file_priv)
407{
408 struct drm_nouveau_private *dev_priv = dev->dev_private;
409 struct drm_nouveau_channel_alloc *init = data;
410 struct nouveau_channel *chan;
411 int ret;
412
413 if (!dev_priv->eng[NVOBJ_ENGINE_GR])
414 return -ENODEV;
415
416 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
417 return -EINVAL;
418
419 ret = nouveau_channel_alloc(dev, &chan, file_priv,
420 init->fb_ctxdma_handle,
421 init->tt_ctxdma_handle);
422 if (ret)
423 return ret;
424 init->channel = chan->id;
425
426 if (nouveau_vram_pushbuf == 0) {
427 if (chan->dma.ib_max)
428 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
429 NOUVEAU_GEM_DOMAIN_GART;
430 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
431 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
432 else
433 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
434 } else {
435 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
436 }
437
438 if (dev_priv->card_type < NV_C0) {
439 init->subchan[0].handle = 0x00000000;
440 init->subchan[0].grclass = 0x0000;
441 init->subchan[1].handle = NvSw;
442 init->subchan[1].grclass = NV_SW;
443 init->nr_subchan = 2;
444 }
445
446 /* Named memory object area */
447 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
448 &init->notifier_handle);
449
450 if (ret == 0)
451 atomic_inc(&chan->users); /* userspace reference */
452 nouveau_channel_put(&chan);
453 return ret;
454}
455
456static int
457nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
458 struct drm_file *file_priv)
459{
460 struct drm_nouveau_channel_free *req = data;
461 struct nouveau_channel *chan;
462
463 chan = nouveau_channel_get(file_priv, req->channel);
464 if (IS_ERR(chan))
465 return PTR_ERR(chan);
466
467 list_del(&chan->list);
468 atomic_dec(&chan->users);
469 nouveau_channel_put(&chan);
470 return 0;
471}
472
473/***********************************
474 * finally, the ioctl table
475 ***********************************/
476
477struct drm_ioctl_desc nouveau_ioctls[] = {
478 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
479 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
480 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
481 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
482 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
483 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
484 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
485 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
486 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
488 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
490};
491
492int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index b4d1b4afcac5..9a36f5f39b06 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -29,6 +29,7 @@
29#include "drm.h" 29#include "drm.h"
30#include "drm_crtc_helper.h" 30#include "drm_crtc_helper.h"
31#include "nouveau_drv.h" 31#include "nouveau_drv.h"
32#include "nouveau_abi16.h"
32#include "nouveau_hw.h" 33#include "nouveau_hw.h"
33#include "nouveau_fb.h" 34#include "nouveau_fb.h"
34#include "nouveau_fbcon.h" 35#include "nouveau_fbcon.h"
@@ -384,6 +385,21 @@ nouveau_pci_resume(struct pci_dev *pdev)
384 return 0; 385 return 0;
385} 386}
386 387
388static struct drm_ioctl_desc nouveau_ioctls[] = {
389 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
390 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
391 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
392 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
393 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
394 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
395 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
396 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
397 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
398 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
399 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
400 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
401};
402
387static const struct file_operations nouveau_driver_fops = { 403static const struct file_operations nouveau_driver_fops = {
388 .owner = THIS_MODULE, 404 .owner = THIS_MODULE,
389 .open = drm_open, 405 .open = drm_open,
@@ -462,7 +478,7 @@ static struct pci_driver nouveau_pci_driver = {
462 478
463static int __init nouveau_init(void) 479static int __init nouveau_init(void)
464{ 480{
465 driver.num_ioctls = nouveau_max_ioctl; 481 driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
466 482
467 if (nouveau_modeset == -1) { 483 if (nouveau_modeset == -1) {
468#ifdef CONFIG_VGA_CONSOLE 484#ifdef CONFIG_VGA_CONSOLE
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 8613cb23808c..4f2cc95ce264 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -689,8 +689,6 @@ struct drm_nouveau_private {
689 void (*irq_handler[32])(struct drm_device *); 689 void (*irq_handler[32])(struct drm_device *);
690 bool msi_enabled; 690 bool msi_enabled;
691 691
692 struct list_head vbl_waiting;
693
694 struct { 692 struct {
695 struct drm_global_reference mem_global_ref; 693 struct drm_global_reference mem_global_ref;
696 struct ttm_bo_global_ref bo_global_ref; 694 struct ttm_bo_global_ref bo_global_ref;
@@ -872,10 +870,6 @@ extern int nouveau_load(struct drm_device *, unsigned long flags);
872extern int nouveau_firstopen(struct drm_device *); 870extern int nouveau_firstopen(struct drm_device *);
873extern void nouveau_lastclose(struct drm_device *); 871extern void nouveau_lastclose(struct drm_device *);
874extern int nouveau_unload(struct drm_device *); 872extern int nouveau_unload(struct drm_device *);
875extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
876 struct drm_file *);
877extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
878 struct drm_file *);
879extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 873extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
880 uint32_t reg, uint32_t mask, uint32_t val); 874 uint32_t reg, uint32_t mask, uint32_t val);
881extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 875extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
@@ -914,15 +908,8 @@ extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
914extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 908extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
915 int cout, uint32_t start, uint32_t end, 909 int cout, uint32_t start, uint32_t end,
916 uint32_t *offset); 910 uint32_t *offset);
917extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
918extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
919 struct drm_file *);
920extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
921 struct drm_file *);
922 911
923/* nouveau_channel.c */ 912/* nouveau_channel.c */
924extern struct drm_ioctl_desc nouveau_ioctls[];
925extern int nouveau_max_ioctl;
926extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 913extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
927extern int nouveau_channel_alloc(struct drm_device *dev, 914extern int nouveau_channel_alloc(struct drm_device *dev,
928 struct nouveau_channel **chan, 915 struct nouveau_channel **chan,
@@ -938,7 +925,7 @@ extern void nouveau_channel_ref(struct nouveau_channel *chan,
938 struct nouveau_channel **pchan); 925 struct nouveau_channel **pchan);
939extern int nouveau_channel_idle(struct nouveau_channel *chan); 926extern int nouveau_channel_idle(struct nouveau_channel *chan);
940 927
941/* nouveau_object.c */ 928/* nouveau_gpuobj.c */
942#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 929#define NVOBJ_ENGINE_ADD(d, e, p) do { \
943 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 930 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
944 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 931 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
@@ -993,10 +980,6 @@ extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
993extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 980extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
994 int class, u64 base, u64 size, int target, 981 int class, u64 base, u64 size, int target,
995 int access, u32 type, u32 comp); 982 int access, u32 type, u32 comp);
996extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
997 struct drm_file *);
998extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
999 struct drm_file *);
1000 983
1001/* nouveau_irq.c */ 984/* nouveau_irq.c */
1002extern int nouveau_irq_init(struct drm_device *); 985extern int nouveau_irq_init(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index fe3f5a821b84..af7cfb825716 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -341,6 +341,7 @@ retry:
341 if (nvbo->reserved_by && nvbo->reserved_by == file_priv) { 341 if (nvbo->reserved_by && nvbo->reserved_by == file_priv) {
342 NV_ERROR(dev, "multiple instances of buffer %d on " 342 NV_ERROR(dev, "multiple instances of buffer %d on "
343 "validation list\n", b->handle); 343 "validation list\n", b->handle);
344 drm_gem_object_unreference_unlocked(gem);
344 validate_fini(op, NULL); 345 validate_fini(op, NULL);
345 return -EINVAL; 346 return -EINVAL;
346 } 347 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_gpuobj.c
index b190cc01c820..bd79fedb7054 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gpuobj.c
@@ -758,66 +758,6 @@ nouveau_gpuobj_resume(struct drm_device *dev)
758 dev_priv->engine.instmem.flush(dev); 758 dev_priv->engine.instmem.flush(dev);
759} 759}
760 760
761int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
762 struct drm_file *file_priv)
763{
764 struct drm_nouveau_grobj_alloc *init = data;
765 struct nouveau_channel *chan;
766 int ret;
767
768 if (init->handle == ~0)
769 return -EINVAL;
770
771 /* compatibility with userspace that assumes 506e for all chipsets */
772 if (init->class == 0x506e) {
773 init->class = nouveau_software_class(dev);
774 if (init->class == 0x906e)
775 return 0;
776 } else
777 if (init->class == 0x906e) {
778 NV_ERROR(dev, "906e not supported yet\n");
779 return -EINVAL;
780 }
781
782 chan = nouveau_channel_get(file_priv, init->channel);
783 if (IS_ERR(chan))
784 return PTR_ERR(chan);
785
786 if (nouveau_ramht_find(chan, init->handle)) {
787 ret = -EEXIST;
788 goto out;
789 }
790
791 ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
792 if (ret) {
793 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
794 ret, init->channel, init->handle);
795 }
796
797out:
798 nouveau_channel_put(&chan);
799 return ret;
800}
801
802int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
803 struct drm_file *file_priv)
804{
805 struct drm_nouveau_gpuobj_free *objfree = data;
806 struct nouveau_channel *chan;
807 int ret;
808
809 chan = nouveau_channel_get(file_priv, objfree->channel);
810 if (IS_ERR(chan))
811 return PTR_ERR(chan);
812
813 /* Synchronize with the user channel */
814 nouveau_channel_idle(chan);
815
816 ret = nouveau_ramht_remove(chan, objfree->handle);
817 nouveau_channel_put(&chan);
818 return ret;
819}
820
821u32 761u32
822nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) 762nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
823{ 763{
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 868c7fd74854..b2c2937531a8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -41,12 +41,8 @@
41void 41void
42nouveau_irq_preinstall(struct drm_device *dev) 42nouveau_irq_preinstall(struct drm_device *dev)
43{ 43{
44 struct drm_nouveau_private *dev_priv = dev->dev_private;
45
46 /* Master disable */ 44 /* Master disable */
47 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 45 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
48
49 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
50} 46}
51 47
52int 48int
diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c
index 2ef883c4bbc1..69c93b864519 100644
--- a/drivers/gpu/drm/nouveau/nouveau_notifier.c
+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c
@@ -161,44 +161,3 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
161 *b_offset = mem->start; 161 *b_offset = mem->start;
162 return 0; 162 return 0;
163} 163}
164
165int
166nouveau_notifier_offset(struct nouveau_gpuobj *nobj, uint32_t *poffset)
167{
168 if (!nobj || nobj->dtor != nouveau_notifier_gpuobj_dtor)
169 return -EINVAL;
170
171 if (poffset) {
172 struct drm_mm_node *mem = nobj->priv;
173
174 if (*poffset >= mem->size)
175 return false;
176
177 *poffset += mem->start;
178 }
179
180 return 0;
181}
182
183int
184nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
185 struct drm_file *file_priv)
186{
187 struct drm_nouveau_private *dev_priv = dev->dev_private;
188 struct drm_nouveau_notifierobj_alloc *na = data;
189 struct nouveau_channel *chan;
190 int ret;
191
192 /* completely unnecessary for these chipsets... */
193 if (unlikely(dev_priv->card_type >= NV_C0))
194 return -EINVAL;
195
196 chan = nouveau_channel_get(file_priv, na->channel);
197 if (IS_ERR(chan))
198 return PTR_ERR(chan);
199
200 ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
201 &na->offset);
202 nouveau_channel_put(&chan);
203 return ret;
204}
diff --git a/drivers/gpu/drm/nouveau/nouveau_software.h b/drivers/gpu/drm/nouveau/nouveau_software.h
index e60bc6ce9003..709e5ac680ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_software.h
+++ b/drivers/gpu/drm/nouveau/nouveau_software.h
@@ -4,13 +4,15 @@
4struct nouveau_software_priv { 4struct nouveau_software_priv {
5 struct nouveau_exec_engine base; 5 struct nouveau_exec_engine base;
6 struct list_head vblank; 6 struct list_head vblank;
7 spinlock_t peephole_lock;
7}; 8};
8 9
9struct nouveau_software_chan { 10struct nouveau_software_chan {
10 struct list_head flip; 11 struct list_head flip;
11 struct { 12 struct {
12 struct list_head list; 13 struct list_head list;
13 struct nouveau_bo *bo; 14 u32 channel;
15 u32 ctxdma;
14 u32 offset; 16 u32 offset;
15 u32 value; 17 u32 value;
16 u32 head; 18 u32 head;
@@ -18,32 +20,17 @@ struct nouveau_software_chan {
18}; 20};
19 21
20static inline void 22static inline void
21nouveau_software_vblank(struct drm_device *dev, int crtc)
22{
23 struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
24 struct nouveau_software_chan *pch, *tmp;
25
26 list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
27 if (pch->vblank.head != crtc)
28 continue;
29
30 nouveau_bo_wr32(pch->vblank.bo, pch->vblank.offset,
31 pch->vblank.value);
32 list_del(&pch->vblank.list);
33 drm_vblank_put(dev, crtc);
34 }
35}
36
37static inline void
38nouveau_software_context_new(struct nouveau_software_chan *pch) 23nouveau_software_context_new(struct nouveau_software_chan *pch)
39{ 24{
40 INIT_LIST_HEAD(&pch->flip); 25 INIT_LIST_HEAD(&pch->flip);
26 INIT_LIST_HEAD(&pch->vblank.list);
41} 27}
42 28
43static inline void 29static inline void
44nouveau_software_create(struct nouveau_software_priv *psw) 30nouveau_software_create(struct nouveau_software_priv *psw)
45{ 31{
46 INIT_LIST_HEAD(&psw->vblank); 32 INIT_LIST_HEAD(&psw->vblank);
33 spin_lock_init(&psw->peephole_lock);
47} 34}
48 35
49static inline u16 36static inline u16
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 19706f0532ea..1cdfd6e757ce 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -1234,80 +1234,6 @@ int nouveau_unload(struct drm_device *dev)
1234 return 0; 1234 return 0;
1235} 1235}
1236 1236
1237int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1238 struct drm_file *file_priv)
1239{
1240 struct drm_nouveau_private *dev_priv = dev->dev_private;
1241 struct drm_nouveau_getparam *getparam = data;
1242
1243 switch (getparam->param) {
1244 case NOUVEAU_GETPARAM_CHIPSET_ID:
1245 getparam->value = dev_priv->chipset;
1246 break;
1247 case NOUVEAU_GETPARAM_PCI_VENDOR:
1248 getparam->value = dev->pci_vendor;
1249 break;
1250 case NOUVEAU_GETPARAM_PCI_DEVICE:
1251 getparam->value = dev->pci_device;
1252 break;
1253 case NOUVEAU_GETPARAM_BUS_TYPE:
1254 if (drm_pci_device_is_agp(dev))
1255 getparam->value = NV_AGP;
1256 else if (pci_is_pcie(dev->pdev))
1257 getparam->value = NV_PCIE;
1258 else
1259 getparam->value = NV_PCI;
1260 break;
1261 case NOUVEAU_GETPARAM_FB_SIZE:
1262 getparam->value = dev_priv->fb_available_size;
1263 break;
1264 case NOUVEAU_GETPARAM_AGP_SIZE:
1265 getparam->value = dev_priv->gart_info.aper_size;
1266 break;
1267 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1268 getparam->value = 0; /* deprecated */
1269 break;
1270 case NOUVEAU_GETPARAM_PTIMER_TIME:
1271 getparam->value = dev_priv->engine.timer.read(dev);
1272 break;
1273 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1274 getparam->value = 1;
1275 break;
1276 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1277 getparam->value = 1;
1278 break;
1279 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1280 /* NV40 and NV50 versions are quite different, but register
1281 * address is the same. User is supposed to know the card
1282 * family anyway... */
1283 if (dev_priv->chipset >= 0x40) {
1284 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1285 break;
1286 }
1287 /* FALLTHRU */
1288 default:
1289 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1290 return -EINVAL;
1291 }
1292
1293 return 0;
1294}
1295
1296int
1297nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1298 struct drm_file *file_priv)
1299{
1300 struct drm_nouveau_setparam *setparam = data;
1301
1302 switch (setparam->param) {
1303 default:
1304 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1305 return -EINVAL;
1306 }
1307
1308 return 0;
1309}
1310
1311/* Wait until (value(reg) & mask) == val, up until timeout has hit */ 1237/* Wait until (value(reg) & mask) == val, up until timeout has hit */
1312bool 1238bool
1313nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, 1239nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 5c41612723b4..b244d9968c5d 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -646,7 +646,30 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
646static void 646static void
647nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc) 647nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
648{ 648{
649 nouveau_software_vblank(dev, crtc); 649 struct drm_nouveau_private *dev_priv = dev->dev_private;
650 struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
651 struct nouveau_software_chan *pch, *tmp;
652
653 list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
654 if (pch->vblank.head != crtc)
655 continue;
656
657 spin_lock(&psw->peephole_lock);
658 nv_wr32(dev, 0x001704, pch->vblank.channel);
659 nv_wr32(dev, 0x001710, 0x80000000 | pch->vblank.ctxdma);
660 if (dev_priv->chipset == 0x50) {
661 nv_wr32(dev, 0x001570, pch->vblank.offset);
662 nv_wr32(dev, 0x001574, pch->vblank.value);
663 } else {
664 nv_wr32(dev, 0x060010, pch->vblank.offset);
665 nv_wr32(dev, 0x060014, pch->vblank.value);
666 }
667 spin_unlock(&psw->peephole_lock);
668
669 list_del(&pch->vblank.list);
670 drm_vblank_put(dev, crtc);
671 }
672
650 drm_handle_vblank(dev, crtc); 673 drm_handle_vblank(dev, crtc);
651} 674}
652 675
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index d9cc2f2638d6..437608d1dfe7 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -299,7 +299,7 @@ static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
299 299
300/* There must be a *lot* of these. Will take some time to gather them up. */ 300/* There must be a *lot* of these. Will take some time to gather them up. */
301struct nouveau_enum nv50_data_error_names[] = { 301struct nouveau_enum nv50_data_error_names[] = {
302 { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL }, 302 { 0x00000003, "INVALID_OPERATION", NULL },
303 { 0x00000004, "INVALID_VALUE", NULL }, 303 { 0x00000004, "INVALID_VALUE", NULL },
304 { 0x00000005, "INVALID_ENUM", NULL }, 304 { 0x00000005, "INVALID_ENUM", NULL },
305 { 0x00000008, "INVALID_OBJECT", NULL }, 305 { 0x00000008, "INVALID_OBJECT", NULL },
diff --git a/drivers/gpu/drm/nouveau/nv50_software.c b/drivers/gpu/drm/nouveau/nv50_software.c
index 114d2517d4a8..df554d9dacb8 100644
--- a/drivers/gpu/drm/nouveau/nv50_software.c
+++ b/drivers/gpu/drm/nouveau/nv50_software.c
@@ -36,9 +36,6 @@ struct nv50_software_priv {
36 36
37struct nv50_software_chan { 37struct nv50_software_chan {
38 struct nouveau_software_chan base; 38 struct nouveau_software_chan base;
39 struct {
40 struct nouveau_gpuobj *object;
41 } vblank;
42}; 39};
43 40
44static int 41static int
@@ -51,11 +48,7 @@ mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
51 if (!gpuobj) 48 if (!gpuobj)
52 return -ENOENT; 49 return -ENOENT;
53 50
54 if (nouveau_notifier_offset(gpuobj, NULL)) 51 pch->base.vblank.ctxdma = gpuobj->cinst >> 4;
55 return -EINVAL;
56
57 pch->vblank.object = gpuobj;
58 pch->base.vblank.offset = ~0;
59 return 0; 52 return 0;
60} 53}
61 54
@@ -63,11 +56,7 @@ static int
63mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) 56mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
64{ 57{
65 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; 58 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
66 59 pch->base.vblank.offset = data;
67 if (nouveau_notifier_offset(pch->vblank.object, &data))
68 return -ERANGE;
69
70 pch->base.vblank.offset = data >> 2;
71 return 0; 60 return 0;
72} 61}
73 62
@@ -86,7 +75,7 @@ mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
86 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; 75 struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
87 struct drm_device *dev = chan->dev; 76 struct drm_device *dev = chan->dev;
88 77
89 if (!pch->vblank.object || pch->base.vblank.offset == ~0 || data > 1) 78 if (data > 1)
90 return -EINVAL; 79 return -EINVAL;
91 80
92 drm_vblank_get(dev, data); 81 drm_vblank_get(dev, data);
@@ -116,7 +105,7 @@ nv50_software_context_new(struct nouveau_channel *chan, int engine)
116 return -ENOMEM; 105 return -ENOMEM;
117 106
118 nouveau_software_context_new(&pch->base); 107 nouveau_software_context_new(&pch->base);
119 pch->base.vblank.bo = chan->notifier_bo; 108 pch->base.vblank.channel = chan->ramin->vinst >> 12;
120 chan->engctx[engine] = pch; 109 chan->engctx[engine] = pch;
121 110
122 /* dma objects for display sync channel semaphore blocks */ 111 /* dma objects for display sync channel semaphore blocks */
diff --git a/drivers/gpu/drm/nouveau/nv84_crypt.c b/drivers/gpu/drm/nouveau/nv84_crypt.c
index edece9c616eb..bbfcc73b6708 100644
--- a/drivers/gpu/drm/nouveau/nv84_crypt.c
+++ b/drivers/gpu/drm/nouveau/nv84_crypt.c
@@ -117,18 +117,30 @@ nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
117 nv50_vm_flush_engine(dev, 0x0a); 117 nv50_vm_flush_engine(dev, 0x0a);
118} 118}
119 119
120static struct nouveau_bitfield nv84_crypt_intr[] = {
121 { 0x00000001, "INVALID_STATE" },
122 { 0x00000002, "ILLEGAL_MTHD" },
123 { 0x00000004, "ILLEGAL_CLASS" },
124 { 0x00000080, "QUERY" },
125 { 0x00000100, "FAULT" },
126 {}
127};
128
120static void 129static void
121nv84_crypt_isr(struct drm_device *dev) 130nv84_crypt_isr(struct drm_device *dev)
122{ 131{
123 u32 stat = nv_rd32(dev, 0x102130); 132 u32 stat = nv_rd32(dev, 0x102130);
124 u32 mthd = nv_rd32(dev, 0x102190); 133 u32 mthd = nv_rd32(dev, 0x102190);
125 u32 data = nv_rd32(dev, 0x102194); 134 u32 data = nv_rd32(dev, 0x102194);
126 u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff; 135 u64 inst = (u64)(nv_rd32(dev, 0x102188) & 0x7fffffff) << 12;
127 int show = nouveau_ratelimit(); 136 int show = nouveau_ratelimit();
137 int chid = nv50_graph_isr_chid(dev, inst);
128 138
129 if (show) { 139 if (show) {
130 NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n", 140 NV_INFO(dev, "PCRYPT:");
131 stat, mthd, data, inst); 141 nouveau_bitfield_print(nv84_crypt_intr, stat);
142 printk(KERN_CONT " ch %d (0x%010llx) mthd 0x%04x data 0x%08x\n",
143 chid, inst, mthd, data);
132 } 144 }
133 145
134 nv_wr32(dev, 0x102130, stat); 146 nv_wr32(dev, 0x102130, stat);
diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc b/drivers/gpu/drm/nouveau/nva3_copy.fuc
index abc36626fef0..219850d53286 100644
--- a/drivers/gpu/drm/nouveau/nva3_copy.fuc
+++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc
@@ -119,9 +119,9 @@ dispatch_dma:
119// mthd 0x030c-0x0340, various stuff 119// mthd 0x030c-0x0340, various stuff
120.b16 0xc3 14 120.b16 0xc3 14
121.b32 #ctx_src_address_high ~0x000000ff 121.b32 #ctx_src_address_high ~0x000000ff
122.b32 #ctx_src_address_low ~0xfffffff0 122.b32 #ctx_src_address_low ~0xffffffff
123.b32 #ctx_dst_address_high ~0x000000ff 123.b32 #ctx_dst_address_high ~0x000000ff
124.b32 #ctx_dst_address_low ~0xfffffff0 124.b32 #ctx_dst_address_low ~0xffffffff
125.b32 #ctx_src_pitch ~0x0007ffff 125.b32 #ctx_src_pitch ~0x0007ffff
126.b32 #ctx_dst_pitch ~0x0007ffff 126.b32 #ctx_dst_pitch ~0x0007ffff
127.b32 #ctx_xcnt ~0x0000ffff 127.b32 #ctx_xcnt ~0x0000ffff
diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc.h b/drivers/gpu/drm/nouveau/nva3_copy.fuc.h
index 1f33fbdc00be..37d6de3c9d61 100644
--- a/drivers/gpu/drm/nouveau/nva3_copy.fuc.h
+++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc.h
@@ -1,37 +1,72 @@
1uint32_t nva3_pcopy_data[] = { 1u32 nva3_pcopy_data[] = {
2/* 0x0000: ctx_object */
2 0x00000000, 3 0x00000000,
4/* 0x0004: ctx_dma */
5/* 0x0004: ctx_dma_query */
3 0x00000000, 6 0x00000000,
7/* 0x0008: ctx_dma_src */
4 0x00000000, 8 0x00000000,
9/* 0x000c: ctx_dma_dst */
5 0x00000000, 10 0x00000000,
11/* 0x0010: ctx_query_address_high */
6 0x00000000, 12 0x00000000,
13/* 0x0014: ctx_query_address_low */
7 0x00000000, 14 0x00000000,
15/* 0x0018: ctx_query_counter */
8 0x00000000, 16 0x00000000,
17/* 0x001c: ctx_src_address_high */
9 0x00000000, 18 0x00000000,
19/* 0x0020: ctx_src_address_low */
10 0x00000000, 20 0x00000000,
21/* 0x0024: ctx_src_pitch */
11 0x00000000, 22 0x00000000,
23/* 0x0028: ctx_src_tile_mode */
12 0x00000000, 24 0x00000000,
25/* 0x002c: ctx_src_xsize */
13 0x00000000, 26 0x00000000,
27/* 0x0030: ctx_src_ysize */
14 0x00000000, 28 0x00000000,
29/* 0x0034: ctx_src_zsize */
15 0x00000000, 30 0x00000000,
31/* 0x0038: ctx_src_zoff */
16 0x00000000, 32 0x00000000,
33/* 0x003c: ctx_src_xoff */
17 0x00000000, 34 0x00000000,
35/* 0x0040: ctx_src_yoff */
18 0x00000000, 36 0x00000000,
37/* 0x0044: ctx_src_cpp */
19 0x00000000, 38 0x00000000,
39/* 0x0048: ctx_dst_address_high */
20 0x00000000, 40 0x00000000,
41/* 0x004c: ctx_dst_address_low */
21 0x00000000, 42 0x00000000,
43/* 0x0050: ctx_dst_pitch */
22 0x00000000, 44 0x00000000,
45/* 0x0054: ctx_dst_tile_mode */
23 0x00000000, 46 0x00000000,
47/* 0x0058: ctx_dst_xsize */
24 0x00000000, 48 0x00000000,
49/* 0x005c: ctx_dst_ysize */
25 0x00000000, 50 0x00000000,
51/* 0x0060: ctx_dst_zsize */
26 0x00000000, 52 0x00000000,
53/* 0x0064: ctx_dst_zoff */
27 0x00000000, 54 0x00000000,
55/* 0x0068: ctx_dst_xoff */
28 0x00000000, 56 0x00000000,
57/* 0x006c: ctx_dst_yoff */
29 0x00000000, 58 0x00000000,
59/* 0x0070: ctx_dst_cpp */
30 0x00000000, 60 0x00000000,
61/* 0x0074: ctx_format */
31 0x00000000, 62 0x00000000,
63/* 0x0078: ctx_swz_const0 */
32 0x00000000, 64 0x00000000,
65/* 0x007c: ctx_swz_const1 */
33 0x00000000, 66 0x00000000,
67/* 0x0080: ctx_xcnt */
34 0x00000000, 68 0x00000000,
69/* 0x0084: ctx_ycnt */
35 0x00000000, 70 0x00000000,
36 0x00000000, 71 0x00000000,
37 0x00000000, 72 0x00000000,
@@ -63,6 +98,7 @@ uint32_t nva3_pcopy_data[] = {
63 0x00000000, 98 0x00000000,
64 0x00000000, 99 0x00000000,
65 0x00000000, 100 0x00000000,
101/* 0x0100: dispatch_table */
66 0x00010000, 102 0x00010000,
67 0x00000000, 103 0x00000000,
68 0x00000000, 104 0x00000000,
@@ -73,6 +109,7 @@ uint32_t nva3_pcopy_data[] = {
73 0x00010162, 109 0x00010162,
74 0x00000000, 110 0x00000000,
75 0x00030060, 111 0x00030060,
112/* 0x0128: dispatch_dma */
76 0x00010170, 113 0x00010170,
77 0x00000000, 114 0x00000000,
78 0x00010170, 115 0x00010170,
@@ -118,11 +155,11 @@ uint32_t nva3_pcopy_data[] = {
118 0x0000001c, 155 0x0000001c,
119 0xffffff00, 156 0xffffff00,
120 0x00000020, 157 0x00000020,
121 0x0000000f, 158 0x00000000,
122 0x00000048, 159 0x00000048,
123 0xffffff00, 160 0xffffff00,
124 0x0000004c, 161 0x0000004c,
125 0x0000000f, 162 0x00000000,
126 0x00000024, 163 0x00000024,
127 0xfff80000, 164 0xfff80000,
128 0x00000050, 165 0x00000050,
@@ -146,7 +183,8 @@ uint32_t nva3_pcopy_data[] = {
146 0x00000800, 183 0x00000800,
147}; 184};
148 185
149uint32_t nva3_pcopy_code[] = { 186u32 nva3_pcopy_code[] = {
187/* 0x0000: main */
150 0x04fe04bd, 188 0x04fe04bd,
151 0x3517f000, 189 0x3517f000,
152 0xf10010fe, 190 0xf10010fe,
@@ -158,23 +196,31 @@ uint32_t nva3_pcopy_code[] = {
158 0x17f11031, 196 0x17f11031,
159 0x27f01200, 197 0x27f01200,
160 0x0012d003, 198 0x0012d003,
199/* 0x002f: spin */
161 0xf40031f4, 200 0xf40031f4,
162 0x0ef40028, 201 0x0ef40028,
202/* 0x0035: ih */
163 0x8001cffd, 203 0x8001cffd,
164 0xf40812c4, 204 0xf40812c4,
165 0x21f4060b, 205 0x21f4060b,
206/* 0x0041: ih_no_chsw */
166 0x0412c472, 207 0x0412c472,
167 0xf4060bf4, 208 0xf4060bf4,
209/* 0x004a: ih_no_cmd */
168 0x11c4c321, 210 0x11c4c321,
169 0x4001d00c, 211 0x4001d00c,
212/* 0x0052: swctx */
170 0x47f101f8, 213 0x47f101f8,
171 0x4bfe7700, 214 0x4bfe7700,
172 0x0007fe00, 215 0x0007fe00,
173 0xf00204b9, 216 0xf00204b9,
174 0x01f40643, 217 0x01f40643,
175 0x0604fa09, 218 0x0604fa09,
219/* 0x006b: swctx_load */
176 0xfa060ef4, 220 0xfa060ef4,
221/* 0x006e: swctx_done */
177 0x03f80504, 222 0x03f80504,
223/* 0x0072: chsw */
178 0x27f100f8, 224 0x27f100f8,
179 0x23cf1400, 225 0x23cf1400,
180 0x1e3fc800, 226 0x1e3fc800,
@@ -183,18 +229,22 @@ uint32_t nva3_pcopy_code[] = {
183 0x1e3af052, 229 0x1e3af052,
184 0xf00023d0, 230 0xf00023d0,
185 0x24d00147, 231 0x24d00147,
232/* 0x0093: chsw_no_unload */
186 0xcf00f880, 233 0xcf00f880,
187 0x3dc84023, 234 0x3dc84023,
188 0x220bf41e, 235 0x220bf41e,
189 0xf40131f4, 236 0xf40131f4,
190 0x57f05221, 237 0x57f05221,
191 0x0367f004, 238 0x0367f004,
239/* 0x00a8: chsw_load_ctx_dma */
192 0xa07856bc, 240 0xa07856bc,
193 0xb6018068, 241 0xb6018068,
194 0x87d00884, 242 0x87d00884,
195 0x0162b600, 243 0x0162b600,
244/* 0x00bb: chsw_finish_load */
196 0xf0f018f4, 245 0xf0f018f4,
197 0x23d00237, 246 0x23d00237,
247/* 0x00c3: dispatch */
198 0xf100f880, 248 0xf100f880,
199 0xcf190037, 249 0xcf190037,
200 0x33cf4032, 250 0x33cf4032,
@@ -202,6 +252,7 @@ uint32_t nva3_pcopy_code[] = {
202 0x1024b607, 252 0x1024b607,
203 0x010057f1, 253 0x010057f1,
204 0x74bd64bd, 254 0x74bd64bd,
255/* 0x00dc: dispatch_loop */
205 0x58005658, 256 0x58005658,
206 0x50b60157, 257 0x50b60157,
207 0x0446b804, 258 0x0446b804,
@@ -211,6 +262,7 @@ uint32_t nva3_pcopy_code[] = {
211 0xb60276bb, 262 0xb60276bb,
212 0x57bb0374, 263 0x57bb0374,
213 0xdf0ef400, 264 0xdf0ef400,
265/* 0x0100: dispatch_valid_mthd */
214 0xb60246bb, 266 0xb60246bb,
215 0x45bb0344, 267 0x45bb0344,
216 0x01459800, 268 0x01459800,
@@ -220,31 +272,41 @@ uint32_t nva3_pcopy_code[] = {
220 0xb0014658, 272 0xb0014658,
221 0x1bf40064, 273 0x1bf40064,
222 0x00538009, 274 0x00538009,
275/* 0x0127: dispatch_cmd */
223 0xf4300ef4, 276 0xf4300ef4,
224 0x55f90132, 277 0x55f90132,
225 0xf40c01f4, 278 0xf40c01f4,
279/* 0x0132: dispatch_invalid_bitfield */
226 0x25f0250e, 280 0x25f0250e,
281/* 0x0135: dispatch_illegal_mthd */
227 0x0125f002, 282 0x0125f002,
283/* 0x0138: dispatch_error */
228 0x100047f1, 284 0x100047f1,
229 0xd00042d0, 285 0xd00042d0,
230 0x27f04043, 286 0x27f04043,
231 0x0002d040, 287 0x0002d040,
288/* 0x0148: hostirq_wait */
232 0xf08002cf, 289 0xf08002cf,
233 0x24b04024, 290 0x24b04024,
234 0xf71bf400, 291 0xf71bf400,
292/* 0x0154: dispatch_done */
235 0x1d0027f1, 293 0x1d0027f1,
236 0xd00137f0, 294 0xd00137f0,
237 0x00f80023, 295 0x00f80023,
296/* 0x0160: cmd_nop */
297/* 0x0162: cmd_pm_trigger */
238 0x27f100f8, 298 0x27f100f8,
239 0x34bd2200, 299 0x34bd2200,
240 0xd00233f0, 300 0xd00233f0,
241 0x00f80023, 301 0x00f80023,
302/* 0x0170: cmd_dma */
242 0x012842b7, 303 0x012842b7,
243 0xf00145b6, 304 0xf00145b6,
244 0x43801e39, 305 0x43801e39,
245 0x0040b701, 306 0x0040b701,
246 0x0644b606, 307 0x0644b606,
247 0xf80043d0, 308 0xf80043d0,
309/* 0x0189: cmd_exec_set_format */
248 0xf030f400, 310 0xf030f400,
249 0xb00001b0, 311 0xb00001b0,
250 0x01b00101, 312 0x01b00101,
@@ -256,20 +318,26 @@ uint32_t nva3_pcopy_code[] = {
256 0x70b63847, 318 0x70b63847,
257 0x0232f401, 319 0x0232f401,
258 0x94bd84bd, 320 0x94bd84bd,
321/* 0x01b4: ncomp_loop */
259 0xb60f4ac4, 322 0xb60f4ac4,
260 0xb4bd0445, 323 0xb4bd0445,
324/* 0x01bc: bpc_loop */
261 0xf404a430, 325 0xf404a430,
262 0xa5ff0f18, 326 0xa5ff0f18,
263 0x00cbbbc0, 327 0x00cbbbc0,
264 0xf40231f4, 328 0xf40231f4,
329/* 0x01ce: cmp_c0 */
265 0x1bf4220e, 330 0x1bf4220e,
266 0x10c7f00c, 331 0x10c7f00c,
267 0xf400cbbb, 332 0xf400cbbb,
333/* 0x01da: cmp_c1 */
268 0xa430160e, 334 0xa430160e,
269 0x0c18f406, 335 0x0c18f406,
270 0xbb14c7f0, 336 0xbb14c7f0,
271 0x0ef400cb, 337 0x0ef400cb,
338/* 0x01e9: cmp_zero */
272 0x80c7f107, 339 0x80c7f107,
340/* 0x01ed: bpc_next */
273 0x01c83800, 341 0x01c83800,
274 0xb60180b6, 342 0xb60180b6,
275 0xb5b801b0, 343 0xb5b801b0,
@@ -280,6 +348,7 @@ uint32_t nva3_pcopy_code[] = {
280 0x98110680, 348 0x98110680,
281 0x68fd2008, 349 0x68fd2008,
282 0x0502f400, 350 0x0502f400,
351/* 0x0216: dst_xcnt */
283 0x75fd64bd, 352 0x75fd64bd,
284 0x1c078000, 353 0x1c078000,
285 0xf10078fd, 354 0xf10078fd,
@@ -304,6 +373,7 @@ uint32_t nva3_pcopy_code[] = {
304 0x980056d0, 373 0x980056d0,
305 0x56d01f06, 374 0x56d01f06,
306 0x1030f440, 375 0x1030f440,
376/* 0x0276: cmd_exec_set_surface_tiled */
307 0x579800f8, 377 0x579800f8,
308 0x6879c70a, 378 0x6879c70a,
309 0xb66478c7, 379 0xb66478c7,
@@ -311,9 +381,11 @@ uint32_t nva3_pcopy_code[] = {
311 0x0e76b060, 381 0x0e76b060,
312 0xf0091bf4, 382 0xf0091bf4,
313 0x0ef40477, 383 0x0ef40477,
384/* 0x0291: xtile64 */
314 0x027cf00f, 385 0x027cf00f,
315 0xfd1170b6, 386 0xfd1170b6,
316 0x77f00947, 387 0x77f00947,
388/* 0x029d: xtileok */
317 0x0f5a9806, 389 0x0f5a9806,
318 0xfd115b98, 390 0xfd115b98,
319 0xb7f000ab, 391 0xb7f000ab,
@@ -371,6 +443,7 @@ uint32_t nva3_pcopy_code[] = {
371 0x67d00600, 443 0x67d00600,
372 0x0060b700, 444 0x0060b700,
373 0x0068d004, 445 0x0068d004,
446/* 0x0382: cmd_exec_set_surface_linear */
374 0x6cf000f8, 447 0x6cf000f8,
375 0x0260b702, 448 0x0260b702,
376 0x0864b602, 449 0x0864b602,
@@ -381,13 +454,16 @@ uint32_t nva3_pcopy_code[] = {
381 0xb70067d0, 454 0xb70067d0,
382 0x98040060, 455 0x98040060,
383 0x67d00957, 456 0x67d00957,
457/* 0x03ab: cmd_exec_wait */
384 0xf900f800, 458 0xf900f800,
385 0xf110f900, 459 0xf110f900,
386 0xb6080007, 460 0xb6080007,
461/* 0x03b6: loop */
387 0x01cf0604, 462 0x01cf0604,
388 0x0114f000, 463 0x0114f000,
389 0xfcfa1bf4, 464 0xfcfa1bf4,
390 0xf800fc10, 465 0xf800fc10,
466/* 0x03c5: cmd_exec_query */
391 0x0d34c800, 467 0x0d34c800,
392 0xf5701bf4, 468 0xf5701bf4,
393 0xf103ab21, 469 0xf103ab21,
@@ -417,6 +493,7 @@ uint32_t nva3_pcopy_code[] = {
417 0x47f10153, 493 0x47f10153,
418 0x44b60800, 494 0x44b60800,
419 0x0045d006, 495 0x0045d006,
496/* 0x0438: query_counter */
420 0x03ab21f5, 497 0x03ab21f5,
421 0x080c47f1, 498 0x080c47f1,
422 0x980644b6, 499 0x980644b6,
@@ -439,11 +516,13 @@ uint32_t nva3_pcopy_code[] = {
439 0x47f10153, 516 0x47f10153,
440 0x44b60800, 517 0x44b60800,
441 0x0045d006, 518 0x0045d006,
519/* 0x0492: cmd_exec */
442 0x21f500f8, 520 0x21f500f8,
443 0x3fc803ab, 521 0x3fc803ab,
444 0x0e0bf400, 522 0x0e0bf400,
445 0x018921f5, 523 0x018921f5,
446 0x020047f1, 524 0x020047f1,
525/* 0x04a7: cmd_exec_no_format */
447 0xf11e0ef4, 526 0xf11e0ef4,
448 0xb6081067, 527 0xb6081067,
449 0x77f00664, 528 0x77f00664,
@@ -451,19 +530,24 @@ uint32_t nva3_pcopy_code[] = {
451 0x981c0780, 530 0x981c0780,
452 0x67d02007, 531 0x67d02007,
453 0x4067d000, 532 0x4067d000,
533/* 0x04c2: cmd_exec_init_src_surface */
454 0x32f444bd, 534 0x32f444bd,
455 0xc854bd02, 535 0xc854bd02,
456 0x0bf4043f, 536 0x0bf4043f,
457 0x8221f50a, 537 0x8221f50a,
458 0x0a0ef403, 538 0x0a0ef403,
539/* 0x04d4: src_tiled */
459 0x027621f5, 540 0x027621f5,
541/* 0x04db: cmd_exec_init_dst_surface */
460 0xf40749f0, 542 0xf40749f0,
461 0x57f00231, 543 0x57f00231,
462 0x083fc82c, 544 0x083fc82c,
463 0xf50a0bf4, 545 0xf50a0bf4,
464 0xf4038221, 546 0xf4038221,
547/* 0x04ee: dst_tiled */
465 0x21f50a0e, 548 0x21f50a0e,
466 0x49f00276, 549 0x49f00276,
550/* 0x04f5: cmd_exec_kick */
467 0x0057f108, 551 0x0057f108,
468 0x0654b608, 552 0x0654b608,
469 0xd0210698, 553 0xd0210698,
@@ -473,6 +557,8 @@ uint32_t nva3_pcopy_code[] = {
473 0xc80054d0, 557 0xc80054d0,
474 0x0bf40c3f, 558 0x0bf40c3f,
475 0xc521f507, 559 0xc521f507,
560/* 0x0519: cmd_exec_done */
561/* 0x051b: cmd_wrcache_flush */
476 0xf100f803, 562 0xf100f803,
477 0xbd220027, 563 0xbd220027,
478 0x0133f034, 564 0x0133f034,
diff --git a/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h b/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
index a8d17458ced1..cd879f31bb38 100644
--- a/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
+++ b/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
@@ -1,34 +1,65 @@
1uint32_t nvc0_pcopy_data[] = { 1u32 nvc0_pcopy_data[] = {
2/* 0x0000: ctx_object */
2 0x00000000, 3 0x00000000,
4/* 0x0004: ctx_query_address_high */
3 0x00000000, 5 0x00000000,
6/* 0x0008: ctx_query_address_low */
4 0x00000000, 7 0x00000000,
8/* 0x000c: ctx_query_counter */
5 0x00000000, 9 0x00000000,
10/* 0x0010: ctx_src_address_high */
6 0x00000000, 11 0x00000000,
12/* 0x0014: ctx_src_address_low */
7 0x00000000, 13 0x00000000,
14/* 0x0018: ctx_src_pitch */
8 0x00000000, 15 0x00000000,
16/* 0x001c: ctx_src_tile_mode */
9 0x00000000, 17 0x00000000,
18/* 0x0020: ctx_src_xsize */
10 0x00000000, 19 0x00000000,
20/* 0x0024: ctx_src_ysize */
11 0x00000000, 21 0x00000000,
22/* 0x0028: ctx_src_zsize */
12 0x00000000, 23 0x00000000,
24/* 0x002c: ctx_src_zoff */
13 0x00000000, 25 0x00000000,
26/* 0x0030: ctx_src_xoff */
14 0x00000000, 27 0x00000000,
28/* 0x0034: ctx_src_yoff */
15 0x00000000, 29 0x00000000,
30/* 0x0038: ctx_src_cpp */
16 0x00000000, 31 0x00000000,
32/* 0x003c: ctx_dst_address_high */
17 0x00000000, 33 0x00000000,
34/* 0x0040: ctx_dst_address_low */
18 0x00000000, 35 0x00000000,
36/* 0x0044: ctx_dst_pitch */
19 0x00000000, 37 0x00000000,
38/* 0x0048: ctx_dst_tile_mode */
20 0x00000000, 39 0x00000000,
40/* 0x004c: ctx_dst_xsize */
21 0x00000000, 41 0x00000000,
42/* 0x0050: ctx_dst_ysize */
22 0x00000000, 43 0x00000000,
44/* 0x0054: ctx_dst_zsize */
23 0x00000000, 45 0x00000000,
46/* 0x0058: ctx_dst_zoff */
24 0x00000000, 47 0x00000000,
48/* 0x005c: ctx_dst_xoff */
25 0x00000000, 49 0x00000000,
50/* 0x0060: ctx_dst_yoff */
26 0x00000000, 51 0x00000000,
52/* 0x0064: ctx_dst_cpp */
27 0x00000000, 53 0x00000000,
54/* 0x0068: ctx_format */
28 0x00000000, 55 0x00000000,
56/* 0x006c: ctx_swz_const0 */
29 0x00000000, 57 0x00000000,
58/* 0x0070: ctx_swz_const1 */
30 0x00000000, 59 0x00000000,
60/* 0x0074: ctx_xcnt */
31 0x00000000, 61 0x00000000,
62/* 0x0078: ctx_ycnt */
32 0x00000000, 63 0x00000000,
33 0x00000000, 64 0x00000000,
34 0x00000000, 65 0x00000000,
@@ -63,6 +94,7 @@ uint32_t nvc0_pcopy_data[] = {
63 0x00000000, 94 0x00000000,
64 0x00000000, 95 0x00000000,
65 0x00000000, 96 0x00000000,
97/* 0x0100: dispatch_table */
66 0x00010000, 98 0x00010000,
67 0x00000000, 99 0x00000000,
68 0x00000000, 100 0x00000000,
@@ -111,11 +143,11 @@ uint32_t nvc0_pcopy_data[] = {
111 0x00000010, 143 0x00000010,
112 0xffffff00, 144 0xffffff00,
113 0x00000014, 145 0x00000014,
114 0x0000000f, 146 0x00000000,
115 0x0000003c, 147 0x0000003c,
116 0xffffff00, 148 0xffffff00,
117 0x00000040, 149 0x00000040,
118 0x0000000f, 150 0x00000000,
119 0x00000018, 151 0x00000018,
120 0xfff80000, 152 0xfff80000,
121 0x00000044, 153 0x00000044,
@@ -139,7 +171,8 @@ uint32_t nvc0_pcopy_data[] = {
139 0x00000800, 171 0x00000800,
140}; 172};
141 173
142uint32_t nvc0_pcopy_code[] = { 174u32 nvc0_pcopy_code[] = {
175/* 0x0000: main */
143 0x04fe04bd, 176 0x04fe04bd,
144 0x3517f000, 177 0x3517f000,
145 0xf10010fe, 178 0xf10010fe,
@@ -151,15 +184,20 @@ uint32_t nvc0_pcopy_code[] = {
151 0x17f11031, 184 0x17f11031,
152 0x27f01200, 185 0x27f01200,
153 0x0012d003, 186 0x0012d003,
187/* 0x002f: spin */
154 0xf40031f4, 188 0xf40031f4,
155 0x0ef40028, 189 0x0ef40028,
190/* 0x0035: ih */
156 0x8001cffd, 191 0x8001cffd,
157 0xf40812c4, 192 0xf40812c4,
158 0x21f4060b, 193 0x21f4060b,
194/* 0x0041: ih_no_chsw */
159 0x0412c4ca, 195 0x0412c4ca,
160 0xf5070bf4, 196 0xf5070bf4,
197/* 0x004b: ih_no_cmd */
161 0xc4010221, 198 0xc4010221,
162 0x01d00c11, 199 0x01d00c11,
200/* 0x0053: swctx */
163 0xf101f840, 201 0xf101f840,
164 0xfe770047, 202 0xfe770047,
165 0x47f1004b, 203 0x47f1004b,
@@ -188,8 +226,11 @@ uint32_t nvc0_pcopy_code[] = {
188 0xf00204b9, 226 0xf00204b9,
189 0x01f40643, 227 0x01f40643,
190 0x0604fa09, 228 0x0604fa09,
229/* 0x00c3: swctx_load */
191 0xfa060ef4, 230 0xfa060ef4,
231/* 0x00c6: swctx_done */
192 0x03f80504, 232 0x03f80504,
233/* 0x00ca: chsw */
193 0x27f100f8, 234 0x27f100f8,
194 0x23cf1400, 235 0x23cf1400,
195 0x1e3fc800, 236 0x1e3fc800,
@@ -198,18 +239,22 @@ uint32_t nvc0_pcopy_code[] = {
198 0x1e3af053, 239 0x1e3af053,
199 0xf00023d0, 240 0xf00023d0,
200 0x24d00147, 241 0x24d00147,
242/* 0x00eb: chsw_no_unload */
201 0xcf00f880, 243 0xcf00f880,
202 0x3dc84023, 244 0x3dc84023,
203 0x090bf41e, 245 0x090bf41e,
204 0xf40131f4, 246 0xf40131f4,
247/* 0x00fa: chsw_finish_load */
205 0x37f05321, 248 0x37f05321,
206 0x8023d002, 249 0x8023d002,
250/* 0x0102: dispatch */
207 0x37f100f8, 251 0x37f100f8,
208 0x32cf1900, 252 0x32cf1900,
209 0x0033cf40, 253 0x0033cf40,
210 0x07ff24e4, 254 0x07ff24e4,
211 0xf11024b6, 255 0xf11024b6,
212 0xbd010057, 256 0xbd010057,
257/* 0x011b: dispatch_loop */
213 0x5874bd64, 258 0x5874bd64,
214 0x57580056, 259 0x57580056,
215 0x0450b601, 260 0x0450b601,
@@ -219,6 +264,7 @@ uint32_t nvc0_pcopy_code[] = {
219 0xbb0f08f4, 264 0xbb0f08f4,
220 0x74b60276, 265 0x74b60276,
221 0x0057bb03, 266 0x0057bb03,
267/* 0x013f: dispatch_valid_mthd */
222 0xbbdf0ef4, 268 0xbbdf0ef4,
223 0x44b60246, 269 0x44b60246,
224 0x0045bb03, 270 0x0045bb03,
@@ -229,24 +275,33 @@ uint32_t nvc0_pcopy_code[] = {
229 0x64b00146, 275 0x64b00146,
230 0x091bf400, 276 0x091bf400,
231 0xf4005380, 277 0xf4005380,
278/* 0x0166: dispatch_cmd */
232 0x32f4300e, 279 0x32f4300e,
233 0xf455f901, 280 0xf455f901,
234 0x0ef40c01, 281 0x0ef40c01,
282/* 0x0171: dispatch_invalid_bitfield */
235 0x0225f025, 283 0x0225f025,
284/* 0x0174: dispatch_illegal_mthd */
285/* 0x0177: dispatch_error */
236 0xf10125f0, 286 0xf10125f0,
237 0xd0100047, 287 0xd0100047,
238 0x43d00042, 288 0x43d00042,
239 0x4027f040, 289 0x4027f040,
290/* 0x0187: hostirq_wait */
240 0xcf0002d0, 291 0xcf0002d0,
241 0x24f08002, 292 0x24f08002,
242 0x0024b040, 293 0x0024b040,
294/* 0x0193: dispatch_done */
243 0xf1f71bf4, 295 0xf1f71bf4,
244 0xf01d0027, 296 0xf01d0027,
245 0x23d00137, 297 0x23d00137,
298/* 0x019f: cmd_nop */
246 0xf800f800, 299 0xf800f800,
300/* 0x01a1: cmd_pm_trigger */
247 0x0027f100, 301 0x0027f100,
248 0xf034bd22, 302 0xf034bd22,
249 0x23d00233, 303 0x23d00233,
304/* 0x01af: cmd_exec_set_format */
250 0xf400f800, 305 0xf400f800,
251 0x01b0f030, 306 0x01b0f030,
252 0x0101b000, 307 0x0101b000,
@@ -258,20 +313,26 @@ uint32_t nvc0_pcopy_code[] = {
258 0x3847c701, 313 0x3847c701,
259 0xf40170b6, 314 0xf40170b6,
260 0x84bd0232, 315 0x84bd0232,
316/* 0x01da: ncomp_loop */
261 0x4ac494bd, 317 0x4ac494bd,
262 0x0445b60f, 318 0x0445b60f,
319/* 0x01e2: bpc_loop */
263 0xa430b4bd, 320 0xa430b4bd,
264 0x0f18f404, 321 0x0f18f404,
265 0xbbc0a5ff, 322 0xbbc0a5ff,
266 0x31f400cb, 323 0x31f400cb,
267 0x220ef402, 324 0x220ef402,
325/* 0x01f4: cmp_c0 */
268 0xf00c1bf4, 326 0xf00c1bf4,
269 0xcbbb10c7, 327 0xcbbb10c7,
270 0x160ef400, 328 0x160ef400,
329/* 0x0200: cmp_c1 */
271 0xf406a430, 330 0xf406a430,
272 0xc7f00c18, 331 0xc7f00c18,
273 0x00cbbb14, 332 0x00cbbb14,
333/* 0x020f: cmp_zero */
274 0xf1070ef4, 334 0xf1070ef4,
335/* 0x0213: bpc_next */
275 0x380080c7, 336 0x380080c7,
276 0x80b601c8, 337 0x80b601c8,
277 0x01b0b601, 338 0x01b0b601,
@@ -283,6 +344,7 @@ uint32_t nvc0_pcopy_code[] = {
283 0x1d08980e, 344 0x1d08980e,
284 0xf40068fd, 345 0xf40068fd,
285 0x64bd0502, 346 0x64bd0502,
347/* 0x023c: dst_xcnt */
286 0x800075fd, 348 0x800075fd,
287 0x78fd1907, 349 0x78fd1907,
288 0x1057f100, 350 0x1057f100,
@@ -307,15 +369,18 @@ uint32_t nvc0_pcopy_code[] = {
307 0x1c069800, 369 0x1c069800,
308 0xf44056d0, 370 0xf44056d0,
309 0x00f81030, 371 0x00f81030,
372/* 0x029c: cmd_exec_set_surface_tiled */
310 0xc7075798, 373 0xc7075798,
311 0x78c76879, 374 0x78c76879,
312 0x0380b664, 375 0x0380b664,
313 0xb06077c7, 376 0xb06077c7,
314 0x1bf40e76, 377 0x1bf40e76,
315 0x0477f009, 378 0x0477f009,
379/* 0x02b7: xtile64 */
316 0xf00f0ef4, 380 0xf00f0ef4,
317 0x70b6027c, 381 0x70b6027c,
318 0x0947fd11, 382 0x0947fd11,
383/* 0x02c3: xtileok */
319 0x980677f0, 384 0x980677f0,
320 0x5b980c5a, 385 0x5b980c5a,
321 0x00abfd0e, 386 0x00abfd0e,
@@ -374,6 +439,7 @@ uint32_t nvc0_pcopy_code[] = {
374 0xb70067d0, 439 0xb70067d0,
375 0xd0040060, 440 0xd0040060,
376 0x00f80068, 441 0x00f80068,
442/* 0x03a8: cmd_exec_set_surface_linear */
377 0xb7026cf0, 443 0xb7026cf0,
378 0xb6020260, 444 0xb6020260,
379 0x57980864, 445 0x57980864,
@@ -384,12 +450,15 @@ uint32_t nvc0_pcopy_code[] = {
384 0x0060b700, 450 0x0060b700,
385 0x06579804, 451 0x06579804,
386 0xf80067d0, 452 0xf80067d0,
453/* 0x03d1: cmd_exec_wait */
387 0xf900f900, 454 0xf900f900,
388 0x0007f110, 455 0x0007f110,
389 0x0604b608, 456 0x0604b608,
457/* 0x03dc: loop */
390 0xf00001cf, 458 0xf00001cf,
391 0x1bf40114, 459 0x1bf40114,
392 0xfc10fcfa, 460 0xfc10fcfa,
461/* 0x03eb: cmd_exec_query */
393 0xc800f800, 462 0xc800f800,
394 0x1bf40d34, 463 0x1bf40d34,
395 0xd121f570, 464 0xd121f570,
@@ -419,6 +488,7 @@ uint32_t nvc0_pcopy_code[] = {
419 0x0153f026, 488 0x0153f026,
420 0x080047f1, 489 0x080047f1,
421 0xd00644b6, 490 0xd00644b6,
491/* 0x045e: query_counter */
422 0x21f50045, 492 0x21f50045,
423 0x47f103d1, 493 0x47f103d1,
424 0x44b6080c, 494 0x44b6080c,
@@ -442,11 +512,13 @@ uint32_t nvc0_pcopy_code[] = {
442 0x080047f1, 512 0x080047f1,
443 0xd00644b6, 513 0xd00644b6,
444 0x00f80045, 514 0x00f80045,
515/* 0x04b8: cmd_exec */
445 0x03d121f5, 516 0x03d121f5,
446 0xf4003fc8, 517 0xf4003fc8,
447 0x21f50e0b, 518 0x21f50e0b,
448 0x47f101af, 519 0x47f101af,
449 0x0ef40200, 520 0x0ef40200,
521/* 0x04cd: cmd_exec_no_format */
450 0x1067f11e, 522 0x1067f11e,
451 0x0664b608, 523 0x0664b608,
452 0x800177f0, 524 0x800177f0,
@@ -454,18 +526,23 @@ uint32_t nvc0_pcopy_code[] = {
454 0x1d079819, 526 0x1d079819,
455 0xd00067d0, 527 0xd00067d0,
456 0x44bd4067, 528 0x44bd4067,
529/* 0x04e8: cmd_exec_init_src_surface */
457 0xbd0232f4, 530 0xbd0232f4,
458 0x043fc854, 531 0x043fc854,
459 0xf50a0bf4, 532 0xf50a0bf4,
460 0xf403a821, 533 0xf403a821,
534/* 0x04fa: src_tiled */
461 0x21f50a0e, 535 0x21f50a0e,
462 0x49f0029c, 536 0x49f0029c,
537/* 0x0501: cmd_exec_init_dst_surface */
463 0x0231f407, 538 0x0231f407,
464 0xc82c57f0, 539 0xc82c57f0,
465 0x0bf4083f, 540 0x0bf4083f,
466 0xa821f50a, 541 0xa821f50a,
467 0x0a0ef403, 542 0x0a0ef403,
543/* 0x0514: dst_tiled */
468 0x029c21f5, 544 0x029c21f5,
545/* 0x051b: cmd_exec_kick */
469 0xf10849f0, 546 0xf10849f0,
470 0xb6080057, 547 0xb6080057,
471 0x06980654, 548 0x06980654,
@@ -475,7 +552,9 @@ uint32_t nvc0_pcopy_code[] = {
475 0x54d00546, 552 0x54d00546,
476 0x0c3fc800, 553 0x0c3fc800,
477 0xf5070bf4, 554 0xf5070bf4,
555/* 0x053f: cmd_exec_done */
478 0xf803eb21, 556 0xf803eb21,
557/* 0x0541: cmd_wrcache_flush */
479 0x0027f100, 558 0x0027f100,
480 0xf034bd22, 559 0xf034bd22,
481 0x23d00133, 560 0x23d00133,
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index 5edd3a76fffa..2a5769fdf8ba 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -25,70 +25,6 @@
25#ifndef __NOUVEAU_DRM_H__ 25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__ 26#define __NOUVEAU_DRM_H__
27 27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29
30struct drm_nouveau_channel_alloc {
31 uint32_t fb_ctxdma_handle;
32 uint32_t tt_ctxdma_handle;
33
34 int channel;
35 uint32_t pushbuf_domains;
36
37 /* Notifier memory */
38 uint32_t notifier_handle;
39
40 /* DRM-enforced subchannel assignments */
41 struct {
42 uint32_t handle;
43 uint32_t grclass;
44 } subchan[8];
45 uint32_t nr_subchan;
46};
47
48struct drm_nouveau_channel_free {
49 int channel;
50};
51
52struct drm_nouveau_grobj_alloc {
53 int channel;
54 uint32_t handle;
55 int class;
56};
57
58struct drm_nouveau_notifierobj_alloc {
59 uint32_t channel;
60 uint32_t handle;
61 uint32_t size;
62 uint32_t offset;
63};
64
65struct drm_nouveau_gpuobj_free {
66 int channel;
67 uint32_t handle;
68};
69
70/* FIXME : maybe unify {GET,SET}PARAMs */
71#define NOUVEAU_GETPARAM_PCI_VENDOR 3
72#define NOUVEAU_GETPARAM_PCI_DEVICE 4
73#define NOUVEAU_GETPARAM_BUS_TYPE 5
74#define NOUVEAU_GETPARAM_FB_SIZE 8
75#define NOUVEAU_GETPARAM_AGP_SIZE 9
76#define NOUVEAU_GETPARAM_CHIPSET_ID 11
77#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
78#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
79#define NOUVEAU_GETPARAM_PTIMER_TIME 14
80#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
81#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
82struct drm_nouveau_getparam {
83 uint64_t param;
84 uint64_t value;
85};
86
87struct drm_nouveau_setparam {
88 uint64_t param;
89 uint64_t value;
90};
91
92#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 28#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
93#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 29#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
94#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 30#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
@@ -180,35 +116,19 @@ struct drm_nouveau_gem_cpu_fini {
180 uint32_t handle; 116 uint32_t handle;
181}; 117};
182 118
183enum nouveau_bus_type { 119#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
184 NV_AGP = 0, 120#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
185 NV_PCI = 1, 121#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
186 NV_PCIE = 2, 122#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
187}; 123#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
188 124#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
189struct drm_nouveau_sarea { 125#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
190};
191
192#define DRM_NOUVEAU_GETPARAM 0x00
193#define DRM_NOUVEAU_SETPARAM 0x01
194#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
195#define DRM_NOUVEAU_CHANNEL_FREE 0x03
196#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
197#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
198#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
199#define DRM_NOUVEAU_GEM_NEW 0x40 126#define DRM_NOUVEAU_GEM_NEW 0x40
200#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 127#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
201#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 128#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
202#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 129#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
203#define DRM_NOUVEAU_GEM_INFO 0x44 130#define DRM_NOUVEAU_GEM_INFO 0x44
204 131
205#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
206#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
207#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
208#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
209#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
210#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
211#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
212#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 132#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
213#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 133#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
214#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) 134#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 22:37:34 -0400