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authorLinus Walleij <linus.walleij@linaro.org>2013-01-04 07:38:18 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-01-07 11:36:15 -0500
commit24dbcd8a0376856c31f03501e9eada577d5ad648 (patch)
tree878977a1156ab0df38309308b8b59a3ceedbec02
parent9f575d9741ff28b6661f639d63b4f465c19889c4 (diff)
dma: coh901318: push platform data into driver
We're only ever going to support the U300 with this driver so skip the separation of platform data from driver, and push it down into the driver itself. Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--arch/arm/mach-u300/core.c1084
-rw-r--r--drivers/dma/coh901318.c1088
2 files changed, 1085 insertions, 1087 deletions
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 0951b51f36a6..834d0bd2aa0f 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -327,1089 +327,6 @@ static struct resource dma_resource[] = {
327 } 327 }
328}; 328};
329 329
330/* points out all dma slave channels.
331 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
332 * Select all channels from A to B, end of list is marked with -1,-1
333 */
334static int dma_slave_channels[] = {
335 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
336 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
337
338/* points out all dma memcpy channels. */
339static int dma_memcpy_channels[] = {
340 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
341
342/** register dma for memory access
343 *
344 * active 1 means dma intends to access memory
345 * 0 means dma wont access memory
346 */
347static void coh901318_access_memory_state(struct device *dev, bool active)
348{
349}
350
351#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
352 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
353 COH901318_CX_CFG_LCR_DISABLE | \
354 COH901318_CX_CFG_TC_IRQ_ENABLE | \
355 COH901318_CX_CFG_BE_IRQ_ENABLE)
356#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
357 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
358 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
359 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
360 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
361 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
362 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
363 COH901318_CX_CTRL_TCP_DISABLE | \
364 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
365 COH901318_CX_CTRL_HSP_DISABLE | \
366 COH901318_CX_CTRL_HSS_DISABLE | \
367 COH901318_CX_CTRL_DDMA_LEGACY | \
368 COH901318_CX_CTRL_PRDD_SOURCE)
369#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
370 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
371 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
372 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
373 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
374 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
375 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
376 COH901318_CX_CTRL_TCP_DISABLE | \
377 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
378 COH901318_CX_CTRL_HSP_DISABLE | \
379 COH901318_CX_CTRL_HSS_DISABLE | \
380 COH901318_CX_CTRL_DDMA_LEGACY | \
381 COH901318_CX_CTRL_PRDD_SOURCE)
382#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
383 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
384 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
385 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
386 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
387 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
388 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
389 COH901318_CX_CTRL_TCP_DISABLE | \
390 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
391 COH901318_CX_CTRL_HSP_DISABLE | \
392 COH901318_CX_CTRL_HSS_DISABLE | \
393 COH901318_CX_CTRL_DDMA_LEGACY | \
394 COH901318_CX_CTRL_PRDD_SOURCE)
395
396const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
397 {
398 .number = U300_DMA_MSL_TX_0,
399 .name = "MSL TX 0",
400 .priority_high = 0,
401 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
402 },
403 {
404 .number = U300_DMA_MSL_TX_1,
405 .name = "MSL TX 1",
406 .priority_high = 0,
407 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
408 .param.config = COH901318_CX_CFG_CH_DISABLE |
409 COH901318_CX_CFG_LCR_DISABLE |
410 COH901318_CX_CFG_TC_IRQ_ENABLE |
411 COH901318_CX_CFG_BE_IRQ_ENABLE,
412 .param.ctrl_lli_chained = 0 |
413 COH901318_CX_CTRL_TC_ENABLE |
414 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
415 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
416 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
417 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
418 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
419 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
420 COH901318_CX_CTRL_TCP_DISABLE |
421 COH901318_CX_CTRL_TC_IRQ_DISABLE |
422 COH901318_CX_CTRL_HSP_ENABLE |
423 COH901318_CX_CTRL_HSS_DISABLE |
424 COH901318_CX_CTRL_DDMA_LEGACY |
425 COH901318_CX_CTRL_PRDD_SOURCE,
426 .param.ctrl_lli = 0 |
427 COH901318_CX_CTRL_TC_ENABLE |
428 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
429 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
430 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
431 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
432 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
433 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
434 COH901318_CX_CTRL_TCP_ENABLE |
435 COH901318_CX_CTRL_TC_IRQ_DISABLE |
436 COH901318_CX_CTRL_HSP_ENABLE |
437 COH901318_CX_CTRL_HSS_DISABLE |
438 COH901318_CX_CTRL_DDMA_LEGACY |
439 COH901318_CX_CTRL_PRDD_SOURCE,
440 .param.ctrl_lli_last = 0 |
441 COH901318_CX_CTRL_TC_ENABLE |
442 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
443 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
444 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
445 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
446 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
447 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
448 COH901318_CX_CTRL_TCP_ENABLE |
449 COH901318_CX_CTRL_TC_IRQ_ENABLE |
450 COH901318_CX_CTRL_HSP_ENABLE |
451 COH901318_CX_CTRL_HSS_DISABLE |
452 COH901318_CX_CTRL_DDMA_LEGACY |
453 COH901318_CX_CTRL_PRDD_SOURCE,
454 },
455 {
456 .number = U300_DMA_MSL_TX_2,
457 .name = "MSL TX 2",
458 .priority_high = 0,
459 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
460 .param.config = COH901318_CX_CFG_CH_DISABLE |
461 COH901318_CX_CFG_LCR_DISABLE |
462 COH901318_CX_CFG_TC_IRQ_ENABLE |
463 COH901318_CX_CFG_BE_IRQ_ENABLE,
464 .param.ctrl_lli_chained = 0 |
465 COH901318_CX_CTRL_TC_ENABLE |
466 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
467 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
468 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
469 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
470 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
471 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
472 COH901318_CX_CTRL_TCP_DISABLE |
473 COH901318_CX_CTRL_TC_IRQ_DISABLE |
474 COH901318_CX_CTRL_HSP_ENABLE |
475 COH901318_CX_CTRL_HSS_DISABLE |
476 COH901318_CX_CTRL_DDMA_LEGACY |
477 COH901318_CX_CTRL_PRDD_SOURCE,
478 .param.ctrl_lli = 0 |
479 COH901318_CX_CTRL_TC_ENABLE |
480 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
481 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
482 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
483 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
484 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
485 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
486 COH901318_CX_CTRL_TCP_ENABLE |
487 COH901318_CX_CTRL_TC_IRQ_DISABLE |
488 COH901318_CX_CTRL_HSP_ENABLE |
489 COH901318_CX_CTRL_HSS_DISABLE |
490 COH901318_CX_CTRL_DDMA_LEGACY |
491 COH901318_CX_CTRL_PRDD_SOURCE,
492 .param.ctrl_lli_last = 0 |
493 COH901318_CX_CTRL_TC_ENABLE |
494 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
495 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
496 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
497 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
498 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
499 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
500 COH901318_CX_CTRL_TCP_ENABLE |
501 COH901318_CX_CTRL_TC_IRQ_ENABLE |
502 COH901318_CX_CTRL_HSP_ENABLE |
503 COH901318_CX_CTRL_HSS_DISABLE |
504 COH901318_CX_CTRL_DDMA_LEGACY |
505 COH901318_CX_CTRL_PRDD_SOURCE,
506 .desc_nbr_max = 10,
507 },
508 {
509 .number = U300_DMA_MSL_TX_3,
510 .name = "MSL TX 3",
511 .priority_high = 0,
512 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
513 .param.config = COH901318_CX_CFG_CH_DISABLE |
514 COH901318_CX_CFG_LCR_DISABLE |
515 COH901318_CX_CFG_TC_IRQ_ENABLE |
516 COH901318_CX_CFG_BE_IRQ_ENABLE,
517 .param.ctrl_lli_chained = 0 |
518 COH901318_CX_CTRL_TC_ENABLE |
519 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
520 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
521 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
522 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
523 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
524 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
525 COH901318_CX_CTRL_TCP_DISABLE |
526 COH901318_CX_CTRL_TC_IRQ_DISABLE |
527 COH901318_CX_CTRL_HSP_ENABLE |
528 COH901318_CX_CTRL_HSS_DISABLE |
529 COH901318_CX_CTRL_DDMA_LEGACY |
530 COH901318_CX_CTRL_PRDD_SOURCE,
531 .param.ctrl_lli = 0 |
532 COH901318_CX_CTRL_TC_ENABLE |
533 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
534 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
535 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
536 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
537 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
538 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
539 COH901318_CX_CTRL_TCP_ENABLE |
540 COH901318_CX_CTRL_TC_IRQ_DISABLE |
541 COH901318_CX_CTRL_HSP_ENABLE |
542 COH901318_CX_CTRL_HSS_DISABLE |
543 COH901318_CX_CTRL_DDMA_LEGACY |
544 COH901318_CX_CTRL_PRDD_SOURCE,
545 .param.ctrl_lli_last = 0 |
546 COH901318_CX_CTRL_TC_ENABLE |
547 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
548 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
549 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
550 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
551 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
552 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
553 COH901318_CX_CTRL_TCP_ENABLE |
554 COH901318_CX_CTRL_TC_IRQ_ENABLE |
555 COH901318_CX_CTRL_HSP_ENABLE |
556 COH901318_CX_CTRL_HSS_DISABLE |
557 COH901318_CX_CTRL_DDMA_LEGACY |
558 COH901318_CX_CTRL_PRDD_SOURCE,
559 },
560 {
561 .number = U300_DMA_MSL_TX_4,
562 .name = "MSL TX 4",
563 .priority_high = 0,
564 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
565 .param.config = COH901318_CX_CFG_CH_DISABLE |
566 COH901318_CX_CFG_LCR_DISABLE |
567 COH901318_CX_CFG_TC_IRQ_ENABLE |
568 COH901318_CX_CFG_BE_IRQ_ENABLE,
569 .param.ctrl_lli_chained = 0 |
570 COH901318_CX_CTRL_TC_ENABLE |
571 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
572 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
573 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
574 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
575 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
576 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
577 COH901318_CX_CTRL_TCP_DISABLE |
578 COH901318_CX_CTRL_TC_IRQ_DISABLE |
579 COH901318_CX_CTRL_HSP_ENABLE |
580 COH901318_CX_CTRL_HSS_DISABLE |
581 COH901318_CX_CTRL_DDMA_LEGACY |
582 COH901318_CX_CTRL_PRDD_SOURCE,
583 .param.ctrl_lli = 0 |
584 COH901318_CX_CTRL_TC_ENABLE |
585 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
586 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
587 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
588 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
589 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
590 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
591 COH901318_CX_CTRL_TCP_ENABLE |
592 COH901318_CX_CTRL_TC_IRQ_DISABLE |
593 COH901318_CX_CTRL_HSP_ENABLE |
594 COH901318_CX_CTRL_HSS_DISABLE |
595 COH901318_CX_CTRL_DDMA_LEGACY |
596 COH901318_CX_CTRL_PRDD_SOURCE,
597 .param.ctrl_lli_last = 0 |
598 COH901318_CX_CTRL_TC_ENABLE |
599 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
600 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
601 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
602 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
603 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
604 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
605 COH901318_CX_CTRL_TCP_ENABLE |
606 COH901318_CX_CTRL_TC_IRQ_ENABLE |
607 COH901318_CX_CTRL_HSP_ENABLE |
608 COH901318_CX_CTRL_HSS_DISABLE |
609 COH901318_CX_CTRL_DDMA_LEGACY |
610 COH901318_CX_CTRL_PRDD_SOURCE,
611 },
612 {
613 .number = U300_DMA_MSL_TX_5,
614 .name = "MSL TX 5",
615 .priority_high = 0,
616 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
617 },
618 {
619 .number = U300_DMA_MSL_TX_6,
620 .name = "MSL TX 6",
621 .priority_high = 0,
622 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
623 },
624 {
625 .number = U300_DMA_MSL_RX_0,
626 .name = "MSL RX 0",
627 .priority_high = 0,
628 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
629 },
630 {
631 .number = U300_DMA_MSL_RX_1,
632 .name = "MSL RX 1",
633 .priority_high = 0,
634 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
635 .param.config = COH901318_CX_CFG_CH_DISABLE |
636 COH901318_CX_CFG_LCR_DISABLE |
637 COH901318_CX_CFG_TC_IRQ_ENABLE |
638 COH901318_CX_CFG_BE_IRQ_ENABLE,
639 .param.ctrl_lli_chained = 0 |
640 COH901318_CX_CTRL_TC_ENABLE |
641 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
642 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
643 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
644 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
645 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
646 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
647 COH901318_CX_CTRL_TCP_DISABLE |
648 COH901318_CX_CTRL_TC_IRQ_DISABLE |
649 COH901318_CX_CTRL_HSP_ENABLE |
650 COH901318_CX_CTRL_HSS_DISABLE |
651 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
652 COH901318_CX_CTRL_PRDD_DEST,
653 .param.ctrl_lli = 0,
654 .param.ctrl_lli_last = 0 |
655 COH901318_CX_CTRL_TC_ENABLE |
656 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
657 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
658 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
659 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
661 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
662 COH901318_CX_CTRL_TCP_DISABLE |
663 COH901318_CX_CTRL_TC_IRQ_ENABLE |
664 COH901318_CX_CTRL_HSP_ENABLE |
665 COH901318_CX_CTRL_HSS_DISABLE |
666 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
667 COH901318_CX_CTRL_PRDD_DEST,
668 },
669 {
670 .number = U300_DMA_MSL_RX_2,
671 .name = "MSL RX 2",
672 .priority_high = 0,
673 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
674 .param.config = COH901318_CX_CFG_CH_DISABLE |
675 COH901318_CX_CFG_LCR_DISABLE |
676 COH901318_CX_CFG_TC_IRQ_ENABLE |
677 COH901318_CX_CFG_BE_IRQ_ENABLE,
678 .param.ctrl_lli_chained = 0 |
679 COH901318_CX_CTRL_TC_ENABLE |
680 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
681 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
682 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
683 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
684 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
685 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
686 COH901318_CX_CTRL_TCP_DISABLE |
687 COH901318_CX_CTRL_TC_IRQ_DISABLE |
688 COH901318_CX_CTRL_HSP_ENABLE |
689 COH901318_CX_CTRL_HSS_DISABLE |
690 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
691 COH901318_CX_CTRL_PRDD_DEST,
692 .param.ctrl_lli = 0 |
693 COH901318_CX_CTRL_TC_ENABLE |
694 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
695 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
696 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
697 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
698 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
699 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
700 COH901318_CX_CTRL_TCP_DISABLE |
701 COH901318_CX_CTRL_TC_IRQ_ENABLE |
702 COH901318_CX_CTRL_HSP_ENABLE |
703 COH901318_CX_CTRL_HSS_DISABLE |
704 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
705 COH901318_CX_CTRL_PRDD_DEST,
706 .param.ctrl_lli_last = 0 |
707 COH901318_CX_CTRL_TC_ENABLE |
708 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
709 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
710 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
711 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
713 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
714 COH901318_CX_CTRL_TCP_DISABLE |
715 COH901318_CX_CTRL_TC_IRQ_ENABLE |
716 COH901318_CX_CTRL_HSP_ENABLE |
717 COH901318_CX_CTRL_HSS_DISABLE |
718 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
719 COH901318_CX_CTRL_PRDD_DEST,
720 },
721 {
722 .number = U300_DMA_MSL_RX_3,
723 .name = "MSL RX 3",
724 .priority_high = 0,
725 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
726 .param.config = COH901318_CX_CFG_CH_DISABLE |
727 COH901318_CX_CFG_LCR_DISABLE |
728 COH901318_CX_CFG_TC_IRQ_ENABLE |
729 COH901318_CX_CFG_BE_IRQ_ENABLE,
730 .param.ctrl_lli_chained = 0 |
731 COH901318_CX_CTRL_TC_ENABLE |
732 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
733 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
734 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
735 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
736 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
737 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
738 COH901318_CX_CTRL_TCP_DISABLE |
739 COH901318_CX_CTRL_TC_IRQ_DISABLE |
740 COH901318_CX_CTRL_HSP_ENABLE |
741 COH901318_CX_CTRL_HSS_DISABLE |
742 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
743 COH901318_CX_CTRL_PRDD_DEST,
744 .param.ctrl_lli = 0 |
745 COH901318_CX_CTRL_TC_ENABLE |
746 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
747 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
748 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
749 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
750 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
751 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
752 COH901318_CX_CTRL_TCP_DISABLE |
753 COH901318_CX_CTRL_TC_IRQ_ENABLE |
754 COH901318_CX_CTRL_HSP_ENABLE |
755 COH901318_CX_CTRL_HSS_DISABLE |
756 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
757 COH901318_CX_CTRL_PRDD_DEST,
758 .param.ctrl_lli_last = 0 |
759 COH901318_CX_CTRL_TC_ENABLE |
760 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
761 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
762 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
763 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
764 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
765 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
766 COH901318_CX_CTRL_TCP_DISABLE |
767 COH901318_CX_CTRL_TC_IRQ_ENABLE |
768 COH901318_CX_CTRL_HSP_ENABLE |
769 COH901318_CX_CTRL_HSS_DISABLE |
770 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
771 COH901318_CX_CTRL_PRDD_DEST,
772 },
773 {
774 .number = U300_DMA_MSL_RX_4,
775 .name = "MSL RX 4",
776 .priority_high = 0,
777 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
778 .param.config = COH901318_CX_CFG_CH_DISABLE |
779 COH901318_CX_CFG_LCR_DISABLE |
780 COH901318_CX_CFG_TC_IRQ_ENABLE |
781 COH901318_CX_CFG_BE_IRQ_ENABLE,
782 .param.ctrl_lli_chained = 0 |
783 COH901318_CX_CTRL_TC_ENABLE |
784 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
785 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
786 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
787 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
788 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
789 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
790 COH901318_CX_CTRL_TCP_DISABLE |
791 COH901318_CX_CTRL_TC_IRQ_DISABLE |
792 COH901318_CX_CTRL_HSP_ENABLE |
793 COH901318_CX_CTRL_HSS_DISABLE |
794 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
795 COH901318_CX_CTRL_PRDD_DEST,
796 .param.ctrl_lli = 0 |
797 COH901318_CX_CTRL_TC_ENABLE |
798 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
799 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
800 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
801 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
802 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
803 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
804 COH901318_CX_CTRL_TCP_DISABLE |
805 COH901318_CX_CTRL_TC_IRQ_ENABLE |
806 COH901318_CX_CTRL_HSP_ENABLE |
807 COH901318_CX_CTRL_HSS_DISABLE |
808 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
809 COH901318_CX_CTRL_PRDD_DEST,
810 .param.ctrl_lli_last = 0 |
811 COH901318_CX_CTRL_TC_ENABLE |
812 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
813 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
814 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
815 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
816 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
817 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
818 COH901318_CX_CTRL_TCP_DISABLE |
819 COH901318_CX_CTRL_TC_IRQ_ENABLE |
820 COH901318_CX_CTRL_HSP_ENABLE |
821 COH901318_CX_CTRL_HSS_DISABLE |
822 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
823 COH901318_CX_CTRL_PRDD_DEST,
824 },
825 {
826 .number = U300_DMA_MSL_RX_5,
827 .name = "MSL RX 5",
828 .priority_high = 0,
829 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
830 .param.config = COH901318_CX_CFG_CH_DISABLE |
831 COH901318_CX_CFG_LCR_DISABLE |
832 COH901318_CX_CFG_TC_IRQ_ENABLE |
833 COH901318_CX_CFG_BE_IRQ_ENABLE,
834 .param.ctrl_lli_chained = 0 |
835 COH901318_CX_CTRL_TC_ENABLE |
836 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
837 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
838 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
839 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
840 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
841 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
842 COH901318_CX_CTRL_TCP_DISABLE |
843 COH901318_CX_CTRL_TC_IRQ_DISABLE |
844 COH901318_CX_CTRL_HSP_ENABLE |
845 COH901318_CX_CTRL_HSS_DISABLE |
846 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
847 COH901318_CX_CTRL_PRDD_DEST,
848 .param.ctrl_lli = 0 |
849 COH901318_CX_CTRL_TC_ENABLE |
850 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
851 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
852 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
853 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
854 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
855 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
856 COH901318_CX_CTRL_TCP_DISABLE |
857 COH901318_CX_CTRL_TC_IRQ_ENABLE |
858 COH901318_CX_CTRL_HSP_ENABLE |
859 COH901318_CX_CTRL_HSS_DISABLE |
860 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
861 COH901318_CX_CTRL_PRDD_DEST,
862 .param.ctrl_lli_last = 0 |
863 COH901318_CX_CTRL_TC_ENABLE |
864 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
865 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
866 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
867 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
868 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
869 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
870 COH901318_CX_CTRL_TCP_DISABLE |
871 COH901318_CX_CTRL_TC_IRQ_ENABLE |
872 COH901318_CX_CTRL_HSP_ENABLE |
873 COH901318_CX_CTRL_HSS_DISABLE |
874 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
875 COH901318_CX_CTRL_PRDD_DEST,
876 },
877 {
878 .number = U300_DMA_MSL_RX_6,
879 .name = "MSL RX 6",
880 .priority_high = 0,
881 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
882 },
883 /*
884 * Don't set up device address, burst count or size of src
885 * or dst bus for this peripheral - handled by PrimeCell
886 * DMA extension.
887 */
888 {
889 .number = U300_DMA_MMCSD_RX_TX,
890 .name = "MMCSD RX TX",
891 .priority_high = 0,
892 .param.config = COH901318_CX_CFG_CH_DISABLE |
893 COH901318_CX_CFG_LCR_DISABLE |
894 COH901318_CX_CFG_TC_IRQ_ENABLE |
895 COH901318_CX_CFG_BE_IRQ_ENABLE,
896 .param.ctrl_lli_chained = 0 |
897 COH901318_CX_CTRL_TC_ENABLE |
898 COH901318_CX_CTRL_MASTER_MODE_M1RW |
899 COH901318_CX_CTRL_TCP_ENABLE |
900 COH901318_CX_CTRL_TC_IRQ_DISABLE |
901 COH901318_CX_CTRL_HSP_ENABLE |
902 COH901318_CX_CTRL_HSS_DISABLE |
903 COH901318_CX_CTRL_DDMA_LEGACY,
904 .param.ctrl_lli = 0 |
905 COH901318_CX_CTRL_TC_ENABLE |
906 COH901318_CX_CTRL_MASTER_MODE_M1RW |
907 COH901318_CX_CTRL_TCP_ENABLE |
908 COH901318_CX_CTRL_TC_IRQ_DISABLE |
909 COH901318_CX_CTRL_HSP_ENABLE |
910 COH901318_CX_CTRL_HSS_DISABLE |
911 COH901318_CX_CTRL_DDMA_LEGACY,
912 .param.ctrl_lli_last = 0 |
913 COH901318_CX_CTRL_TC_ENABLE |
914 COH901318_CX_CTRL_MASTER_MODE_M1RW |
915 COH901318_CX_CTRL_TCP_DISABLE |
916 COH901318_CX_CTRL_TC_IRQ_ENABLE |
917 COH901318_CX_CTRL_HSP_ENABLE |
918 COH901318_CX_CTRL_HSS_DISABLE |
919 COH901318_CX_CTRL_DDMA_LEGACY,
920
921 },
922 {
923 .number = U300_DMA_MSPRO_TX,
924 .name = "MSPRO TX",
925 .priority_high = 0,
926 },
927 {
928 .number = U300_DMA_MSPRO_RX,
929 .name = "MSPRO RX",
930 .priority_high = 0,
931 },
932 /*
933 * Don't set up device address, burst count or size of src
934 * or dst bus for this peripheral - handled by PrimeCell
935 * DMA extension.
936 */
937 {
938 .number = U300_DMA_UART0_TX,
939 .name = "UART0 TX",
940 .priority_high = 0,
941 .param.config = COH901318_CX_CFG_CH_DISABLE |
942 COH901318_CX_CFG_LCR_DISABLE |
943 COH901318_CX_CFG_TC_IRQ_ENABLE |
944 COH901318_CX_CFG_BE_IRQ_ENABLE,
945 .param.ctrl_lli_chained = 0 |
946 COH901318_CX_CTRL_TC_ENABLE |
947 COH901318_CX_CTRL_MASTER_MODE_M1RW |
948 COH901318_CX_CTRL_TCP_ENABLE |
949 COH901318_CX_CTRL_TC_IRQ_DISABLE |
950 COH901318_CX_CTRL_HSP_ENABLE |
951 COH901318_CX_CTRL_HSS_DISABLE |
952 COH901318_CX_CTRL_DDMA_LEGACY,
953 .param.ctrl_lli = 0 |
954 COH901318_CX_CTRL_TC_ENABLE |
955 COH901318_CX_CTRL_MASTER_MODE_M1RW |
956 COH901318_CX_CTRL_TCP_ENABLE |
957 COH901318_CX_CTRL_TC_IRQ_ENABLE |
958 COH901318_CX_CTRL_HSP_ENABLE |
959 COH901318_CX_CTRL_HSS_DISABLE |
960 COH901318_CX_CTRL_DDMA_LEGACY,
961 .param.ctrl_lli_last = 0 |
962 COH901318_CX_CTRL_TC_ENABLE |
963 COH901318_CX_CTRL_MASTER_MODE_M1RW |
964 COH901318_CX_CTRL_TCP_ENABLE |
965 COH901318_CX_CTRL_TC_IRQ_ENABLE |
966 COH901318_CX_CTRL_HSP_ENABLE |
967 COH901318_CX_CTRL_HSS_DISABLE |
968 COH901318_CX_CTRL_DDMA_LEGACY,
969 },
970 {
971 .number = U300_DMA_UART0_RX,
972 .name = "UART0 RX",
973 .priority_high = 0,
974 .param.config = COH901318_CX_CFG_CH_DISABLE |
975 COH901318_CX_CFG_LCR_DISABLE |
976 COH901318_CX_CFG_TC_IRQ_ENABLE |
977 COH901318_CX_CFG_BE_IRQ_ENABLE,
978 .param.ctrl_lli_chained = 0 |
979 COH901318_CX_CTRL_TC_ENABLE |
980 COH901318_CX_CTRL_MASTER_MODE_M1RW |
981 COH901318_CX_CTRL_TCP_ENABLE |
982 COH901318_CX_CTRL_TC_IRQ_DISABLE |
983 COH901318_CX_CTRL_HSP_ENABLE |
984 COH901318_CX_CTRL_HSS_DISABLE |
985 COH901318_CX_CTRL_DDMA_LEGACY,
986 .param.ctrl_lli = 0 |
987 COH901318_CX_CTRL_TC_ENABLE |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_ENABLE |
990 COH901318_CX_CTRL_TC_IRQ_ENABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY,
994 .param.ctrl_lli_last = 0 |
995 COH901318_CX_CTRL_TC_ENABLE |
996 COH901318_CX_CTRL_MASTER_MODE_M1RW |
997 COH901318_CX_CTRL_TCP_ENABLE |
998 COH901318_CX_CTRL_TC_IRQ_ENABLE |
999 COH901318_CX_CTRL_HSP_ENABLE |
1000 COH901318_CX_CTRL_HSS_DISABLE |
1001 COH901318_CX_CTRL_DDMA_LEGACY,
1002 },
1003 {
1004 .number = U300_DMA_APEX_TX,
1005 .name = "APEX TX",
1006 .priority_high = 0,
1007 },
1008 {
1009 .number = U300_DMA_APEX_RX,
1010 .name = "APEX RX",
1011 .priority_high = 0,
1012 },
1013 {
1014 .number = U300_DMA_PCM_I2S0_TX,
1015 .name = "PCM I2S0 TX",
1016 .priority_high = 1,
1017 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1018 .param.config = COH901318_CX_CFG_CH_DISABLE |
1019 COH901318_CX_CFG_LCR_DISABLE |
1020 COH901318_CX_CFG_TC_IRQ_ENABLE |
1021 COH901318_CX_CFG_BE_IRQ_ENABLE,
1022 .param.ctrl_lli_chained = 0 |
1023 COH901318_CX_CTRL_TC_ENABLE |
1024 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1025 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1026 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1027 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1028 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1029 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1030 COH901318_CX_CTRL_TCP_DISABLE |
1031 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1032 COH901318_CX_CTRL_HSP_ENABLE |
1033 COH901318_CX_CTRL_HSS_DISABLE |
1034 COH901318_CX_CTRL_DDMA_LEGACY |
1035 COH901318_CX_CTRL_PRDD_SOURCE,
1036 .param.ctrl_lli = 0 |
1037 COH901318_CX_CTRL_TC_ENABLE |
1038 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1039 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1040 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1041 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1042 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1043 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1044 COH901318_CX_CTRL_TCP_ENABLE |
1045 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1046 COH901318_CX_CTRL_HSP_ENABLE |
1047 COH901318_CX_CTRL_HSS_DISABLE |
1048 COH901318_CX_CTRL_DDMA_LEGACY |
1049 COH901318_CX_CTRL_PRDD_SOURCE,
1050 .param.ctrl_lli_last = 0 |
1051 COH901318_CX_CTRL_TC_ENABLE |
1052 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1053 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1054 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1055 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1056 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1057 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1058 COH901318_CX_CTRL_TCP_ENABLE |
1059 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1060 COH901318_CX_CTRL_HSP_ENABLE |
1061 COH901318_CX_CTRL_HSS_DISABLE |
1062 COH901318_CX_CTRL_DDMA_LEGACY |
1063 COH901318_CX_CTRL_PRDD_SOURCE,
1064 },
1065 {
1066 .number = U300_DMA_PCM_I2S0_RX,
1067 .name = "PCM I2S0 RX",
1068 .priority_high = 1,
1069 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1070 .param.config = COH901318_CX_CFG_CH_DISABLE |
1071 COH901318_CX_CFG_LCR_DISABLE |
1072 COH901318_CX_CFG_TC_IRQ_ENABLE |
1073 COH901318_CX_CFG_BE_IRQ_ENABLE,
1074 .param.ctrl_lli_chained = 0 |
1075 COH901318_CX_CTRL_TC_ENABLE |
1076 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1077 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1078 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1079 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1080 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_DISABLE |
1083 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY |
1087 COH901318_CX_CTRL_PRDD_DEST,
1088 .param.ctrl_lli = 0 |
1089 COH901318_CX_CTRL_TC_ENABLE |
1090 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1091 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1092 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1093 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1094 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1095 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1096 COH901318_CX_CTRL_TCP_ENABLE |
1097 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1098 COH901318_CX_CTRL_HSP_ENABLE |
1099 COH901318_CX_CTRL_HSS_DISABLE |
1100 COH901318_CX_CTRL_DDMA_LEGACY |
1101 COH901318_CX_CTRL_PRDD_DEST,
1102 .param.ctrl_lli_last = 0 |
1103 COH901318_CX_CTRL_TC_ENABLE |
1104 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1105 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1106 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1107 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1108 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1109 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1110 COH901318_CX_CTRL_TCP_ENABLE |
1111 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1112 COH901318_CX_CTRL_HSP_ENABLE |
1113 COH901318_CX_CTRL_HSS_DISABLE |
1114 COH901318_CX_CTRL_DDMA_LEGACY |
1115 COH901318_CX_CTRL_PRDD_DEST,
1116 },
1117 {
1118 .number = U300_DMA_PCM_I2S1_TX,
1119 .name = "PCM I2S1 TX",
1120 .priority_high = 1,
1121 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1122 .param.config = COH901318_CX_CFG_CH_DISABLE |
1123 COH901318_CX_CFG_LCR_DISABLE |
1124 COH901318_CX_CFG_TC_IRQ_ENABLE |
1125 COH901318_CX_CFG_BE_IRQ_ENABLE,
1126 .param.ctrl_lli_chained = 0 |
1127 COH901318_CX_CTRL_TC_ENABLE |
1128 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1129 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1130 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1131 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1132 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1133 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134 COH901318_CX_CTRL_TCP_DISABLE |
1135 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1136 COH901318_CX_CTRL_HSP_ENABLE |
1137 COH901318_CX_CTRL_HSS_DISABLE |
1138 COH901318_CX_CTRL_DDMA_LEGACY |
1139 COH901318_CX_CTRL_PRDD_SOURCE,
1140 .param.ctrl_lli = 0 |
1141 COH901318_CX_CTRL_TC_ENABLE |
1142 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1143 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1144 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1145 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1146 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1147 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1148 COH901318_CX_CTRL_TCP_ENABLE |
1149 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1150 COH901318_CX_CTRL_HSP_ENABLE |
1151 COH901318_CX_CTRL_HSS_DISABLE |
1152 COH901318_CX_CTRL_DDMA_LEGACY |
1153 COH901318_CX_CTRL_PRDD_SOURCE,
1154 .param.ctrl_lli_last = 0 |
1155 COH901318_CX_CTRL_TC_ENABLE |
1156 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1157 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1158 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1159 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1160 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1161 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1162 COH901318_CX_CTRL_TCP_ENABLE |
1163 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1164 COH901318_CX_CTRL_HSP_ENABLE |
1165 COH901318_CX_CTRL_HSS_DISABLE |
1166 COH901318_CX_CTRL_DDMA_LEGACY |
1167 COH901318_CX_CTRL_PRDD_SOURCE,
1168 },
1169 {
1170 .number = U300_DMA_PCM_I2S1_RX,
1171 .name = "PCM I2S1 RX",
1172 .priority_high = 1,
1173 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1174 .param.config = COH901318_CX_CFG_CH_DISABLE |
1175 COH901318_CX_CFG_LCR_DISABLE |
1176 COH901318_CX_CFG_TC_IRQ_ENABLE |
1177 COH901318_CX_CFG_BE_IRQ_ENABLE,
1178 .param.ctrl_lli_chained = 0 |
1179 COH901318_CX_CTRL_TC_ENABLE |
1180 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1181 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1182 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1183 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1184 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1185 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1186 COH901318_CX_CTRL_TCP_DISABLE |
1187 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1188 COH901318_CX_CTRL_HSP_ENABLE |
1189 COH901318_CX_CTRL_HSS_DISABLE |
1190 COH901318_CX_CTRL_DDMA_LEGACY |
1191 COH901318_CX_CTRL_PRDD_DEST,
1192 .param.ctrl_lli = 0 |
1193 COH901318_CX_CTRL_TC_ENABLE |
1194 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1195 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1196 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1197 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1198 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1199 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1200 COH901318_CX_CTRL_TCP_ENABLE |
1201 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1202 COH901318_CX_CTRL_HSP_ENABLE |
1203 COH901318_CX_CTRL_HSS_DISABLE |
1204 COH901318_CX_CTRL_DDMA_LEGACY |
1205 COH901318_CX_CTRL_PRDD_DEST,
1206 .param.ctrl_lli_last = 0 |
1207 COH901318_CX_CTRL_TC_ENABLE |
1208 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1209 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1210 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1211 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1212 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1213 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1214 COH901318_CX_CTRL_TCP_ENABLE |
1215 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1216 COH901318_CX_CTRL_HSP_ENABLE |
1217 COH901318_CX_CTRL_HSS_DISABLE |
1218 COH901318_CX_CTRL_DDMA_LEGACY |
1219 COH901318_CX_CTRL_PRDD_DEST,
1220 },
1221 {
1222 .number = U300_DMA_XGAM_CDI,
1223 .name = "XGAM CDI",
1224 .priority_high = 0,
1225 },
1226 {
1227 .number = U300_DMA_XGAM_PDI,
1228 .name = "XGAM PDI",
1229 .priority_high = 0,
1230 },
1231 /*
1232 * Don't set up device address, burst count or size of src
1233 * or dst bus for this peripheral - handled by PrimeCell
1234 * DMA extension.
1235 */
1236 {
1237 .number = U300_DMA_SPI_TX,
1238 .name = "SPI TX",
1239 .priority_high = 0,
1240 .param.config = COH901318_CX_CFG_CH_DISABLE |
1241 COH901318_CX_CFG_LCR_DISABLE |
1242 COH901318_CX_CFG_TC_IRQ_ENABLE |
1243 COH901318_CX_CFG_BE_IRQ_ENABLE,
1244 .param.ctrl_lli_chained = 0 |
1245 COH901318_CX_CTRL_TC_ENABLE |
1246 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1247 COH901318_CX_CTRL_TCP_DISABLE |
1248 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1249 COH901318_CX_CTRL_HSP_ENABLE |
1250 COH901318_CX_CTRL_HSS_DISABLE |
1251 COH901318_CX_CTRL_DDMA_LEGACY,
1252 .param.ctrl_lli = 0 |
1253 COH901318_CX_CTRL_TC_ENABLE |
1254 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1255 COH901318_CX_CTRL_TCP_DISABLE |
1256 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1257 COH901318_CX_CTRL_HSP_ENABLE |
1258 COH901318_CX_CTRL_HSS_DISABLE |
1259 COH901318_CX_CTRL_DDMA_LEGACY,
1260 .param.ctrl_lli_last = 0 |
1261 COH901318_CX_CTRL_TC_ENABLE |
1262 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1263 COH901318_CX_CTRL_TCP_DISABLE |
1264 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1265 COH901318_CX_CTRL_HSP_ENABLE |
1266 COH901318_CX_CTRL_HSS_DISABLE |
1267 COH901318_CX_CTRL_DDMA_LEGACY,
1268 },
1269 {
1270 .number = U300_DMA_SPI_RX,
1271 .name = "SPI RX",
1272 .priority_high = 0,
1273 .param.config = COH901318_CX_CFG_CH_DISABLE |
1274 COH901318_CX_CFG_LCR_DISABLE |
1275 COH901318_CX_CFG_TC_IRQ_ENABLE |
1276 COH901318_CX_CFG_BE_IRQ_ENABLE,
1277 .param.ctrl_lli_chained = 0 |
1278 COH901318_CX_CTRL_TC_ENABLE |
1279 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1280 COH901318_CX_CTRL_TCP_DISABLE |
1281 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1282 COH901318_CX_CTRL_HSP_ENABLE |
1283 COH901318_CX_CTRL_HSS_DISABLE |
1284 COH901318_CX_CTRL_DDMA_LEGACY,
1285 .param.ctrl_lli = 0 |
1286 COH901318_CX_CTRL_TC_ENABLE |
1287 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1288 COH901318_CX_CTRL_TCP_DISABLE |
1289 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1290 COH901318_CX_CTRL_HSP_ENABLE |
1291 COH901318_CX_CTRL_HSS_DISABLE |
1292 COH901318_CX_CTRL_DDMA_LEGACY,
1293 .param.ctrl_lli_last = 0 |
1294 COH901318_CX_CTRL_TC_ENABLE |
1295 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1296 COH901318_CX_CTRL_TCP_DISABLE |
1297 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1298 COH901318_CX_CTRL_HSP_ENABLE |
1299 COH901318_CX_CTRL_HSS_DISABLE |
1300 COH901318_CX_CTRL_DDMA_LEGACY,
1301
1302 },
1303 {
1304 .number = U300_DMA_GENERAL_PURPOSE_0,
1305 .name = "GENERAL 00",
1306 .priority_high = 0,
1307
1308 .param.config = flags_memcpy_config,
1309 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1310 .param.ctrl_lli = flags_memcpy_lli,
1311 .param.ctrl_lli_last = flags_memcpy_lli_last,
1312 },
1313 {
1314 .number = U300_DMA_GENERAL_PURPOSE_1,
1315 .name = "GENERAL 01",
1316 .priority_high = 0,
1317
1318 .param.config = flags_memcpy_config,
1319 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1320 .param.ctrl_lli = flags_memcpy_lli,
1321 .param.ctrl_lli_last = flags_memcpy_lli_last,
1322 },
1323 {
1324 .number = U300_DMA_GENERAL_PURPOSE_2,
1325 .name = "GENERAL 02",
1326 .priority_high = 0,
1327
1328 .param.config = flags_memcpy_config,
1329 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1330 .param.ctrl_lli = flags_memcpy_lli,
1331 .param.ctrl_lli_last = flags_memcpy_lli_last,
1332 },
1333 {
1334 .number = U300_DMA_GENERAL_PURPOSE_3,
1335 .name = "GENERAL 03",
1336 .priority_high = 0,
1337
1338 .param.config = flags_memcpy_config,
1339 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1340 .param.ctrl_lli = flags_memcpy_lli,
1341 .param.ctrl_lli_last = flags_memcpy_lli_last,
1342 },
1343 {
1344 .number = U300_DMA_GENERAL_PURPOSE_4,
1345 .name = "GENERAL 04",
1346 .priority_high = 0,
1347
1348 .param.config = flags_memcpy_config,
1349 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1350 .param.ctrl_lli = flags_memcpy_lli,
1351 .param.ctrl_lli_last = flags_memcpy_lli_last,
1352 },
1353 {
1354 .number = U300_DMA_GENERAL_PURPOSE_5,
1355 .name = "GENERAL 05",
1356 .priority_high = 0,
1357
1358 .param.config = flags_memcpy_config,
1359 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1360 .param.ctrl_lli = flags_memcpy_lli,
1361 .param.ctrl_lli_last = flags_memcpy_lli_last,
1362 },
1363 {
1364 .number = U300_DMA_GENERAL_PURPOSE_6,
1365 .name = "GENERAL 06",
1366 .priority_high = 0,
1367
1368 .param.config = flags_memcpy_config,
1369 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1370 .param.ctrl_lli = flags_memcpy_lli,
1371 .param.ctrl_lli_last = flags_memcpy_lli_last,
1372 },
1373 {
1374 .number = U300_DMA_GENERAL_PURPOSE_7,
1375 .name = "GENERAL 07",
1376 .priority_high = 0,
1377
1378 .param.config = flags_memcpy_config,
1379 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1380 .param.ctrl_lli = flags_memcpy_lli,
1381 .param.ctrl_lli_last = flags_memcpy_lli_last,
1382 },
1383 {
1384 .number = U300_DMA_GENERAL_PURPOSE_8,
1385 .name = "GENERAL 08",
1386 .priority_high = 0,
1387
1388 .param.config = flags_memcpy_config,
1389 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1390 .param.ctrl_lli = flags_memcpy_lli,
1391 .param.ctrl_lli_last = flags_memcpy_lli_last,
1392 },
1393 {
1394 .number = U300_DMA_UART1_TX,
1395 .name = "UART1 TX",
1396 .priority_high = 0,
1397 },
1398 {
1399 .number = U300_DMA_UART1_RX,
1400 .name = "UART1 RX",
1401 .priority_high = 0,
1402 }
1403};
1404
1405
1406static struct coh901318_platform coh901318_platform = {
1407 .chans_slave = dma_slave_channels,
1408 .chans_memcpy = dma_memcpy_channels,
1409 .access_memory_state = coh901318_access_memory_state,
1410 .chan_conf = chan_config,
1411 .max_channels = U300_DMA_CHANNELS,
1412};
1413 330
1414static struct resource pinctrl_resources[] = { 331static struct resource pinctrl_resources[] = {
1415 { 332 {
@@ -1521,7 +438,6 @@ static struct platform_device dma_device = {
1521 .resource = dma_resource, 438 .resource = dma_resource,
1522 .num_resources = ARRAY_SIZE(dma_resource), 439 .num_resources = ARRAY_SIZE(dma_resource),
1523 .dev = { 440 .dev = {
1524 .platform_data = &coh901318_platform,
1525 .coherent_dma_mask = ~0, 441 .coherent_dma_mask = ~0,
1526 }, 442 },
1527}; 443};
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 5fdd38bcda23..06d97955c544 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -23,10 +23,1094 @@
23#include <linux/debugfs.h> 23#include <linux/debugfs.h>
24#include <linux/platform_data/dma-coh901318.h> 24#include <linux/platform_data/dma-coh901318.h>
25#include <mach/coh901318.h> 25#include <mach/coh901318.h>
26#include <mach/u300-regs.h>
26 27
27#include "coh901318_lli.h" 28#include "coh901318_lli.h"
28#include "dmaengine.h" 29#include "dmaengine.h"
29 30
31/* points out all dma slave channels.
32 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
33 * Select all channels from A to B, end of list is marked with -1,-1
34 */
35static int dma_slave_channels[] = {
36 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
37 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
38
39/* points out all dma memcpy channels. */
40static int dma_memcpy_channels[] = {
41 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
42
43/** register dma for memory access
44 *
45 * active 1 means dma intends to access memory
46 * 0 means dma wont access memory
47 */
48static void coh901318_access_memory_state(struct device *dev, bool active)
49{
50}
51
52#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
53 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
54 COH901318_CX_CFG_LCR_DISABLE | \
55 COH901318_CX_CFG_TC_IRQ_ENABLE | \
56 COH901318_CX_CFG_BE_IRQ_ENABLE)
57#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
58 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
59 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
60 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
61 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
62 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
63 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
64 COH901318_CX_CTRL_TCP_DISABLE | \
65 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
66 COH901318_CX_CTRL_HSP_DISABLE | \
67 COH901318_CX_CTRL_HSS_DISABLE | \
68 COH901318_CX_CTRL_DDMA_LEGACY | \
69 COH901318_CX_CTRL_PRDD_SOURCE)
70#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
71 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
72 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
73 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
74 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
75 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
76 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
77 COH901318_CX_CTRL_TCP_DISABLE | \
78 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
79 COH901318_CX_CTRL_HSP_DISABLE | \
80 COH901318_CX_CTRL_HSS_DISABLE | \
81 COH901318_CX_CTRL_DDMA_LEGACY | \
82 COH901318_CX_CTRL_PRDD_SOURCE)
83#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
84 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
85 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
86 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
87 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
88 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
89 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
90 COH901318_CX_CTRL_TCP_DISABLE | \
91 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
92 COH901318_CX_CTRL_HSP_DISABLE | \
93 COH901318_CX_CTRL_HSS_DISABLE | \
94 COH901318_CX_CTRL_DDMA_LEGACY | \
95 COH901318_CX_CTRL_PRDD_SOURCE)
96
97const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
98 {
99 .number = U300_DMA_MSL_TX_0,
100 .name = "MSL TX 0",
101 .priority_high = 0,
102 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
103 },
104 {
105 .number = U300_DMA_MSL_TX_1,
106 .name = "MSL TX 1",
107 .priority_high = 0,
108 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
109 .param.config = COH901318_CX_CFG_CH_DISABLE |
110 COH901318_CX_CFG_LCR_DISABLE |
111 COH901318_CX_CFG_TC_IRQ_ENABLE |
112 COH901318_CX_CFG_BE_IRQ_ENABLE,
113 .param.ctrl_lli_chained = 0 |
114 COH901318_CX_CTRL_TC_ENABLE |
115 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
116 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
117 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
118 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
119 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
120 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
121 COH901318_CX_CTRL_TCP_DISABLE |
122 COH901318_CX_CTRL_TC_IRQ_DISABLE |
123 COH901318_CX_CTRL_HSP_ENABLE |
124 COH901318_CX_CTRL_HSS_DISABLE |
125 COH901318_CX_CTRL_DDMA_LEGACY |
126 COH901318_CX_CTRL_PRDD_SOURCE,
127 .param.ctrl_lli = 0 |
128 COH901318_CX_CTRL_TC_ENABLE |
129 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
130 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
131 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
132 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
133 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
134 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
135 COH901318_CX_CTRL_TCP_ENABLE |
136 COH901318_CX_CTRL_TC_IRQ_DISABLE |
137 COH901318_CX_CTRL_HSP_ENABLE |
138 COH901318_CX_CTRL_HSS_DISABLE |
139 COH901318_CX_CTRL_DDMA_LEGACY |
140 COH901318_CX_CTRL_PRDD_SOURCE,
141 .param.ctrl_lli_last = 0 |
142 COH901318_CX_CTRL_TC_ENABLE |
143 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
144 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
145 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
146 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
147 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
148 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
149 COH901318_CX_CTRL_TCP_ENABLE |
150 COH901318_CX_CTRL_TC_IRQ_ENABLE |
151 COH901318_CX_CTRL_HSP_ENABLE |
152 COH901318_CX_CTRL_HSS_DISABLE |
153 COH901318_CX_CTRL_DDMA_LEGACY |
154 COH901318_CX_CTRL_PRDD_SOURCE,
155 },
156 {
157 .number = U300_DMA_MSL_TX_2,
158 .name = "MSL TX 2",
159 .priority_high = 0,
160 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
161 .param.config = COH901318_CX_CFG_CH_DISABLE |
162 COH901318_CX_CFG_LCR_DISABLE |
163 COH901318_CX_CFG_TC_IRQ_ENABLE |
164 COH901318_CX_CFG_BE_IRQ_ENABLE,
165 .param.ctrl_lli_chained = 0 |
166 COH901318_CX_CTRL_TC_ENABLE |
167 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
168 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
169 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
170 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
171 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
172 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
173 COH901318_CX_CTRL_TCP_DISABLE |
174 COH901318_CX_CTRL_TC_IRQ_DISABLE |
175 COH901318_CX_CTRL_HSP_ENABLE |
176 COH901318_CX_CTRL_HSS_DISABLE |
177 COH901318_CX_CTRL_DDMA_LEGACY |
178 COH901318_CX_CTRL_PRDD_SOURCE,
179 .param.ctrl_lli = 0 |
180 COH901318_CX_CTRL_TC_ENABLE |
181 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
182 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
183 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
184 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
185 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
186 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
187 COH901318_CX_CTRL_TCP_ENABLE |
188 COH901318_CX_CTRL_TC_IRQ_DISABLE |
189 COH901318_CX_CTRL_HSP_ENABLE |
190 COH901318_CX_CTRL_HSS_DISABLE |
191 COH901318_CX_CTRL_DDMA_LEGACY |
192 COH901318_CX_CTRL_PRDD_SOURCE,
193 .param.ctrl_lli_last = 0 |
194 COH901318_CX_CTRL_TC_ENABLE |
195 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
196 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
197 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
198 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
199 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
200 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
201 COH901318_CX_CTRL_TCP_ENABLE |
202 COH901318_CX_CTRL_TC_IRQ_ENABLE |
203 COH901318_CX_CTRL_HSP_ENABLE |
204 COH901318_CX_CTRL_HSS_DISABLE |
205 COH901318_CX_CTRL_DDMA_LEGACY |
206 COH901318_CX_CTRL_PRDD_SOURCE,
207 .desc_nbr_max = 10,
208 },
209 {
210 .number = U300_DMA_MSL_TX_3,
211 .name = "MSL TX 3",
212 .priority_high = 0,
213 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
214 .param.config = COH901318_CX_CFG_CH_DISABLE |
215 COH901318_CX_CFG_LCR_DISABLE |
216 COH901318_CX_CFG_TC_IRQ_ENABLE |
217 COH901318_CX_CFG_BE_IRQ_ENABLE,
218 .param.ctrl_lli_chained = 0 |
219 COH901318_CX_CTRL_TC_ENABLE |
220 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
221 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
222 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
223 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
224 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
225 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
226 COH901318_CX_CTRL_TCP_DISABLE |
227 COH901318_CX_CTRL_TC_IRQ_DISABLE |
228 COH901318_CX_CTRL_HSP_ENABLE |
229 COH901318_CX_CTRL_HSS_DISABLE |
230 COH901318_CX_CTRL_DDMA_LEGACY |
231 COH901318_CX_CTRL_PRDD_SOURCE,
232 .param.ctrl_lli = 0 |
233 COH901318_CX_CTRL_TC_ENABLE |
234 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
235 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
236 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
237 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
238 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
239 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
240 COH901318_CX_CTRL_TCP_ENABLE |
241 COH901318_CX_CTRL_TC_IRQ_DISABLE |
242 COH901318_CX_CTRL_HSP_ENABLE |
243 COH901318_CX_CTRL_HSS_DISABLE |
244 COH901318_CX_CTRL_DDMA_LEGACY |
245 COH901318_CX_CTRL_PRDD_SOURCE,
246 .param.ctrl_lli_last = 0 |
247 COH901318_CX_CTRL_TC_ENABLE |
248 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
249 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
250 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
251 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
252 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
253 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
254 COH901318_CX_CTRL_TCP_ENABLE |
255 COH901318_CX_CTRL_TC_IRQ_ENABLE |
256 COH901318_CX_CTRL_HSP_ENABLE |
257 COH901318_CX_CTRL_HSS_DISABLE |
258 COH901318_CX_CTRL_DDMA_LEGACY |
259 COH901318_CX_CTRL_PRDD_SOURCE,
260 },
261 {
262 .number = U300_DMA_MSL_TX_4,
263 .name = "MSL TX 4",
264 .priority_high = 0,
265 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
266 .param.config = COH901318_CX_CFG_CH_DISABLE |
267 COH901318_CX_CFG_LCR_DISABLE |
268 COH901318_CX_CFG_TC_IRQ_ENABLE |
269 COH901318_CX_CFG_BE_IRQ_ENABLE,
270 .param.ctrl_lli_chained = 0 |
271 COH901318_CX_CTRL_TC_ENABLE |
272 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
273 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
274 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
275 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
276 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
277 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
278 COH901318_CX_CTRL_TCP_DISABLE |
279 COH901318_CX_CTRL_TC_IRQ_DISABLE |
280 COH901318_CX_CTRL_HSP_ENABLE |
281 COH901318_CX_CTRL_HSS_DISABLE |
282 COH901318_CX_CTRL_DDMA_LEGACY |
283 COH901318_CX_CTRL_PRDD_SOURCE,
284 .param.ctrl_lli = 0 |
285 COH901318_CX_CTRL_TC_ENABLE |
286 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
287 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
288 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
289 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
290 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
291 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
292 COH901318_CX_CTRL_TCP_ENABLE |
293 COH901318_CX_CTRL_TC_IRQ_DISABLE |
294 COH901318_CX_CTRL_HSP_ENABLE |
295 COH901318_CX_CTRL_HSS_DISABLE |
296 COH901318_CX_CTRL_DDMA_LEGACY |
297 COH901318_CX_CTRL_PRDD_SOURCE,
298 .param.ctrl_lli_last = 0 |
299 COH901318_CX_CTRL_TC_ENABLE |
300 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
301 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
302 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
303 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
304 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
305 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
306 COH901318_CX_CTRL_TCP_ENABLE |
307 COH901318_CX_CTRL_TC_IRQ_ENABLE |
308 COH901318_CX_CTRL_HSP_ENABLE |
309 COH901318_CX_CTRL_HSS_DISABLE |
310 COH901318_CX_CTRL_DDMA_LEGACY |
311 COH901318_CX_CTRL_PRDD_SOURCE,
312 },
313 {
314 .number = U300_DMA_MSL_TX_5,
315 .name = "MSL TX 5",
316 .priority_high = 0,
317 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
318 },
319 {
320 .number = U300_DMA_MSL_TX_6,
321 .name = "MSL TX 6",
322 .priority_high = 0,
323 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
324 },
325 {
326 .number = U300_DMA_MSL_RX_0,
327 .name = "MSL RX 0",
328 .priority_high = 0,
329 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
330 },
331 {
332 .number = U300_DMA_MSL_RX_1,
333 .name = "MSL RX 1",
334 .priority_high = 0,
335 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
336 .param.config = COH901318_CX_CFG_CH_DISABLE |
337 COH901318_CX_CFG_LCR_DISABLE |
338 COH901318_CX_CFG_TC_IRQ_ENABLE |
339 COH901318_CX_CFG_BE_IRQ_ENABLE,
340 .param.ctrl_lli_chained = 0 |
341 COH901318_CX_CTRL_TC_ENABLE |
342 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
343 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
344 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
345 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
346 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
347 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
348 COH901318_CX_CTRL_TCP_DISABLE |
349 COH901318_CX_CTRL_TC_IRQ_DISABLE |
350 COH901318_CX_CTRL_HSP_ENABLE |
351 COH901318_CX_CTRL_HSS_DISABLE |
352 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
353 COH901318_CX_CTRL_PRDD_DEST,
354 .param.ctrl_lli = 0,
355 .param.ctrl_lli_last = 0 |
356 COH901318_CX_CTRL_TC_ENABLE |
357 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
358 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
359 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
360 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
361 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
362 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
363 COH901318_CX_CTRL_TCP_DISABLE |
364 COH901318_CX_CTRL_TC_IRQ_ENABLE |
365 COH901318_CX_CTRL_HSP_ENABLE |
366 COH901318_CX_CTRL_HSS_DISABLE |
367 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
368 COH901318_CX_CTRL_PRDD_DEST,
369 },
370 {
371 .number = U300_DMA_MSL_RX_2,
372 .name = "MSL RX 2",
373 .priority_high = 0,
374 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
375 .param.config = COH901318_CX_CFG_CH_DISABLE |
376 COH901318_CX_CFG_LCR_DISABLE |
377 COH901318_CX_CFG_TC_IRQ_ENABLE |
378 COH901318_CX_CFG_BE_IRQ_ENABLE,
379 .param.ctrl_lli_chained = 0 |
380 COH901318_CX_CTRL_TC_ENABLE |
381 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
382 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
383 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
384 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
385 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
386 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
387 COH901318_CX_CTRL_TCP_DISABLE |
388 COH901318_CX_CTRL_TC_IRQ_DISABLE |
389 COH901318_CX_CTRL_HSP_ENABLE |
390 COH901318_CX_CTRL_HSS_DISABLE |
391 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
392 COH901318_CX_CTRL_PRDD_DEST,
393 .param.ctrl_lli = 0 |
394 COH901318_CX_CTRL_TC_ENABLE |
395 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
396 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
397 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
398 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
399 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
400 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
401 COH901318_CX_CTRL_TCP_DISABLE |
402 COH901318_CX_CTRL_TC_IRQ_ENABLE |
403 COH901318_CX_CTRL_HSP_ENABLE |
404 COH901318_CX_CTRL_HSS_DISABLE |
405 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
406 COH901318_CX_CTRL_PRDD_DEST,
407 .param.ctrl_lli_last = 0 |
408 COH901318_CX_CTRL_TC_ENABLE |
409 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
410 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
411 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
412 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
413 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
414 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
415 COH901318_CX_CTRL_TCP_DISABLE |
416 COH901318_CX_CTRL_TC_IRQ_ENABLE |
417 COH901318_CX_CTRL_HSP_ENABLE |
418 COH901318_CX_CTRL_HSS_DISABLE |
419 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
420 COH901318_CX_CTRL_PRDD_DEST,
421 },
422 {
423 .number = U300_DMA_MSL_RX_3,
424 .name = "MSL RX 3",
425 .priority_high = 0,
426 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
427 .param.config = COH901318_CX_CFG_CH_DISABLE |
428 COH901318_CX_CFG_LCR_DISABLE |
429 COH901318_CX_CFG_TC_IRQ_ENABLE |
430 COH901318_CX_CFG_BE_IRQ_ENABLE,
431 .param.ctrl_lli_chained = 0 |
432 COH901318_CX_CTRL_TC_ENABLE |
433 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
434 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
435 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
436 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
437 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
438 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
439 COH901318_CX_CTRL_TCP_DISABLE |
440 COH901318_CX_CTRL_TC_IRQ_DISABLE |
441 COH901318_CX_CTRL_HSP_ENABLE |
442 COH901318_CX_CTRL_HSS_DISABLE |
443 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
444 COH901318_CX_CTRL_PRDD_DEST,
445 .param.ctrl_lli = 0 |
446 COH901318_CX_CTRL_TC_ENABLE |
447 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
448 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
449 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
450 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
451 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
452 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
453 COH901318_CX_CTRL_TCP_DISABLE |
454 COH901318_CX_CTRL_TC_IRQ_ENABLE |
455 COH901318_CX_CTRL_HSP_ENABLE |
456 COH901318_CX_CTRL_HSS_DISABLE |
457 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
458 COH901318_CX_CTRL_PRDD_DEST,
459 .param.ctrl_lli_last = 0 |
460 COH901318_CX_CTRL_TC_ENABLE |
461 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
462 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
463 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
464 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
465 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
466 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
467 COH901318_CX_CTRL_TCP_DISABLE |
468 COH901318_CX_CTRL_TC_IRQ_ENABLE |
469 COH901318_CX_CTRL_HSP_ENABLE |
470 COH901318_CX_CTRL_HSS_DISABLE |
471 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
472 COH901318_CX_CTRL_PRDD_DEST,
473 },
474 {
475 .number = U300_DMA_MSL_RX_4,
476 .name = "MSL RX 4",
477 .priority_high = 0,
478 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
479 .param.config = COH901318_CX_CFG_CH_DISABLE |
480 COH901318_CX_CFG_LCR_DISABLE |
481 COH901318_CX_CFG_TC_IRQ_ENABLE |
482 COH901318_CX_CFG_BE_IRQ_ENABLE,
483 .param.ctrl_lli_chained = 0 |
484 COH901318_CX_CTRL_TC_ENABLE |
485 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
486 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
487 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
488 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
489 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
490 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
491 COH901318_CX_CTRL_TCP_DISABLE |
492 COH901318_CX_CTRL_TC_IRQ_DISABLE |
493 COH901318_CX_CTRL_HSP_ENABLE |
494 COH901318_CX_CTRL_HSS_DISABLE |
495 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
496 COH901318_CX_CTRL_PRDD_DEST,
497 .param.ctrl_lli = 0 |
498 COH901318_CX_CTRL_TC_ENABLE |
499 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
500 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
501 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
502 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
503 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
504 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
505 COH901318_CX_CTRL_TCP_DISABLE |
506 COH901318_CX_CTRL_TC_IRQ_ENABLE |
507 COH901318_CX_CTRL_HSP_ENABLE |
508 COH901318_CX_CTRL_HSS_DISABLE |
509 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
510 COH901318_CX_CTRL_PRDD_DEST,
511 .param.ctrl_lli_last = 0 |
512 COH901318_CX_CTRL_TC_ENABLE |
513 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
514 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
515 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
516 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
517 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
518 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
519 COH901318_CX_CTRL_TCP_DISABLE |
520 COH901318_CX_CTRL_TC_IRQ_ENABLE |
521 COH901318_CX_CTRL_HSP_ENABLE |
522 COH901318_CX_CTRL_HSS_DISABLE |
523 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
524 COH901318_CX_CTRL_PRDD_DEST,
525 },
526 {
527 .number = U300_DMA_MSL_RX_5,
528 .name = "MSL RX 5",
529 .priority_high = 0,
530 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
531 .param.config = COH901318_CX_CFG_CH_DISABLE |
532 COH901318_CX_CFG_LCR_DISABLE |
533 COH901318_CX_CFG_TC_IRQ_ENABLE |
534 COH901318_CX_CFG_BE_IRQ_ENABLE,
535 .param.ctrl_lli_chained = 0 |
536 COH901318_CX_CTRL_TC_ENABLE |
537 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
538 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
539 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
540 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
541 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
542 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
543 COH901318_CX_CTRL_TCP_DISABLE |
544 COH901318_CX_CTRL_TC_IRQ_DISABLE |
545 COH901318_CX_CTRL_HSP_ENABLE |
546 COH901318_CX_CTRL_HSS_DISABLE |
547 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
548 COH901318_CX_CTRL_PRDD_DEST,
549 .param.ctrl_lli = 0 |
550 COH901318_CX_CTRL_TC_ENABLE |
551 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
552 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
553 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
554 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
555 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
556 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
557 COH901318_CX_CTRL_TCP_DISABLE |
558 COH901318_CX_CTRL_TC_IRQ_ENABLE |
559 COH901318_CX_CTRL_HSP_ENABLE |
560 COH901318_CX_CTRL_HSS_DISABLE |
561 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
562 COH901318_CX_CTRL_PRDD_DEST,
563 .param.ctrl_lli_last = 0 |
564 COH901318_CX_CTRL_TC_ENABLE |
565 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
566 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
567 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
568 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
569 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
570 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
571 COH901318_CX_CTRL_TCP_DISABLE |
572 COH901318_CX_CTRL_TC_IRQ_ENABLE |
573 COH901318_CX_CTRL_HSP_ENABLE |
574 COH901318_CX_CTRL_HSS_DISABLE |
575 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
576 COH901318_CX_CTRL_PRDD_DEST,
577 },
578 {
579 .number = U300_DMA_MSL_RX_6,
580 .name = "MSL RX 6",
581 .priority_high = 0,
582 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
583 },
584 /*
585 * Don't set up device address, burst count or size of src
586 * or dst bus for this peripheral - handled by PrimeCell
587 * DMA extension.
588 */
589 {
590 .number = U300_DMA_MMCSD_RX_TX,
591 .name = "MMCSD RX TX",
592 .priority_high = 0,
593 .param.config = COH901318_CX_CFG_CH_DISABLE |
594 COH901318_CX_CFG_LCR_DISABLE |
595 COH901318_CX_CFG_TC_IRQ_ENABLE |
596 COH901318_CX_CFG_BE_IRQ_ENABLE,
597 .param.ctrl_lli_chained = 0 |
598 COH901318_CX_CTRL_TC_ENABLE |
599 COH901318_CX_CTRL_MASTER_MODE_M1RW |
600 COH901318_CX_CTRL_TCP_ENABLE |
601 COH901318_CX_CTRL_TC_IRQ_DISABLE |
602 COH901318_CX_CTRL_HSP_ENABLE |
603 COH901318_CX_CTRL_HSS_DISABLE |
604 COH901318_CX_CTRL_DDMA_LEGACY,
605 .param.ctrl_lli = 0 |
606 COH901318_CX_CTRL_TC_ENABLE |
607 COH901318_CX_CTRL_MASTER_MODE_M1RW |
608 COH901318_CX_CTRL_TCP_ENABLE |
609 COH901318_CX_CTRL_TC_IRQ_DISABLE |
610 COH901318_CX_CTRL_HSP_ENABLE |
611 COH901318_CX_CTRL_HSS_DISABLE |
612 COH901318_CX_CTRL_DDMA_LEGACY,
613 .param.ctrl_lli_last = 0 |
614 COH901318_CX_CTRL_TC_ENABLE |
615 COH901318_CX_CTRL_MASTER_MODE_M1RW |
616 COH901318_CX_CTRL_TCP_DISABLE |
617 COH901318_CX_CTRL_TC_IRQ_ENABLE |
618 COH901318_CX_CTRL_HSP_ENABLE |
619 COH901318_CX_CTRL_HSS_DISABLE |
620 COH901318_CX_CTRL_DDMA_LEGACY,
621
622 },
623 {
624 .number = U300_DMA_MSPRO_TX,
625 .name = "MSPRO TX",
626 .priority_high = 0,
627 },
628 {
629 .number = U300_DMA_MSPRO_RX,
630 .name = "MSPRO RX",
631 .priority_high = 0,
632 },
633 /*
634 * Don't set up device address, burst count or size of src
635 * or dst bus for this peripheral - handled by PrimeCell
636 * DMA extension.
637 */
638 {
639 .number = U300_DMA_UART0_TX,
640 .name = "UART0 TX",
641 .priority_high = 0,
642 .param.config = COH901318_CX_CFG_CH_DISABLE |
643 COH901318_CX_CFG_LCR_DISABLE |
644 COH901318_CX_CFG_TC_IRQ_ENABLE |
645 COH901318_CX_CFG_BE_IRQ_ENABLE,
646 .param.ctrl_lli_chained = 0 |
647 COH901318_CX_CTRL_TC_ENABLE |
648 COH901318_CX_CTRL_MASTER_MODE_M1RW |
649 COH901318_CX_CTRL_TCP_ENABLE |
650 COH901318_CX_CTRL_TC_IRQ_DISABLE |
651 COH901318_CX_CTRL_HSP_ENABLE |
652 COH901318_CX_CTRL_HSS_DISABLE |
653 COH901318_CX_CTRL_DDMA_LEGACY,
654 .param.ctrl_lli = 0 |
655 COH901318_CX_CTRL_TC_ENABLE |
656 COH901318_CX_CTRL_MASTER_MODE_M1RW |
657 COH901318_CX_CTRL_TCP_ENABLE |
658 COH901318_CX_CTRL_TC_IRQ_ENABLE |
659 COH901318_CX_CTRL_HSP_ENABLE |
660 COH901318_CX_CTRL_HSS_DISABLE |
661 COH901318_CX_CTRL_DDMA_LEGACY,
662 .param.ctrl_lli_last = 0 |
663 COH901318_CX_CTRL_TC_ENABLE |
664 COH901318_CX_CTRL_MASTER_MODE_M1RW |
665 COH901318_CX_CTRL_TCP_ENABLE |
666 COH901318_CX_CTRL_TC_IRQ_ENABLE |
667 COH901318_CX_CTRL_HSP_ENABLE |
668 COH901318_CX_CTRL_HSS_DISABLE |
669 COH901318_CX_CTRL_DDMA_LEGACY,
670 },
671 {
672 .number = U300_DMA_UART0_RX,
673 .name = "UART0 RX",
674 .priority_high = 0,
675 .param.config = COH901318_CX_CFG_CH_DISABLE |
676 COH901318_CX_CFG_LCR_DISABLE |
677 COH901318_CX_CFG_TC_IRQ_ENABLE |
678 COH901318_CX_CFG_BE_IRQ_ENABLE,
679 .param.ctrl_lli_chained = 0 |
680 COH901318_CX_CTRL_TC_ENABLE |
681 COH901318_CX_CTRL_MASTER_MODE_M1RW |
682 COH901318_CX_CTRL_TCP_ENABLE |
683 COH901318_CX_CTRL_TC_IRQ_DISABLE |
684 COH901318_CX_CTRL_HSP_ENABLE |
685 COH901318_CX_CTRL_HSS_DISABLE |
686 COH901318_CX_CTRL_DDMA_LEGACY,
687 .param.ctrl_lli = 0 |
688 COH901318_CX_CTRL_TC_ENABLE |
689 COH901318_CX_CTRL_MASTER_MODE_M1RW |
690 COH901318_CX_CTRL_TCP_ENABLE |
691 COH901318_CX_CTRL_TC_IRQ_ENABLE |
692 COH901318_CX_CTRL_HSP_ENABLE |
693 COH901318_CX_CTRL_HSS_DISABLE |
694 COH901318_CX_CTRL_DDMA_LEGACY,
695 .param.ctrl_lli_last = 0 |
696 COH901318_CX_CTRL_TC_ENABLE |
697 COH901318_CX_CTRL_MASTER_MODE_M1RW |
698 COH901318_CX_CTRL_TCP_ENABLE |
699 COH901318_CX_CTRL_TC_IRQ_ENABLE |
700 COH901318_CX_CTRL_HSP_ENABLE |
701 COH901318_CX_CTRL_HSS_DISABLE |
702 COH901318_CX_CTRL_DDMA_LEGACY,
703 },
704 {
705 .number = U300_DMA_APEX_TX,
706 .name = "APEX TX",
707 .priority_high = 0,
708 },
709 {
710 .number = U300_DMA_APEX_RX,
711 .name = "APEX RX",
712 .priority_high = 0,
713 },
714 {
715 .number = U300_DMA_PCM_I2S0_TX,
716 .name = "PCM I2S0 TX",
717 .priority_high = 1,
718 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
719 .param.config = COH901318_CX_CFG_CH_DISABLE |
720 COH901318_CX_CFG_LCR_DISABLE |
721 COH901318_CX_CFG_TC_IRQ_ENABLE |
722 COH901318_CX_CFG_BE_IRQ_ENABLE,
723 .param.ctrl_lli_chained = 0 |
724 COH901318_CX_CTRL_TC_ENABLE |
725 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
726 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
727 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
728 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
729 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
730 COH901318_CX_CTRL_MASTER_MODE_M1RW |
731 COH901318_CX_CTRL_TCP_DISABLE |
732 COH901318_CX_CTRL_TC_IRQ_DISABLE |
733 COH901318_CX_CTRL_HSP_ENABLE |
734 COH901318_CX_CTRL_HSS_DISABLE |
735 COH901318_CX_CTRL_DDMA_LEGACY |
736 COH901318_CX_CTRL_PRDD_SOURCE,
737 .param.ctrl_lli = 0 |
738 COH901318_CX_CTRL_TC_ENABLE |
739 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
740 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
741 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
742 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
743 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
744 COH901318_CX_CTRL_MASTER_MODE_M1RW |
745 COH901318_CX_CTRL_TCP_ENABLE |
746 COH901318_CX_CTRL_TC_IRQ_DISABLE |
747 COH901318_CX_CTRL_HSP_ENABLE |
748 COH901318_CX_CTRL_HSS_DISABLE |
749 COH901318_CX_CTRL_DDMA_LEGACY |
750 COH901318_CX_CTRL_PRDD_SOURCE,
751 .param.ctrl_lli_last = 0 |
752 COH901318_CX_CTRL_TC_ENABLE |
753 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
754 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
755 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
756 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
757 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
758 COH901318_CX_CTRL_MASTER_MODE_M1RW |
759 COH901318_CX_CTRL_TCP_ENABLE |
760 COH901318_CX_CTRL_TC_IRQ_DISABLE |
761 COH901318_CX_CTRL_HSP_ENABLE |
762 COH901318_CX_CTRL_HSS_DISABLE |
763 COH901318_CX_CTRL_DDMA_LEGACY |
764 COH901318_CX_CTRL_PRDD_SOURCE,
765 },
766 {
767 .number = U300_DMA_PCM_I2S0_RX,
768 .name = "PCM I2S0 RX",
769 .priority_high = 1,
770 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
771 .param.config = COH901318_CX_CFG_CH_DISABLE |
772 COH901318_CX_CFG_LCR_DISABLE |
773 COH901318_CX_CFG_TC_IRQ_ENABLE |
774 COH901318_CX_CFG_BE_IRQ_ENABLE,
775 .param.ctrl_lli_chained = 0 |
776 COH901318_CX_CTRL_TC_ENABLE |
777 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
778 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
779 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
780 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
781 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
782 COH901318_CX_CTRL_MASTER_MODE_M1RW |
783 COH901318_CX_CTRL_TCP_DISABLE |
784 COH901318_CX_CTRL_TC_IRQ_DISABLE |
785 COH901318_CX_CTRL_HSP_ENABLE |
786 COH901318_CX_CTRL_HSS_DISABLE |
787 COH901318_CX_CTRL_DDMA_LEGACY |
788 COH901318_CX_CTRL_PRDD_DEST,
789 .param.ctrl_lli = 0 |
790 COH901318_CX_CTRL_TC_ENABLE |
791 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
792 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
793 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
794 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
795 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
796 COH901318_CX_CTRL_MASTER_MODE_M1RW |
797 COH901318_CX_CTRL_TCP_ENABLE |
798 COH901318_CX_CTRL_TC_IRQ_DISABLE |
799 COH901318_CX_CTRL_HSP_ENABLE |
800 COH901318_CX_CTRL_HSS_DISABLE |
801 COH901318_CX_CTRL_DDMA_LEGACY |
802 COH901318_CX_CTRL_PRDD_DEST,
803 .param.ctrl_lli_last = 0 |
804 COH901318_CX_CTRL_TC_ENABLE |
805 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
806 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
807 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
808 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
809 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
810 COH901318_CX_CTRL_MASTER_MODE_M1RW |
811 COH901318_CX_CTRL_TCP_ENABLE |
812 COH901318_CX_CTRL_TC_IRQ_ENABLE |
813 COH901318_CX_CTRL_HSP_ENABLE |
814 COH901318_CX_CTRL_HSS_DISABLE |
815 COH901318_CX_CTRL_DDMA_LEGACY |
816 COH901318_CX_CTRL_PRDD_DEST,
817 },
818 {
819 .number = U300_DMA_PCM_I2S1_TX,
820 .name = "PCM I2S1 TX",
821 .priority_high = 1,
822 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
823 .param.config = COH901318_CX_CFG_CH_DISABLE |
824 COH901318_CX_CFG_LCR_DISABLE |
825 COH901318_CX_CFG_TC_IRQ_ENABLE |
826 COH901318_CX_CFG_BE_IRQ_ENABLE,
827 .param.ctrl_lli_chained = 0 |
828 COH901318_CX_CTRL_TC_ENABLE |
829 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
830 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
831 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
832 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
833 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
834 COH901318_CX_CTRL_MASTER_MODE_M1RW |
835 COH901318_CX_CTRL_TCP_DISABLE |
836 COH901318_CX_CTRL_TC_IRQ_DISABLE |
837 COH901318_CX_CTRL_HSP_ENABLE |
838 COH901318_CX_CTRL_HSS_DISABLE |
839 COH901318_CX_CTRL_DDMA_LEGACY |
840 COH901318_CX_CTRL_PRDD_SOURCE,
841 .param.ctrl_lli = 0 |
842 COH901318_CX_CTRL_TC_ENABLE |
843 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
844 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
845 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
846 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
847 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
848 COH901318_CX_CTRL_MASTER_MODE_M1RW |
849 COH901318_CX_CTRL_TCP_ENABLE |
850 COH901318_CX_CTRL_TC_IRQ_DISABLE |
851 COH901318_CX_CTRL_HSP_ENABLE |
852 COH901318_CX_CTRL_HSS_DISABLE |
853 COH901318_CX_CTRL_DDMA_LEGACY |
854 COH901318_CX_CTRL_PRDD_SOURCE,
855 .param.ctrl_lli_last = 0 |
856 COH901318_CX_CTRL_TC_ENABLE |
857 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
858 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
859 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
860 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
861 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
862 COH901318_CX_CTRL_MASTER_MODE_M1RW |
863 COH901318_CX_CTRL_TCP_ENABLE |
864 COH901318_CX_CTRL_TC_IRQ_ENABLE |
865 COH901318_CX_CTRL_HSP_ENABLE |
866 COH901318_CX_CTRL_HSS_DISABLE |
867 COH901318_CX_CTRL_DDMA_LEGACY |
868 COH901318_CX_CTRL_PRDD_SOURCE,
869 },
870 {
871 .number = U300_DMA_PCM_I2S1_RX,
872 .name = "PCM I2S1 RX",
873 .priority_high = 1,
874 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
875 .param.config = COH901318_CX_CFG_CH_DISABLE |
876 COH901318_CX_CFG_LCR_DISABLE |
877 COH901318_CX_CFG_TC_IRQ_ENABLE |
878 COH901318_CX_CFG_BE_IRQ_ENABLE,
879 .param.ctrl_lli_chained = 0 |
880 COH901318_CX_CTRL_TC_ENABLE |
881 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
882 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
883 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
884 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
885 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
886 COH901318_CX_CTRL_MASTER_MODE_M1RW |
887 COH901318_CX_CTRL_TCP_DISABLE |
888 COH901318_CX_CTRL_TC_IRQ_DISABLE |
889 COH901318_CX_CTRL_HSP_ENABLE |
890 COH901318_CX_CTRL_HSS_DISABLE |
891 COH901318_CX_CTRL_DDMA_LEGACY |
892 COH901318_CX_CTRL_PRDD_DEST,
893 .param.ctrl_lli = 0 |
894 COH901318_CX_CTRL_TC_ENABLE |
895 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
896 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
897 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
898 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
899 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
900 COH901318_CX_CTRL_MASTER_MODE_M1RW |
901 COH901318_CX_CTRL_TCP_ENABLE |
902 COH901318_CX_CTRL_TC_IRQ_DISABLE |
903 COH901318_CX_CTRL_HSP_ENABLE |
904 COH901318_CX_CTRL_HSS_DISABLE |
905 COH901318_CX_CTRL_DDMA_LEGACY |
906 COH901318_CX_CTRL_PRDD_DEST,
907 .param.ctrl_lli_last = 0 |
908 COH901318_CX_CTRL_TC_ENABLE |
909 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
910 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
911 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
912 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
913 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
914 COH901318_CX_CTRL_MASTER_MODE_M1RW |
915 COH901318_CX_CTRL_TCP_ENABLE |
916 COH901318_CX_CTRL_TC_IRQ_ENABLE |
917 COH901318_CX_CTRL_HSP_ENABLE |
918 COH901318_CX_CTRL_HSS_DISABLE |
919 COH901318_CX_CTRL_DDMA_LEGACY |
920 COH901318_CX_CTRL_PRDD_DEST,
921 },
922 {
923 .number = U300_DMA_XGAM_CDI,
924 .name = "XGAM CDI",
925 .priority_high = 0,
926 },
927 {
928 .number = U300_DMA_XGAM_PDI,
929 .name = "XGAM PDI",
930 .priority_high = 0,
931 },
932 /*
933 * Don't set up device address, burst count or size of src
934 * or dst bus for this peripheral - handled by PrimeCell
935 * DMA extension.
936 */
937 {
938 .number = U300_DMA_SPI_TX,
939 .name = "SPI TX",
940 .priority_high = 0,
941 .param.config = COH901318_CX_CFG_CH_DISABLE |
942 COH901318_CX_CFG_LCR_DISABLE |
943 COH901318_CX_CFG_TC_IRQ_ENABLE |
944 COH901318_CX_CFG_BE_IRQ_ENABLE,
945 .param.ctrl_lli_chained = 0 |
946 COH901318_CX_CTRL_TC_ENABLE |
947 COH901318_CX_CTRL_MASTER_MODE_M1RW |
948 COH901318_CX_CTRL_TCP_DISABLE |
949 COH901318_CX_CTRL_TC_IRQ_DISABLE |
950 COH901318_CX_CTRL_HSP_ENABLE |
951 COH901318_CX_CTRL_HSS_DISABLE |
952 COH901318_CX_CTRL_DDMA_LEGACY,
953 .param.ctrl_lli = 0 |
954 COH901318_CX_CTRL_TC_ENABLE |
955 COH901318_CX_CTRL_MASTER_MODE_M1RW |
956 COH901318_CX_CTRL_TCP_DISABLE |
957 COH901318_CX_CTRL_TC_IRQ_ENABLE |
958 COH901318_CX_CTRL_HSP_ENABLE |
959 COH901318_CX_CTRL_HSS_DISABLE |
960 COH901318_CX_CTRL_DDMA_LEGACY,
961 .param.ctrl_lli_last = 0 |
962 COH901318_CX_CTRL_TC_ENABLE |
963 COH901318_CX_CTRL_MASTER_MODE_M1RW |
964 COH901318_CX_CTRL_TCP_DISABLE |
965 COH901318_CX_CTRL_TC_IRQ_ENABLE |
966 COH901318_CX_CTRL_HSP_ENABLE |
967 COH901318_CX_CTRL_HSS_DISABLE |
968 COH901318_CX_CTRL_DDMA_LEGACY,
969 },
970 {
971 .number = U300_DMA_SPI_RX,
972 .name = "SPI RX",
973 .priority_high = 0,
974 .param.config = COH901318_CX_CFG_CH_DISABLE |
975 COH901318_CX_CFG_LCR_DISABLE |
976 COH901318_CX_CFG_TC_IRQ_ENABLE |
977 COH901318_CX_CFG_BE_IRQ_ENABLE,
978 .param.ctrl_lli_chained = 0 |
979 COH901318_CX_CTRL_TC_ENABLE |
980 COH901318_CX_CTRL_MASTER_MODE_M1RW |
981 COH901318_CX_CTRL_TCP_DISABLE |
982 COH901318_CX_CTRL_TC_IRQ_DISABLE |
983 COH901318_CX_CTRL_HSP_ENABLE |
984 COH901318_CX_CTRL_HSS_DISABLE |
985 COH901318_CX_CTRL_DDMA_LEGACY,
986 .param.ctrl_lli = 0 |
987 COH901318_CX_CTRL_TC_ENABLE |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_DISABLE |
990 COH901318_CX_CTRL_TC_IRQ_ENABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY,
994 .param.ctrl_lli_last = 0 |
995 COH901318_CX_CTRL_TC_ENABLE |
996 COH901318_CX_CTRL_MASTER_MODE_M1RW |
997 COH901318_CX_CTRL_TCP_DISABLE |
998 COH901318_CX_CTRL_TC_IRQ_ENABLE |
999 COH901318_CX_CTRL_HSP_ENABLE |
1000 COH901318_CX_CTRL_HSS_DISABLE |
1001 COH901318_CX_CTRL_DDMA_LEGACY,
1002
1003 },
1004 {
1005 .number = U300_DMA_GENERAL_PURPOSE_0,
1006 .name = "GENERAL 00",
1007 .priority_high = 0,
1008
1009 .param.config = flags_memcpy_config,
1010 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1011 .param.ctrl_lli = flags_memcpy_lli,
1012 .param.ctrl_lli_last = flags_memcpy_lli_last,
1013 },
1014 {
1015 .number = U300_DMA_GENERAL_PURPOSE_1,
1016 .name = "GENERAL 01",
1017 .priority_high = 0,
1018
1019 .param.config = flags_memcpy_config,
1020 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1021 .param.ctrl_lli = flags_memcpy_lli,
1022 .param.ctrl_lli_last = flags_memcpy_lli_last,
1023 },
1024 {
1025 .number = U300_DMA_GENERAL_PURPOSE_2,
1026 .name = "GENERAL 02",
1027 .priority_high = 0,
1028
1029 .param.config = flags_memcpy_config,
1030 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1031 .param.ctrl_lli = flags_memcpy_lli,
1032 .param.ctrl_lli_last = flags_memcpy_lli_last,
1033 },
1034 {
1035 .number = U300_DMA_GENERAL_PURPOSE_3,
1036 .name = "GENERAL 03",
1037 .priority_high = 0,
1038
1039 .param.config = flags_memcpy_config,
1040 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1041 .param.ctrl_lli = flags_memcpy_lli,
1042 .param.ctrl_lli_last = flags_memcpy_lli_last,
1043 },
1044 {
1045 .number = U300_DMA_GENERAL_PURPOSE_4,
1046 .name = "GENERAL 04",
1047 .priority_high = 0,
1048
1049 .param.config = flags_memcpy_config,
1050 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1051 .param.ctrl_lli = flags_memcpy_lli,
1052 .param.ctrl_lli_last = flags_memcpy_lli_last,
1053 },
1054 {
1055 .number = U300_DMA_GENERAL_PURPOSE_5,
1056 .name = "GENERAL 05",
1057 .priority_high = 0,
1058
1059 .param.config = flags_memcpy_config,
1060 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1061 .param.ctrl_lli = flags_memcpy_lli,
1062 .param.ctrl_lli_last = flags_memcpy_lli_last,
1063 },
1064 {
1065 .number = U300_DMA_GENERAL_PURPOSE_6,
1066 .name = "GENERAL 06",
1067 .priority_high = 0,
1068
1069 .param.config = flags_memcpy_config,
1070 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1071 .param.ctrl_lli = flags_memcpy_lli,
1072 .param.ctrl_lli_last = flags_memcpy_lli_last,
1073 },
1074 {
1075 .number = U300_DMA_GENERAL_PURPOSE_7,
1076 .name = "GENERAL 07",
1077 .priority_high = 0,
1078
1079 .param.config = flags_memcpy_config,
1080 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1081 .param.ctrl_lli = flags_memcpy_lli,
1082 .param.ctrl_lli_last = flags_memcpy_lli_last,
1083 },
1084 {
1085 .number = U300_DMA_GENERAL_PURPOSE_8,
1086 .name = "GENERAL 08",
1087 .priority_high = 0,
1088
1089 .param.config = flags_memcpy_config,
1090 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1091 .param.ctrl_lli = flags_memcpy_lli,
1092 .param.ctrl_lli_last = flags_memcpy_lli_last,
1093 },
1094 {
1095 .number = U300_DMA_UART1_TX,
1096 .name = "UART1 TX",
1097 .priority_high = 0,
1098 },
1099 {
1100 .number = U300_DMA_UART1_RX,
1101 .name = "UART1 RX",
1102 .priority_high = 0,
1103 }
1104};
1105
1106static struct coh901318_platform coh901318_platform = {
1107 .chans_slave = dma_slave_channels,
1108 .chans_memcpy = dma_memcpy_channels,
1109 .access_memory_state = coh901318_access_memory_state,
1110 .chan_conf = chan_config,
1111 .max_channels = U300_DMA_CHANNELS,
1112};
1113
30#define COHC_2_DEV(cohc) (&cohc->chan.dev->device) 1114#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
31 1115
32#ifdef VERBOSE_DEBUG 1116#ifdef VERBOSE_DEBUG
@@ -1448,9 +2532,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
1448 pdev->dev.driver->name) == NULL) 2532 pdev->dev.driver->name) == NULL)
1449 return -ENOMEM; 2533 return -ENOMEM;
1450 2534
1451 pdata = pdev->dev.platform_data; 2535 pdata = &coh901318_platform,
1452 if (!pdata)
1453 return -ENODEV;
1454 2536
1455 base = devm_kzalloc(&pdev->dev, 2537 base = devm_kzalloc(&pdev->dev,
1456 ALIGN(sizeof(struct coh901318_base), 4) + 2538 ALIGN(sizeof(struct coh901318_base), 4) +
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-24 22:29:46 -0500