diff options
author | Shawn Guo <shawn.guo@freescale.com> | 2014-05-04 09:48:05 -0400 |
---|---|---|
committer | Tejun Heo <tj@kernel.org> | 2014-05-04 15:04:35 -0400 |
commit | 24a9ad5b82929cdeaff70018d82263de0c34c45d (patch) | |
tree | 7f707f52c9d5ec831ce9b03f88747636ed37e400 | |
parent | 0cf4a7d6cf23715276fcd0f1cd1cabc6a9b46942 (diff) |
ahci: imx: add namespace for register enums
Update register enums a little bit to add proper namespace prefix, and
have the names match i.MX reference manual.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
-rw-r--r-- | drivers/ata/ahci_imx.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index 497c7abe1c7d..776757634e90 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c | |||
@@ -29,9 +29,11 @@ | |||
29 | #include "ahci.h" | 29 | #include "ahci.h" |
30 | 30 | ||
31 | enum { | 31 | enum { |
32 | PORT_PHY_CTL = 0x178, /* Port0 PHY Control */ | 32 | /* Timer 1-ms Register */ |
33 | PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */ | 33 | IMX_TIMER1MS = 0x00e0, |
34 | HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ | 34 | /* Port0 PHY Control Register */ |
35 | IMX_P0PHYCR = 0x0178, | ||
36 | IMX_P0PHYCR_TEST_PDDQ = 1 << 20, | ||
35 | }; | 37 | }; |
36 | 38 | ||
37 | enum ahci_imx_type { | 39 | enum ahci_imx_type { |
@@ -156,8 +158,8 @@ static void ahci_imx_error_handler(struct ata_port *ap) | |||
156 | * without full reset once the pddq mode is enabled making it | 158 | * without full reset once the pddq mode is enabled making it |
157 | * impossible to use as part of libata LPM. | 159 | * impossible to use as part of libata LPM. |
158 | */ | 160 | */ |
159 | reg_val = readl(mmio + PORT_PHY_CTL); | 161 | reg_val = readl(mmio + IMX_P0PHYCR); |
160 | writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); | 162 | writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR); |
161 | imx_sata_disable(hpriv); | 163 | imx_sata_disable(hpriv); |
162 | imxpriv->no_device = true; | 164 | imxpriv->no_device = true; |
163 | } | 165 | } |
@@ -248,7 +250,7 @@ static int imx_ahci_probe(struct platform_device *pdev) | |||
248 | 250 | ||
249 | /* | 251 | /* |
250 | * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, | 252 | * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, |
251 | * and IP vendor specific register HOST_TIMER1MS. | 253 | * and IP vendor specific register IMX_TIMER1MS. |
252 | * Configure CAP_SSS (support stagered spin up). | 254 | * Configure CAP_SSS (support stagered spin up). |
253 | * Implement the port0. | 255 | * Implement the port0. |
254 | * Get the ahb clock rate, and configure the TIMER1MS register. | 256 | * Get the ahb clock rate, and configure the TIMER1MS register. |
@@ -265,7 +267,7 @@ static int imx_ahci_probe(struct platform_device *pdev) | |||
265 | } | 267 | } |
266 | 268 | ||
267 | reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; | 269 | reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; |
268 | writel(reg_val, hpriv->mmio + HOST_TIMER1MS); | 270 | writel(reg_val, hpriv->mmio + IMX_TIMER1MS); |
269 | 271 | ||
270 | ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0); | 272 | ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0); |
271 | if (ret) | 273 | if (ret) |