[ARM] S3C64XX: Add S3C64XX_SPCON register bit definitions

Add the definitions for the SPCON register in the
GPIO block.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

1 files changed, 81 insertions, 0 deletions

diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
index d45d66b8c2fa..81f7f6e6832e 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
@@ -37,6 +37,87 @@
 
 #define S3C64XX_SPCON           S3C64XX_GPIOREG(0x1A0)
 
+#define S3C64XX_SPCON_DRVCON_CAM_MASK           (0x3 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_SHIFT          (30)
+#define S3C64XX_SPCON_DRVCON_CAM_2mA            (0x0 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_4mA            (0x1 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_7mA            (0x2 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_9mA            (0x3 << 30)
+
+#define S3C64XX_SPCON_DRVCON_HSSPI_MASK         (0x3 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT        (28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_2mA          (0x0 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_4mA          (0x1 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_7mA          (0x2 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_9mA          (0x3 << 28)
+
+#define S3C64XX_SPCON_DRVCON_HSMMC_MASK         (0x3 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT        (26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_2mA          (0x0 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_4mA          (0x1 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_7mA          (0x2 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_9mA          (0x3 << 26)
+
+#define S3C64XX_SPCON_DRVCON_LCD_MASK           (0x3 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_SHIFT          (24)
+#define S3C64XX_SPCON_DRVCON_LCD_2mA            (0x0 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_4mA            (0x1 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_7mA            (0x2 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_9mA            (0x3 << 24)
+
+#define S3C64XX_SPCON_DRVCON_MODEM_MASK         (0x3 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT        (22)
+#define S3C64XX_SPCON_DRVCON_MODEM_2mA          (0x0 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_4mA          (0x1 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_7mA          (0x2 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_9mA          (0x3 << 22)
+
+#define S3C64XX_SPCON_nRSTOUT_OEN               (1 << 21)
+
+#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK       (0x3 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT      (18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA        (0x0 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA        (0x1 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA        (0x2 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA        (0x3 << 18)
+
+#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK         (0x3 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT        (16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED     (0x0 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN         (0x1 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_UP           (0x2 << 16)
+
+#define S3C64XX_SPCON_MEM1_D_PUD1_MASK          (0x3 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT         (14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED      (0x0 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN          (0x1 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_UP            (0x2 << 14)
+
+#define S3C64XX_SPCON_MEM1_D_PUD0_MASK          (0x3 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT         (12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED      (0x0 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN          (0x1 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_UP            (0x2 << 12)
+
+#define S3C64XX_SPCON_MEM0_D_PUD_MASK           (0x3 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT          (8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED       (0x0 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DOWN           (0x1 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_UP             (0x2 << 8)
+
+#define S3C64XX_SPCON_USBH_DMPD                 (1 << 7)
+#define S3C64XX_SPCON_USBH_DPPD                 (1 << 6)
+#define S3C64XX_SPCON_USBH_PUSW2                (1 << 5)
+#define S3C64XX_SPCON_USBH_PUSW1                (1 << 4)
+#define S3C64XX_SPCON_USBH_SUSPND               (1 << 3)
+
+#define S3C64XX_SPCON_LCD_SEL_MASK              (0x3 << 0)
+#define S3C64XX_SPCON_LCD_SEL_SHIFT             (0)
+#define S3C64XX_SPCON_LCD_SEL_HOST              (0x0 << 0)
+#define S3C64XX_SPCON_LCD_SEL_RGB               (0x1 << 0)
+#define S3C64XX_SPCON_LCD_SEL_606_656           (0x2 << 0)
+
+
 /* External interrupt registers */
 
 #define S3C64XX_EINT12CON       S3C64XX_GPIOREG(0x200)