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authorSrikanth Thokala <sthokal@xilinx.com>2013-12-07 03:10:48 -0500
committerDavid S. Miller <davem@davemloft.net>2013-12-09 21:02:25 -0500
commit243fedd5fa4a4a72caae7bde3f0bd0354a256b88 (patch)
tree878c459de127ebf3fb8d4dc74ae31c4c4d2018fa
parenta3300ef4bbb1f1e33ff0400e1e6cf7733d988f4f (diff)
net: emaclite: Remove unnecessary code that enables/disables interrupts on PONG buffers
There are no specific interrupts for the PONG buffer on both transmit and receive side, same interrupt is valid for both buffers. So, this patch removes this code. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Reviewed-by: Michal Simek <monstr@monstr.eu> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/xilinx/xilinx_emaclite.c38
1 files changed, 0 insertions, 38 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 74234a51c851..b2850fdb517e 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -163,26 +163,9 @@ static void xemaclite_enable_interrupts(struct net_local *drvdata)
163 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 163 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
164 drvdata->base_addr + XEL_TSR_OFFSET); 164 drvdata->base_addr + XEL_TSR_OFFSET);
165 165
166 /* Enable the Tx interrupts for the second Buffer if
167 * configured in HW */
168 if (drvdata->tx_ping_pong != 0) {
169 reg_data = __raw_readl(drvdata->base_addr +
170 XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
171 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
172 drvdata->base_addr + XEL_BUFFER_OFFSET +
173 XEL_TSR_OFFSET);
174 }
175
176 /* Enable the Rx interrupts for the first buffer */ 166 /* Enable the Rx interrupts for the first buffer */
177 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 167 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
178 168
179 /* Enable the Rx interrupts for the second Buffer if
180 * configured in HW */
181 if (drvdata->rx_ping_pong != 0) {
182 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr +
183 XEL_BUFFER_OFFSET + XEL_RSR_OFFSET);
184 }
185
186 /* Enable the Global Interrupt Enable */ 169 /* Enable the Global Interrupt Enable */
187 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 170 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
188} 171}
@@ -206,31 +189,10 @@ static void xemaclite_disable_interrupts(struct net_local *drvdata)
206 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 189 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
207 drvdata->base_addr + XEL_TSR_OFFSET); 190 drvdata->base_addr + XEL_TSR_OFFSET);
208 191
209 /* Disable the Tx interrupts for the second Buffer
210 * if configured in HW */
211 if (drvdata->tx_ping_pong != 0) {
212 reg_data = __raw_readl(drvdata->base_addr + XEL_BUFFER_OFFSET +
213 XEL_TSR_OFFSET);
214 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
215 drvdata->base_addr + XEL_BUFFER_OFFSET +
216 XEL_TSR_OFFSET);
217 }
218
219 /* Disable the Rx interrupts for the first buffer */ 192 /* Disable the Rx interrupts for the first buffer */
220 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET); 193 reg_data = __raw_readl(drvdata->base_addr + XEL_RSR_OFFSET);
221 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 194 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
222 drvdata->base_addr + XEL_RSR_OFFSET); 195 drvdata->base_addr + XEL_RSR_OFFSET);
223
224 /* Disable the Rx interrupts for the second buffer
225 * if configured in HW */
226 if (drvdata->rx_ping_pong != 0) {
227
228 reg_data = __raw_readl(drvdata->base_addr + XEL_BUFFER_OFFSET +
229 XEL_RSR_OFFSET);
230 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
231 drvdata->base_addr + XEL_BUFFER_OFFSET +
232 XEL_RSR_OFFSET);
233 }
234} 196}
235 197
236/** 198/**