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authorBen Widawsky <benjamin.widawsky@intel.com>2014-04-18 17:04:29 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-05 03:09:24 -0400
commit242a4018cc7902fbdaf213314db2bc622f5c579d (patch)
tree8cde1d6db593fcc53d0aa7022676ed25c5dae2e8
parent1d2866baf71e222308345ec745c20cbdb279f325 (diff)
drm/i915/bdw: Disable idle DOP clock gating
It seems we need this at least for the current platforms we have, but probably not later. In any event, it should cause too much harm as we do the same thing on several other platforms. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 19020e5e914b..0c33953cd270 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4988,6 +4988,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
4988 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 4988 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4989 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); 4989 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4990 4990
4991 /* WaDisableDopClockGating:bdw May not be needed for production */
4992 I915_WRITE(GEN7_ROW_CHICKEN2,
4993 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4994
4991 /* WaSwitchSolVfFArbitrationPriority:bdw */ 4995 /* WaSwitchSolVfFArbitrationPriority:bdw */
4992 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 4996 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4993 4997