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authorDave Airlie <airlied@redhat.com>2014-03-26 00:00:53 -0400
committerDave Airlie <airlied@redhat.com>2014-03-26 00:00:53 -0400
commit23c73b24a0f582fa0e8d4419f896e9b684dc8761 (patch)
tree65d3a519d0b8ea32867f0be26cf8d6969d032113
parent63ac07cdee6e1f2bf748ac3f28662e3c01a72496 (diff)
parent020ff5467603483a97042625d12696c9b39922cf (diff)
Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next
this is the third pull request for 3.15 radeon changes. Highlights this time: - More DP work from Alex, especially making use of the new DP aux helpers - Marek's 1D and linear tiling fixes for CIK * 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux: drm/radeon: set PIPE_CONFIG for 1D and linear tiling modes on CIK drm/radeon: use drm_dp_dpcd_read_link_status() drm/radeon: use the new drm helpers for dp aux drm/dp: make aux retries less chatty drm/radeon: clarify special handling in i2c over aux drm/radeon/atom: rework encoder enable/disable sequence drm/radeon/dp: move sink power control to a separate function drm/radeon/dp: use i2c_get_adapdata rather than casting
Diffstat
-rw-r--r--drivers/gpu/drm/drm_dp_helper.c4
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c268
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c82
-rw-r--r--drivers/gpu/drm/radeon/cik.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h4
7 files changed, 202 insertions, 203 deletions
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 35251af3b14e..74724aacb8ae 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -402,7 +402,7 @@ static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
402 } 402 }
403 } 403 }
404 404
405 DRM_ERROR("too many retries, giving up\n"); 405 DRM_DEBUG_KMS("too many retries, giving up\n");
406 return -EIO; 406 return -EIO;
407} 407}
408 408
@@ -656,7 +656,7 @@ static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
656 } 656 }
657 } 657 }
658 658
659 DRM_ERROR("too many retries, giving up\n"); 659 DRM_DEBUG_KMS("too many retries, giving up\n");
660 return -EREMOTEIO; 660 return -EREMOTEIO;
661} 661}
662 662
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 4ad7643fce5f..8b0ab170cef9 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -142,101 +142,69 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
142 return recv_bytes; 142 return recv_bytes;
143} 143}
144 144
145static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 145#define HEADER_SIZE 4
146 u16 address, u8 *send, u8 send_bytes, u8 delay)
147{
148 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
149 int ret;
150 u8 msg[20];
151 int msg_bytes = send_bytes + 4;
152 u8 ack;
153 unsigned retry;
154
155 if (send_bytes > 16)
156 return -1;
157 146
158 msg[0] = address; 147static ssize_t
159 msg[1] = address >> 8; 148radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
160 msg[2] = DP_AUX_NATIVE_WRITE << 4;
161 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
162 memcpy(&msg[4], send, send_bytes);
163
164 for (retry = 0; retry < 7; retry++) {
165 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
166 msg, msg_bytes, NULL, 0, delay, &ack);
167 if (ret == -EBUSY)
168 continue;
169 else if (ret < 0)
170 return ret;
171 ack >>= 4;
172 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
173 return send_bytes;
174 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
175 usleep_range(400, 500);
176 else
177 return -EIO;
178 }
179
180 return -EIO;
181}
182
183static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
184 u16 address, u8 *recv, int recv_bytes, u8 delay)
185{ 149{
186 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 150 struct radeon_i2c_chan *chan =
187 u8 msg[4]; 151 container_of(aux, struct radeon_i2c_chan, aux);
188 int msg_bytes = 4;
189 u8 ack;
190 int ret; 152 int ret;
191 unsigned retry; 153 u8 tx_buf[20];
192 154 size_t tx_size;
193 msg[0] = address; 155 u8 ack, delay = 0;
194 msg[1] = address >> 8; 156
195 msg[2] = DP_AUX_NATIVE_READ << 4; 157 if (WARN_ON(msg->size > 16))
196 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 158 return -E2BIG;
197 159
198 for (retry = 0; retry < 7; retry++) { 160 tx_buf[0] = msg->address & 0xff;
199 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 161 tx_buf[1] = msg->address >> 8;
200 msg, msg_bytes, recv, recv_bytes, delay, &ack); 162 tx_buf[2] = msg->request << 4;
201 if (ret == -EBUSY) 163 tx_buf[3] = msg->size - 1;
202 continue; 164
203 else if (ret < 0) 165 switch (msg->request & ~DP_AUX_I2C_MOT) {
204 return ret; 166 case DP_AUX_NATIVE_WRITE:
205 ack >>= 4; 167 case DP_AUX_I2C_WRITE:
206 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 168 tx_size = HEADER_SIZE + msg->size;
207 return ret; 169 tx_buf[3] |= tx_size << 4;
208 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 170 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
209 usleep_range(400, 500); 171 ret = radeon_process_aux_ch(chan,
210 else if (ret == 0) 172 tx_buf, tx_size, NULL, 0, delay, &ack);
211 return -EPROTO; 173 if (ret >= 0)
212 else 174 /* Return payload size. */
213 return -EIO; 175 ret = msg->size;
176 break;
177 case DP_AUX_NATIVE_READ:
178 case DP_AUX_I2C_READ:
179 tx_size = HEADER_SIZE;
180 tx_buf[3] |= tx_size << 4;
181 ret = radeon_process_aux_ch(chan,
182 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
183 break;
184 default:
185 ret = -EINVAL;
186 break;
214 } 187 }
215 188
216 return -EIO; 189 if (ret > 0)
217} 190 msg->reply = ack >> 4;
218 191
219static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, 192 return ret;
220 u16 reg, u8 val)
221{
222 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
223} 193}
224 194
225static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, 195void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
226 u16 reg)
227{ 196{
228 u8 val = 0; 197 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
229
230 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
231 198
232 return val; 199 dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;
200 dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;
233} 201}
234 202
235int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 203int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
236 u8 write_byte, u8 *read_byte) 204 u8 write_byte, u8 *read_byte)
237{ 205{
238 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 206 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
239 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; 207 struct radeon_i2c_chan *auxch = i2c_get_adapdata(adapter);
240 u16 address = algo_data->address; 208 u16 address = algo_data->address;
241 u8 msg[5]; 209 u8 msg[5];
242 u8 reply[2]; 210 u8 reply[2];
@@ -246,34 +214,30 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
246 int ret; 214 int ret;
247 u8 ack; 215 u8 ack;
248 216
249 /* Set up the command byte */ 217 /* Set up the address */
250 if (mode & MODE_I2C_READ)
251 msg[2] = DP_AUX_I2C_READ << 4;
252 else
253 msg[2] = DP_AUX_I2C_WRITE << 4;
254
255 if (!(mode & MODE_I2C_STOP))
256 msg[2] |= DP_AUX_I2C_MOT << 4;
257
258 msg[0] = address; 218 msg[0] = address;
259 msg[1] = address >> 8; 219 msg[1] = address >> 8;
260 220
261 switch (mode) { 221 /* Set up the command byte */
262 case MODE_I2C_WRITE: 222 if (mode & MODE_I2C_READ) {
223 msg[2] = DP_AUX_I2C_READ << 4;
224 msg_bytes = 4;
225 msg[3] = msg_bytes << 4;
226 } else {
227 msg[2] = DP_AUX_I2C_WRITE << 4;
263 msg_bytes = 5; 228 msg_bytes = 5;
264 msg[3] = msg_bytes << 4; 229 msg[3] = msg_bytes << 4;
265 msg[4] = write_byte; 230 msg[4] = write_byte;
266 break;
267 case MODE_I2C_READ:
268 msg_bytes = 4;
269 msg[3] = msg_bytes << 4;
270 break;
271 default:
272 msg_bytes = 4;
273 msg[3] = 3 << 4;
274 break;
275 } 231 }
276 232
233 /* special handling for start/stop */
234 if (mode & (MODE_I2C_START | MODE_I2C_STOP))
235 msg[3] = 3 << 4;
236
237 /* Set MOT bit for all but stop */
238 if ((mode & MODE_I2C_STOP) == 0)
239 msg[2] |= DP_AUX_I2C_MOT << 4;
240
277 for (retry = 0; retry < 7; retry++) { 241 for (retry = 0; retry < 7; retry++) {
278 ret = radeon_process_aux_ch(auxch, 242 ret = radeon_process_aux_ch(auxch,
279 msg, msg_bytes, reply, reply_bytes, 0, &ack); 243 msg, msg_bytes, reply, reply_bytes, 0, &ack);
@@ -472,11 +436,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
472 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 436 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
473 return; 437 return;
474 438
475 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) 439 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3))
476 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 440 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
477 buf[0], buf[1], buf[2]); 441 buf[0], buf[1], buf[2]);
478 442
479 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) 443 if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3))
480 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 444 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
481 buf[0], buf[1], buf[2]); 445 buf[0], buf[1], buf[2]);
482} 446}
@@ -487,8 +451,8 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
487 u8 msg[DP_DPCD_SIZE]; 451 u8 msg[DP_DPCD_SIZE];
488 int ret, i; 452 int ret, i;
489 453
490 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 454 ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg,
491 DP_DPCD_SIZE, 0); 455 DP_DPCD_SIZE);
492 if (ret > 0) { 456 if (ret > 0) {
493 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 457 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
494 DRM_DEBUG_KMS("DPCD: "); 458 DRM_DEBUG_KMS("DPCD: ");
@@ -510,6 +474,7 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
510 struct drm_device *dev = encoder->dev; 474 struct drm_device *dev = encoder->dev;
511 struct radeon_device *rdev = dev->dev_private; 475 struct radeon_device *rdev = dev->dev_private;
512 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
477 struct radeon_connector_atom_dig *dig_connector;
513 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 478 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
514 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 479 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
515 u8 tmp; 480 u8 tmp;
@@ -517,9 +482,15 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
517 if (!ASIC_IS_DCE4(rdev)) 482 if (!ASIC_IS_DCE4(rdev))
518 return panel_mode; 483 return panel_mode;
519 484
485 if (!radeon_connector->con_priv)
486 return panel_mode;
487
488 dig_connector = radeon_connector->con_priv;
489
520 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 490 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
521 /* DP bridge chips */ 491 /* DP bridge chips */
522 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 492 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
493 DP_EDP_CONFIGURATION_CAP, &tmp);
523 if (tmp & 1) 494 if (tmp & 1)
524 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 495 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
525 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 496 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
@@ -529,7 +500,8 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
529 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 500 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
530 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 501 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
531 /* eDP */ 502 /* eDP */
532 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 503 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
504 DP_EDP_CONFIGURATION_CAP, &tmp);
533 if (tmp & 1) 505 if (tmp & 1)
534 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 506 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
535 } 507 }
@@ -577,37 +549,42 @@ int radeon_dp_mode_valid_helper(struct drm_connector *connector,
577 return MODE_OK; 549 return MODE_OK;
578} 550}
579 551
580static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
581 u8 link_status[DP_LINK_STATUS_SIZE])
582{
583 int ret;
584 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
585 link_status, DP_LINK_STATUS_SIZE, 100);
586 if (ret <= 0) {
587 return false;
588 }
589
590 DRM_DEBUG_KMS("link status %6ph\n", link_status);
591 return true;
592}
593
594bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 552bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
595{ 553{
596 u8 link_status[DP_LINK_STATUS_SIZE]; 554 u8 link_status[DP_LINK_STATUS_SIZE];
597 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 555 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
598 556
599 if (!radeon_dp_get_link_status(radeon_connector, link_status)) 557 if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0)
600 return false; 558 return false;
601 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 559 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
602 return false; 560 return false;
603 return true; 561 return true;
604} 562}
605 563
564void radeon_dp_set_rx_power_state(struct drm_connector *connector,
565 u8 power_state)
566{
567 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
568 struct radeon_connector_atom_dig *dig_connector;
569
570 if (!radeon_connector->con_priv)
571 return;
572
573 dig_connector = radeon_connector->con_priv;
574
575 /* power up/down the sink */
576 if (dig_connector->dpcd[0] >= 0x11) {
577 drm_dp_dpcd_writeb(&dig_connector->dp_i2c_bus->aux,
578 DP_SET_POWER, power_state);
579 usleep_range(1000, 2000);
580 }
581}
582
583
606struct radeon_dp_link_train_info { 584struct radeon_dp_link_train_info {
607 struct radeon_device *rdev; 585 struct radeon_device *rdev;
608 struct drm_encoder *encoder; 586 struct drm_encoder *encoder;
609 struct drm_connector *connector; 587 struct drm_connector *connector;
610 struct radeon_connector *radeon_connector;
611 int enc_id; 588 int enc_id;
612 int dp_clock; 589 int dp_clock;
613 int dp_lane_count; 590 int dp_lane_count;
@@ -617,6 +594,7 @@ struct radeon_dp_link_train_info {
617 u8 link_status[DP_LINK_STATUS_SIZE]; 594 u8 link_status[DP_LINK_STATUS_SIZE];
618 u8 tries; 595 u8 tries;
619 bool use_dpencoder; 596 bool use_dpencoder;
597 struct drm_dp_aux *aux;
620}; 598};
621 599
622static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 600static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
@@ -627,8 +605,8 @@ static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
627 0, dp_info->train_set[0]); /* sets all lanes at once */ 605 0, dp_info->train_set[0]); /* sets all lanes at once */
628 606
629 /* set the vs/emph on the sink */ 607 /* set the vs/emph on the sink */
630 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, 608 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
631 dp_info->train_set, dp_info->dp_lane_count, 0); 609 dp_info->train_set, dp_info->dp_lane_count);
632} 610}
633 611
634static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 612static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
@@ -663,7 +641,7 @@ static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
663 } 641 }
664 642
665 /* enable training pattern on the sink */ 643 /* enable training pattern on the sink */
666 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); 644 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
667} 645}
668 646
669static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 647static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
@@ -673,34 +651,30 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
673 u8 tmp; 651 u8 tmp;
674 652
675 /* power up the sink */ 653 /* power up the sink */
676 if (dp_info->dpcd[0] >= 0x11) { 654 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
677 radeon_write_dpcd_reg(dp_info->radeon_connector,
678 DP_SET_POWER, DP_SET_POWER_D0);
679 usleep_range(1000, 2000);
680 }
681 655
682 /* possibly enable downspread on the sink */ 656 /* possibly enable downspread on the sink */
683 if (dp_info->dpcd[3] & 0x1) 657 if (dp_info->dpcd[3] & 0x1)
684 radeon_write_dpcd_reg(dp_info->radeon_connector, 658 drm_dp_dpcd_writeb(dp_info->aux,
685 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 659 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
686 else 660 else
687 radeon_write_dpcd_reg(dp_info->radeon_connector, 661 drm_dp_dpcd_writeb(dp_info->aux,
688 DP_DOWNSPREAD_CTRL, 0); 662 DP_DOWNSPREAD_CTRL, 0);
689 663
690 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && 664 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
691 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { 665 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
692 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); 666 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
693 } 667 }
694 668
695 /* set the lane count on the sink */ 669 /* set the lane count on the sink */
696 tmp = dp_info->dp_lane_count; 670 tmp = dp_info->dp_lane_count;
697 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 671 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
698 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 672 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
699 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); 673 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
700 674
701 /* set the link rate on the sink */ 675 /* set the link rate on the sink */
702 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 676 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
703 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); 677 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
704 678
705 /* start training on the source */ 679 /* start training on the source */
706 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 680 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
@@ -711,9 +685,9 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
711 dp_info->dp_clock, dp_info->enc_id, 0); 685 dp_info->dp_clock, dp_info->enc_id, 0);
712 686
713 /* disable the training pattern on the sink */ 687 /* disable the training pattern on the sink */
714 radeon_write_dpcd_reg(dp_info->radeon_connector, 688 drm_dp_dpcd_writeb(dp_info->aux,
715 DP_TRAINING_PATTERN_SET, 689 DP_TRAINING_PATTERN_SET,
716 DP_TRAINING_PATTERN_DISABLE); 690 DP_TRAINING_PATTERN_DISABLE);
717 691
718 return 0; 692 return 0;
719} 693}
@@ -723,9 +697,9 @@ static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info
723 udelay(400); 697 udelay(400);
724 698
725 /* disable the training pattern on the sink */ 699 /* disable the training pattern on the sink */
726 radeon_write_dpcd_reg(dp_info->radeon_connector, 700 drm_dp_dpcd_writeb(dp_info->aux,
727 DP_TRAINING_PATTERN_SET, 701 DP_TRAINING_PATTERN_SET,
728 DP_TRAINING_PATTERN_DISABLE); 702 DP_TRAINING_PATTERN_DISABLE);
729 703
730 /* disable the training pattern on the source */ 704 /* disable the training pattern on the source */
731 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 705 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
@@ -757,7 +731,8 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
757 while (1) { 731 while (1) {
758 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 732 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
759 733
760 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 734 if (drm_dp_dpcd_read_link_status(dp_info->aux,
735 dp_info->link_status) <= 0) {
761 DRM_ERROR("displayport link status failed\n"); 736 DRM_ERROR("displayport link status failed\n");
762 break; 737 break;
763 } 738 }
@@ -819,7 +794,8 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
819 while (1) { 794 while (1) {
820 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 795 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
821 796
822 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 797 if (drm_dp_dpcd_read_link_status(dp_info->aux,
798 dp_info->link_status) <= 0) {
823 DRM_ERROR("displayport link status failed\n"); 799 DRM_ERROR("displayport link status failed\n");
824 break; 800 break;
825 } 801 }
@@ -902,7 +878,7 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
902 else 878 else
903 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 879 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
904 880
905 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); 881 drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux, DP_MAX_LANE_COUNT, &tmp);
906 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 882 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
907 dp_info.tp3_supported = true; 883 dp_info.tp3_supported = true;
908 else 884 else
@@ -912,9 +888,9 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
912 dp_info.rdev = rdev; 888 dp_info.rdev = rdev;
913 dp_info.encoder = encoder; 889 dp_info.encoder = encoder;
914 dp_info.connector = connector; 890 dp_info.connector = connector;
915 dp_info.radeon_connector = radeon_connector;
916 dp_info.dp_lane_count = dig_connector->dp_lane_count; 891 dp_info.dp_lane_count = dig_connector->dp_lane_count;
917 dp_info.dp_clock = dig_connector->dp_clock; 892 dp_info.dp_clock = dig_connector->dp_clock;
893 dp_info.aux = &dig_connector->dp_i2c_bus->aux;
918 894
919 if (radeon_dp_link_train_init(&dp_info)) 895 if (radeon_dp_link_train_init(&dp_info))
920 goto done; 896 goto done;
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 607dc14d195e..e6eb5097597f 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1633,10 +1633,16 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1633 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1633 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1634 struct radeon_connector *radeon_connector = NULL; 1634 struct radeon_connector *radeon_connector = NULL;
1635 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1635 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1636 bool travis_quirk = false;
1636 1637
1637 if (connector) { 1638 if (connector) {
1638 radeon_connector = to_radeon_connector(connector); 1639 radeon_connector = to_radeon_connector(connector);
1639 radeon_dig_connector = radeon_connector->con_priv; 1640 radeon_dig_connector = radeon_connector->con_priv;
1641 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1642 ENCODER_OBJECT_ID_TRAVIS) &&
1643 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1644 !ASIC_IS_DCE5(rdev))
1645 travis_quirk = true;
1640 } 1646 }
1641 1647
1642 switch (mode) { 1648 switch (mode) {
@@ -1657,17 +1663,13 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1657 atombios_external_encoder_setup(encoder, ext_encoder, 1663 atombios_external_encoder_setup(encoder, ext_encoder,
1658 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1664 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1659 } 1665 }
1660 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1661 } else if (ASIC_IS_DCE4(rdev)) { 1666 } else if (ASIC_IS_DCE4(rdev)) {
1662 /* setup and enable the encoder */ 1667 /* setup and enable the encoder */
1663 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1668 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1664 /* enable the transmitter */
1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1666 } else { 1669 } else {
1667 /* setup and enable the encoder and transmitter */ 1670 /* setup and enable the encoder and transmitter */
1668 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1671 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1669 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1670 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1671 } 1673 }
1672 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1674 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1673 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1675 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
@@ -1675,68 +1677,56 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1675 ATOM_TRANSMITTER_ACTION_POWER_ON); 1677 ATOM_TRANSMITTER_ACTION_POWER_ON);
1676 radeon_dig_connector->edp_on = true; 1678 radeon_dig_connector->edp_on = true;
1677 } 1679 }
1680 }
1681 /* enable the transmitter */
1682 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1683 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1684 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1678 radeon_dp_link_train(encoder, connector); 1685 radeon_dp_link_train(encoder, connector);
1679 if (ASIC_IS_DCE4(rdev)) 1686 if (ASIC_IS_DCE4(rdev))
1680 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1687 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1681 } 1688 }
1682 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1689 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1683 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1690 atombios_dig_transmitter_setup(encoder,
1691 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1692 if (ext_encoder)
1693 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1684 break; 1694 break;
1685 case DRM_MODE_DPMS_STANDBY: 1695 case DRM_MODE_DPMS_STANDBY:
1686 case DRM_MODE_DPMS_SUSPEND: 1696 case DRM_MODE_DPMS_SUSPEND:
1687 case DRM_MODE_DPMS_OFF: 1697 case DRM_MODE_DPMS_OFF:
1688 if (ASIC_IS_DCE4(rdev)) { 1698 if (ASIC_IS_DCE4(rdev)) {
1699 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1700 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1701 }
1702 if (ext_encoder)
1703 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1704 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1705 atombios_dig_transmitter_setup(encoder,
1706 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1707
1708 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1709 connector && !travis_quirk)
1710 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1711 if (ASIC_IS_DCE4(rdev)) {
1689 /* disable the transmitter */ 1712 /* disable the transmitter */
1690 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1713 atombios_dig_transmitter_setup(encoder,
1714 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1691 } else { 1715 } else {
1692 /* disable the encoder and transmitter */ 1716 /* disable the encoder and transmitter */
1693 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1717 atombios_dig_transmitter_setup(encoder,
1718 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1694 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1719 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1695 } 1720 }
1696 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1721 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1697 if (ASIC_IS_DCE4(rdev)) 1722 if (travis_quirk)
1698 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1723 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1699 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1724 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1700 atombios_set_edp_panel_power(connector, 1725 atombios_set_edp_panel_power(connector,
1701 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1726 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1702 radeon_dig_connector->edp_on = false; 1727 radeon_dig_connector->edp_on = false;
1703 } 1728 }
1704 } 1729 }
1705 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1706 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1707 break;
1708 }
1709}
1710
1711static void
1712radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1713 struct drm_encoder *ext_encoder,
1714 int mode)
1715{
1716 struct drm_device *dev = encoder->dev;
1717 struct radeon_device *rdev = dev->dev_private;
1718
1719 switch (mode) {
1720 case DRM_MODE_DPMS_ON:
1721 default:
1722 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1723 atombios_external_encoder_setup(encoder, ext_encoder,
1724 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1725 atombios_external_encoder_setup(encoder, ext_encoder,
1726 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1727 } else
1728 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1729 break;
1730 case DRM_MODE_DPMS_STANDBY:
1731 case DRM_MODE_DPMS_SUSPEND:
1732 case DRM_MODE_DPMS_OFF:
1733 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1734 atombios_external_encoder_setup(encoder, ext_encoder,
1735 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1736 atombios_external_encoder_setup(encoder, ext_encoder,
1737 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1738 } else
1739 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1740 break; 1730 break;
1741 } 1731 }
1742} 1732}
@@ -1747,7 +1737,6 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1747 struct drm_device *dev = encoder->dev; 1737 struct drm_device *dev = encoder->dev;
1748 struct radeon_device *rdev = dev->dev_private; 1738 struct radeon_device *rdev = dev->dev_private;
1749 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1739 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1750 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1751 1740
1752 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1741 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1753 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1742 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
@@ -1807,9 +1796,6 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1807 return; 1796 return;
1808 } 1797 }
1809 1798
1810 if (ext_encoder)
1811 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1812
1813 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1799 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1814 1800
1815} 1801}
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0ae991d3289a..62fefbbaf263 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2029,6 +2029,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2029 break; 2029 break;
2030 case 5: 2030 case 5:
2031 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2031 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2032 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2032 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2033 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2033 break; 2034 break;
2034 case 6: 2035 case 6:
@@ -2049,6 +2050,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2049 break; 2050 break;
2050 case 9: 2051 case 9:
2051 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2052 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2053 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2052 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 2054 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2053 break; 2055 break;
2054 case 10: 2056 case 10:
@@ -2071,6 +2073,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2071 break; 2073 break;
2072 case 13: 2074 case 13:
2073 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2075 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2076 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2074 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 2077 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2075 break; 2078 break;
2076 case 14: 2079 case 14:
@@ -2093,6 +2096,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2093 break; 2096 break;
2094 case 27: 2097 case 27:
2095 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2098 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2099 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2096 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 2100 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2097 break; 2101 break;
2098 case 28: 2102 case 28:
@@ -2247,6 +2251,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2247 break; 2251 break;
2248 case 5: 2252 case 5:
2249 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2253 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2254 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2255 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2251 break; 2256 break;
2252 case 6: 2257 case 6:
@@ -2267,6 +2272,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2267 break; 2272 break;
2268 case 9: 2273 case 9:
2269 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2274 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2275 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2270 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 2276 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2271 break; 2277 break;
2272 case 10: 2278 case 10:
@@ -2289,6 +2295,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2289 break; 2295 break;
2290 case 13: 2296 case 13:
2291 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2297 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2298 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2292 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 2299 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2293 break; 2300 break;
2294 case 14: 2301 case 14:
@@ -2311,6 +2318,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2311 break; 2318 break;
2312 case 27: 2319 case 27:
2313 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2320 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2321 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2314 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 2322 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2315 break; 2323 break;
2316 case 28: 2324 case 28:
@@ -2467,6 +2475,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2467 break; 2475 break;
2468 case 5: 2476 case 5:
2469 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2477 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2478 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2470 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2479 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2471 break; 2480 break;
2472 case 6: 2481 case 6:
@@ -2487,6 +2496,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2487 break; 2496 break;
2488 case 9: 2497 case 9:
2489 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2498 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2499 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2490 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 2500 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2491 break; 2501 break;
2492 case 10: 2502 case 10:
@@ -2509,6 +2519,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2509 break; 2519 break;
2510 case 13: 2520 case 13:
2511 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2521 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2522 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2512 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 2523 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2513 break; 2524 break;
2514 case 14: 2525 case 14:
@@ -2531,6 +2542,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2531 break; 2542 break;
2532 case 27: 2543 case 27:
2533 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2544 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2545 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2534 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 2546 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2535 break; 2547 break;
2536 case 28: 2548 case 28:
@@ -2593,6 +2605,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2593 break; 2605 break;
2594 case 5: 2606 case 5:
2595 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2607 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2608 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2596 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2609 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2597 break; 2610 break;
2598 case 6: 2611 case 6:
@@ -2613,6 +2626,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2613 break; 2626 break;
2614 case 9: 2627 case 9:
2615 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2628 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2629 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2616 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 2630 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2617 break; 2631 break;
2618 case 10: 2632 case 10:
@@ -2635,6 +2649,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2635 break; 2649 break;
2636 case 13: 2650 case 13:
2637 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2651 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2652 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2638 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 2653 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2639 break; 2654 break;
2640 case 14: 2655 case 14:
@@ -2657,6 +2672,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2657 break; 2672 break;
2658 case 27: 2673 case 27:
2659 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2674 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2675 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2660 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 2676 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2661 break; 2677 break;
2662 case 28: 2678 case 28:
@@ -2813,6 +2829,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2813 break; 2829 break;
2814 case 5: 2830 case 5:
2815 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2831 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2832 PIPE_CONFIG(ADDR_SURF_P2) |
2816 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2833 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2817 break; 2834 break;
2818 case 6: 2835 case 6:
@@ -2828,11 +2845,13 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2828 TILE_SPLIT(split_equal_to_row_size)); 2845 TILE_SPLIT(split_equal_to_row_size));
2829 break; 2846 break;
2830 case 8: 2847 case 8:
2831 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 2848 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2849 PIPE_CONFIG(ADDR_SURF_P2);
2832 break; 2850 break;
2833 case 9: 2851 case 9:
2834 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2852 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2835 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 2853 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2854 PIPE_CONFIG(ADDR_SURF_P2));
2836 break; 2855 break;
2837 case 10: 2856 case 10:
2838 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2857 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2854,6 +2873,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2854 break; 2873 break;
2855 case 13: 2874 case 13:
2856 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2875 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2876 PIPE_CONFIG(ADDR_SURF_P2) |
2857 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 2877 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2858 break; 2878 break;
2859 case 14: 2879 case 14:
@@ -2876,7 +2896,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2876 break; 2896 break;
2877 case 27: 2897 case 27:
2878 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2898 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2879 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 2899 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2900 PIPE_CONFIG(ADDR_SURF_P2));
2880 break; 2901 break;
2881 case 28: 2902 case 28:
2882 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 2903 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 82d4f865546e..ec958e86fd8b 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1595,6 +1595,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1595 uint32_t subpixel_order = SubPixelNone; 1595 uint32_t subpixel_order = SubPixelNone;
1596 bool shared_ddc = false; 1596 bool shared_ddc = false;
1597 bool is_dp_bridge = false; 1597 bool is_dp_bridge = false;
1598 bool has_aux = false;
1598 1599
1599 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1600 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1600 return; 1601 return;
@@ -1672,7 +1673,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1672 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch"); 1673 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1673 else 1674 else
1674 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch"); 1675 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1675 if (!radeon_dig_connector->dp_i2c_bus) 1676 if (radeon_dig_connector->dp_i2c_bus)
1677 has_aux = true;
1678 else
1676 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n"); 1679 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1677 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); 1680 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1678 if (!radeon_connector->ddc_bus) 1681 if (!radeon_connector->ddc_bus)
@@ -1895,7 +1898,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1895 if (!radeon_dig_connector->dp_i2c_bus) 1898 if (!radeon_dig_connector->dp_i2c_bus)
1896 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n"); 1899 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1897 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); 1900 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1898 if (!radeon_connector->ddc_bus) 1901 if (radeon_connector->ddc_bus)
1902 has_aux = true;
1903 else
1899 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1904 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
1900 } 1905 }
1901 subpixel_order = SubPixelHorizontalRGB; 1906 subpixel_order = SubPixelHorizontalRGB;
@@ -1939,7 +1944,9 @@ radeon_add_atom_connector(struct drm_device *dev,
1939 if (i2c_bus->valid) { 1944 if (i2c_bus->valid) {
1940 /* add DP i2c bus */ 1945 /* add DP i2c bus */
1941 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch"); 1946 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1942 if (!radeon_dig_connector->dp_i2c_bus) 1947 if (radeon_dig_connector->dp_i2c_bus)
1948 has_aux = true;
1949 else
1943 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n"); 1950 DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
1944 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); 1951 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1945 if (!radeon_connector->ddc_bus) 1952 if (!radeon_connector->ddc_bus)
@@ -2000,6 +2007,10 @@ radeon_add_atom_connector(struct drm_device *dev,
2000 2007
2001 connector->display_info.subpixel_order = subpixel_order; 2008 connector->display_info.subpixel_order = subpixel_order;
2002 drm_sysfs_connector_add(connector); 2009 drm_sysfs_connector_add(connector);
2010
2011 if (has_aux)
2012 radeon_dp_aux_init(radeon_connector);
2013
2003 return; 2014 return;
2004 2015
2005failed: 2016failed:
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 4392b7c95ee6..e8b0284e34bb 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -79,7 +79,8 @@
79 * 2.35.0 - Add CIK macrotile mode array query 79 * 2.35.0 - Add CIK macrotile mode array query
80 * 2.36.0 - Fix CIK DCE tiling setup 80 * 2.36.0 - Fix CIK DCE tiling setup
81 * 2.37.0 - allow GS ring setup on r6xx/r7xx 81 * 2.37.0 - allow GS ring setup on r6xx/r7xx
82 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN) 82 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
83 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
83 */ 84 */
84#define KMS_DRIVER_MAJOR 2 85#define KMS_DRIVER_MAJOR 2
85#define KMS_DRIVER_MINOR 38 86#define KMS_DRIVER_MINOR 38
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 402dbe32c234..832d9fa1a4c4 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -192,6 +192,7 @@ struct radeon_i2c_chan {
192 struct i2c_algo_dp_aux_data dp; 192 struct i2c_algo_dp_aux_data dp;
193 } algo; 193 } algo;
194 struct radeon_i2c_bus_rec rec; 194 struct radeon_i2c_bus_rec rec;
195 struct drm_dp_aux aux;
195}; 196};
196 197
197/* mostly for macs, but really any system without connector tables */ 198/* mostly for macs, but really any system without connector tables */
@@ -690,6 +691,9 @@ extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
690extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 691extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
691extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 692extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
692 struct drm_connector *connector); 693 struct drm_connector *connector);
694extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
695 u8 power_state);
696extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
693extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 697extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
694extern void radeon_atom_encoder_init(struct radeon_device *rdev); 698extern void radeon_atom_encoder_init(struct radeon_device *rdev);
695extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 699extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 02:34:15 -0400