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authorJohn W. Linville <linville@tuxdriver.com>2011-08-24 14:08:41 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-08-26 10:47:57 -0400
commit22c55e6e7ed46ad3734c206d90b5ccba3b318d22 (patch)
tree500f138a0e99248ae6e74518e8105b62cff11395
parentea5a08cfa5fe9d10333eb7d65a7158ab766dae93 (diff)
ath9k: remove replicated null check in ath_pci_aspm_init
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index d704c8d9bae7..91c2e64de799 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -115,6 +115,8 @@ static void ath_pci_aspm_init(struct ath_common *common)
115 return; 115 return;
116 116
117 parent = pdev->bus->self; 117 parent = pdev->bus->self;
118 if (!parent)
119 return;
118 120
119 if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) { 121 if (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) {
120 /* Bluetooth coexistance requires disabling ASPM. */ 122 /* Bluetooth coexistance requires disabling ASPM. */
@@ -126,9 +128,6 @@ static void ath_pci_aspm_init(struct ath_common *common)
126 * Both upstream and downstream PCIe components should 128 * Both upstream and downstream PCIe components should
127 * have the same ASPM settings. 129 * have the same ASPM settings.
128 */ 130 */
129 if (!parent)
130 return;
131
132 pos = pci_pcie_cap(parent); 131 pos = pci_pcie_cap(parent);
133 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 132 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
134 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 133 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
@@ -137,9 +136,6 @@ static void ath_pci_aspm_init(struct ath_common *common)
137 return; 136 return;
138 } 137 }
139 138
140 if (!parent)
141 return;
142
143 pos = pci_pcie_cap(parent); 139 pos = pci_pcie_cap(parent);
144 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 140 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
145 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 141 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {