diff options
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-24 11:29:06 -0500 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-02-28 06:04:53 -0500 |
| commit | 225b02163cd51b6d5ebef4d2e19a09345f2ee3a5 (patch) | |
| tree | fc86d2f4c738b90de28828e662a7ef17353aaa1b | |
| parent | d5cf89c9ec7761e48e016460d26221533e2f6c7b (diff) | |
ARM: sun6i: dt: Fix mod0 compatible
The module 0 clock compatibles were changed between the time the patch was sent
and it was merged. Update the compatibles.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index af6f87c4e1c7..42f310a925c4 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi | |||
| @@ -200,7 +200,7 @@ | |||
| 200 | 200 | ||
| 201 | spi0_clk: clk@01c200a0 { | 201 | spi0_clk: clk@01c200a0 { |
| 202 | #clock-cells = <0>; | 202 | #clock-cells = <0>; |
| 203 | compatible = "allwinner,sun4i-mod0-clk"; | 203 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 204 | reg = <0x01c200a0 0x4>; | 204 | reg = <0x01c200a0 0x4>; |
| 205 | clocks = <&osc24M>, <&pll6>; | 205 | clocks = <&osc24M>, <&pll6>; |
| 206 | clock-output-names = "spi0"; | 206 | clock-output-names = "spi0"; |
| @@ -208,7 +208,7 @@ | |||
| 208 | 208 | ||
| 209 | spi1_clk: clk@01c200a4 { | 209 | spi1_clk: clk@01c200a4 { |
| 210 | #clock-cells = <0>; | 210 | #clock-cells = <0>; |
| 211 | compatible = "allwinner,sun4i-mod0-clk"; | 211 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 212 | reg = <0x01c200a4 0x4>; | 212 | reg = <0x01c200a4 0x4>; |
| 213 | clocks = <&osc24M>, <&pll6>; | 213 | clocks = <&osc24M>, <&pll6>; |
| 214 | clock-output-names = "spi1"; | 214 | clock-output-names = "spi1"; |
| @@ -216,7 +216,7 @@ | |||
| 216 | 216 | ||
| 217 | spi2_clk: clk@01c200a8 { | 217 | spi2_clk: clk@01c200a8 { |
| 218 | #clock-cells = <0>; | 218 | #clock-cells = <0>; |
| 219 | compatible = "allwinner,sun4i-mod0-clk"; | 219 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 220 | reg = <0x01c200a8 0x4>; | 220 | reg = <0x01c200a8 0x4>; |
| 221 | clocks = <&osc24M>, <&pll6>; | 221 | clocks = <&osc24M>, <&pll6>; |
| 222 | clock-output-names = "spi2"; | 222 | clock-output-names = "spi2"; |
| @@ -224,7 +224,7 @@ | |||
| 224 | 224 | ||
| 225 | spi3_clk: clk@01c200ac { | 225 | spi3_clk: clk@01c200ac { |
| 226 | #clock-cells = <0>; | 226 | #clock-cells = <0>; |
| 227 | compatible = "allwinner,sun4i-mod0-clk"; | 227 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 228 | reg = <0x01c200ac 0x4>; | 228 | reg = <0x01c200ac 0x4>; |
| 229 | clocks = <&osc24M>, <&pll6>; | 229 | clocks = <&osc24M>, <&pll6>; |
| 230 | clock-output-names = "spi3"; | 230 | clock-output-names = "spi3"; |