Merge branch 'samsung/exynos-multiplatform-drivers' into late/multiplatform

This series contains the final pieces for Exynos multiplatform support:
Most of the patches are about the exynos-combiner irqchip, which is
converted to not rely on platform provided constants.

* samsung/exynos-multiplatform-drivers:
  ARM: exynos: restore mach/regs-clock.h for exynos5
  irqchip: exynos: look up irq using irq_find_mapping
  irqchip: exynos: pass irq_base from platform
  irqchip: exynos: localize irq lookup for ATAGS
  irqchip: exynos: allocate combiner_data dynamically
  irqchip: exynos: pass max combiner number to combiner_init
  ARM: exynos: add missing properties for combiner IRQs
  clocksource: exynos_mct: remove platform header dependency
  clk: exynos: prepare for multiplatform

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

11 files changed, 152 insertions, 137 deletions

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 15143bdbafb8..5feccffae409 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -41,6 +41,7 @@
         };
 
         combiner:interrupt-controller@10440000 {
+                samsung,combiner-nr = <16>;
                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 36d4299789ef..c0f60f49cea6 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -26,6 +26,15 @@
                 cpu-offset = <0x8000>;
         };
 
+        interrupt-controller@10440000 {
+                samsung,combiner-nr = <18>;
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                             <0 107 0>, <0 108 0>;
+        };
+
         mct@10050000 {
                 compatible = "samsung,exynos4412-mct";
                 reg = <0x10050000 0x800>;
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d75c047e80a9..f433206bd3c5 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -26,6 +26,15 @@
                 cpu-offset = <0x4000>;
         };
 
+        interrupt-controller@10440000 {
+                samsung,combiner-nr = <20>;
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                             <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
+        };
+
         mct@10050000 {
                 compatible = "samsung,exynos4412-mct";
                 reg = <0x10050000 0x800>;
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index a3ab0ecc7c6a..9208079d5d52 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -413,13 +413,26 @@ void __init exynos_init_time(void)
         } else {
                 /* todo: remove after migrating legacy E4 platforms to dt */
 #ifdef CONFIG_ARCH_EXYNOS4
-                exynos4_clk_init(NULL);
+                exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
-                mct_init();
+                mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
         }
 }
 
+static unsigned int max_combiner_nr(void)
+{
+        if (soc_is_exynos5250())
+                return EXYNOS5_MAX_COMBINER_NR;
+        else if (soc_is_exynos4412())
+                return EXYNOS4412_MAX_COMBINER_NR;
+        else if (soc_is_exynos4212())
+                return EXYNOS4212_MAX_COMBINER_NR;
+        else
+                return EXYNOS4210_MAX_COMBINER_NR;
+}
+
+
 void __init exynos4_init_irq(void)
 {
         unsigned int gic_bank_offset;
@@ -434,7 +447,8 @@ void __init exynos4_init_irq(void)
 #endif
 
         if (!of_have_populated_dt())
-                combiner_init(S5P_VA_COMBINER_BASE, NULL);
+                combiner_init(S5P_VA_COMBINER_BASE, NULL,
+                              max_combiner_nr(), COMBINER_IRQ(0, 0));
 
         /*
          * The parameters of s5p_init_irq() are for VIC init.
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index cb89ab886950..3e72d03a385e 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -14,7 +14,7 @@
 
 #include <linux/of.h>
 
-extern void mct_init(void);
+void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 void exynos_init_time(void);
 extern unsigned long xxti_f, xusbxti_f;
 
@@ -27,7 +27,7 @@ void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
 /* ToDo: remove these after migrating legacy exynos4 platforms to dt */
-void exynos4_clk_init(struct device_node *np);
+void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom);
 void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
 
 #ifdef CONFIG_PM_GENERIC_DOMAINS
@@ -69,7 +69,8 @@ void exynos4212_register_clocks(void);
 #endif
 
 struct device_node;
-void combiner_init(void __iomem *combiner_base, struct device_node *np);
+void combiner_init(void __iomem *combiner_base, struct device_node *np,
+                        unsigned int max_nr, int irq_base);
 
 extern struct smp_operations exynos_smp_ops;
 
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 71046694d9dd..d0940e69d034 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -16,7 +16,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <plat/cpu.h>
 #include "clk.h"
 #include "clk-pll.h"
 
@@ -910,16 +909,6 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
                         CLK_IGNORE_UNUSED, 0),
 };
 
-#ifdef CONFIG_OF
-static struct of_device_id exynos4_clk_ids[] __initdata = {
-        { .compatible = "samsung,exynos4210-clock",
-                        .data = (void *)EXYNOS4210, },
-        { .compatible = "samsung,exynos4412-clock",
-                        .data = (void *)EXYNOS4X12, },
-        { },
-};
-#endif
-
 /*
  * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
  * resides in chipid register space, outside of the clock controller memory
@@ -927,33 +916,40 @@ static struct of_device_id exynos4_clk_ids[] __initdata = {
  * controller is first remapped and the value of XOM[0] bit is read to
  * determine the parent clock.
  */
-static void __init exynos4_clk_register_finpll(void)
+static unsigned long exynos4_get_xom(void)
 {
-        struct samsung_fixed_rate_clock fclk;
+        unsigned long xom = 0;
+        void __iomem *chipid_base;
         struct device_node *np;
-        struct clk *clk;
-        void __iomem *chipid_base = S5P_VA_CHIPID;
-        unsigned long xom, finpll_f = 24000000;
-        char *parent_name;
 
         np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
-        if (np)
+        if (np) {
                 chipid_base = of_iomap(np, 0);
 
-        if (chipid_base) {
-                xom = readl(chipid_base + 8);
-                parent_name = xom & 1 ? "xusbxti" : "xxti";
-                clk = clk_get(NULL, parent_name);
-                if (IS_ERR(clk)) {
-                        pr_err("%s: failed to lookup parent clock %s, assuming "
-                                "fin_pll clock frequency is 24MHz\n", __func__,
-                                parent_name);
-                } else {
-                        finpll_f = clk_get_rate(clk);
-                }
+                if (chipid_base)
+                        xom = readl(chipid_base + 8);
+
+                iounmap(chipid_base);
+        }
+
+        return xom;
+}
+
+static void __init exynos4_clk_register_finpll(unsigned long xom)
+{
+        struct samsung_fixed_rate_clock fclk;
+        struct clk *clk;
+        unsigned long finpll_f = 24000000;
+        char *parent_name;
+
+        parent_name = xom & 1 ? "xusbxti" : "xxti";
+        clk = clk_get(NULL, parent_name);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to lookup parent clock %s, assuming "
+                        "fin_pll clock frequency is 24MHz\n", __func__,
+                        parent_name);
         } else {
-                pr_err("%s: failed to map chipid registers, assuming "
-                        "fin_pll clock frequency is 24MHz\n", __func__);
+                finpll_f = clk_get_rate(clk);
         }
 
         fclk.id = fin_pll;
@@ -963,8 +959,6 @@ static void __init exynos4_clk_register_finpll(void)
         fclk.fixed_rate = finpll_f;
         samsung_clk_register_fixed_rate(&fclk, 1);
 
-        if (np)
-                iounmap(chipid_base);
 }
 
 /*
@@ -988,28 +982,14 @@ static __initdata struct of_device_id ext_clk_match[] = {
 };
 
 /* register exynos4 clocks */
-void __init exynos4_clk_init(struct device_node *np)
+void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom)
 {
-        void __iomem *reg_base;
         struct clk *apll, *mpll, *epll, *vpll;
-        u32 exynos4_soc;
 
         if (np) {
-                const struct of_device_id *match;
-                match = of_match_node(exynos4_clk_ids, np);
-                exynos4_soc = (u32)match->data;
-
                 reg_base = of_iomap(np, 0);
                 if (!reg_base)
                         panic("%s: failed to map registers\n", __func__);
-        } else {
-                reg_base = S5P_VA_CMU;
-                if (soc_is_exynos4210())
-                        exynos4_soc = EXYNOS4210;
-                else if (soc_is_exynos4212() || soc_is_exynos4412())
-                        exynos4_soc = EXYNOS4X12;
-                else
-                        panic("%s: unable to determine soc\n", __func__);
         }
 
         if (exynos4_soc == EXYNOS4210)
@@ -1026,7 +1006,7 @@ void __init exynos4_clk_init(struct device_node *np)
                         ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
                         ext_clk_match);
 
-        exynos4_clk_register_finpll();
+        exynos4_clk_register_finpll(xom);
 
         if (exynos4_soc == EXYNOS4210) {
                 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
@@ -1087,5 +1067,16 @@ void __init exynos4_clk_init(struct device_node *np)
                 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
                 _get_rate("arm_clk"));
 }
-CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
-CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
+
+
+static void __init exynos4210_clk_init(struct device_node *np)
+{
+        exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom());
+}
+CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
+
+static void __init exynos4412_clk_init(struct device_node *np)
+{
+        exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom());
+}
+CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 7290faa518d2..61068cda2ab3 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -16,7 +16,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <plat/cpu.h>
 #include "clk.h"
 #include "clk-pll.h"
 
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index a0a094c06f19..7d5434167a96 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -15,7 +15,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <plat/cpu.h>
 #include "clk.h"
 #include "clk-pll.h"
 
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 10b2111f0c0f..e4ad6ea9aa76 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -20,8 +20,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
-#include <mach/map.h>
-
 /**
  * struct samsung_clock_alias: information about mux clock
  * @id: platform specific id of the clock.
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 661026834b23..a6ca0fb06939 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -26,11 +26,6 @@
 
 #include <asm/arch_timer.h>
 #include <asm/localtimer.h>
-
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
 #include <asm/mach/time.h>
 
 #define EXYNOS4_MCTREG(x)               (x)
@@ -511,18 +506,14 @@ static void __init exynos4_timer_resources(struct device_node *np, void __iomem
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
-void __init mct_init(void)
+void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
 {
-        if (soc_is_exynos4210()) {
-                mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
-                mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
-                mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
-                mct_int_type = MCT_INT_SPI;
-        } else {
-                panic("unable to determine mct controller type\n");
-        }
+        mct_irqs[MCT_G0_IRQ] = irq_g0;
+        mct_irqs[MCT_L0_IRQ] = irq_l0;
+        mct_irqs[MCT_L1_IRQ] = irq_l1;
+        mct_int_type = MCT_INT_SPI;
 
-        exynos4_timer_resources(NULL, S5P_VA_SYSTIMER);
+        exynos4_timer_resources(NULL, base);
         exynos4_clocksource_init();
         exynos4_clockevent_init();
 }
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index e8501dbaa0b7..494c2e21b538 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -12,12 +12,15 @@
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/slab.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <asm/mach/irq.h>
 
+#ifdef CONFIG_EXYNOS_ATAGS
 #include <plat/cpu.h>
+#endif
 
 #include "irqchip.h"
 
@@ -25,17 +28,18 @@
 #define COMBINER_ENABLE_CLEAR   0x4
 #define COMBINER_INT_STATUS     0xC
 
+#define IRQ_IN_COMBINER         8
+
 static DEFINE_SPINLOCK(irq_controller_lock);
 
 struct combiner_chip_data {
-        unsigned int irq_offset;
+        unsigned int hwirq_offset;
         unsigned int irq_mask;
         void __iomem *base;
         unsigned int parent_irq;
 };
 
 static struct irq_domain *combiner_irq_domain;
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 
 static inline void __iomem *combiner_base(struct irq_data *data)
 {
@@ -76,11 +80,11 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         if (status == 0)
                 goto out;
 
-        combiner_irq = __ffs(status);
+        combiner_irq = chip_data->hwirq_offset + __ffs(status);
+        cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
 
-        cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
-        if (unlikely(cascade_irq >= NR_IRQS))
-                do_bad_IRQ(cascade_irq, desc);
+        if (unlikely(!cascade_irq))
+                do_bad_IRQ(irq, desc);
         else
                 generic_handle_irq(cascade_irq);
 
@@ -112,40 +116,25 @@ static struct irq_chip combiner_chip = {
 #endif
 };
 
-static unsigned int max_combiner_nr(void)
-{
-        if (soc_is_exynos5250())
-                return EXYNOS5_MAX_COMBINER_NR;
-        else if (soc_is_exynos4412())
-                return EXYNOS4412_MAX_COMBINER_NR;
-        else if (soc_is_exynos4212())
-                return EXYNOS4212_MAX_COMBINER_NR;
-        else
-                return EXYNOS4210_MAX_COMBINER_NR;
-}
-
-static void __init combiner_cascade_irq(unsigned int combiner_nr,
+static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data,
                                         unsigned int irq)
 {
-        if (combiner_nr >= max_combiner_nr())
-                BUG();
-        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
+        if (irq_set_handler_data(irq, combiner_data) != 0)
                 BUG();
         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
-static void __init combiner_init_one(unsigned int combiner_nr,
+static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
+                                     unsigned int combiner_nr,
                                      void __iomem *base, unsigned int irq)
 {
-        combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_find_mapping(
-                combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
-        combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
-        combiner_data[combiner_nr].parent_irq = irq;
+        combiner_data->base = base;
+        combiner_data->hwirq_offset = (combiner_nr & ~3) * IRQ_IN_COMBINER;
+        combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
+        combiner_data->parent_irq = irq;
 
         /* Disable all interrupts */
-        __raw_writel(combiner_data[combiner_nr].irq_mask,
-                     base + COMBINER_ENABLE_CLEAR);
+        __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
 }
 
 #ifdef CONFIG_OF
@@ -161,7 +150,7 @@ static int combiner_irq_domain_xlate(struct irq_domain *d,
         if (intsize < 2)
                 return -EINVAL;
 
-        *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
+        *out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1];
         *out_type = 0;
 
         return 0;
@@ -180,6 +169,8 @@ static int combiner_irq_domain_xlate(struct irq_domain *d,
 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
                                    irq_hw_number_t hw)
 {
+        struct combiner_chip_data *combiner_data = d->host_data;
+
         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
@@ -192,8 +183,12 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
         .map    = combiner_irq_domain_map,
 };
 
-static unsigned int exynos4x12_combiner_extra_irq(int group)
+static unsigned int combiner_lookup_irq(int group)
 {
+#ifdef CONFIG_EXYNOS_ATAGS
+        if (group < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
+                return IRQ_SPI(group);
+
         switch (group) {
         case 16:
                 return IRQ_SPI(107);
@@ -203,53 +198,46 @@ static unsigned int exynos4x12_combiner_extra_irq(int group)
                 return IRQ_SPI(48);
         case 19:
                 return IRQ_SPI(42);
-        default:
-                return 0;
         }
+#endif
+        return 0;
 }
 
 void __init combiner_init(void __iomem *combiner_base,
-                          struct device_node *np)
+                          struct device_node *np,
+                          unsigned int max_nr,
+                          int irq_base)
 {
-        int i, irq, irq_base;
-        unsigned int max_nr, nr_irq;
+        int i, irq;
+        unsigned int nr_irq;
+        struct combiner_chip_data *combiner_data;
 
-        max_nr = max_combiner_nr();
+        nr_irq = max_nr * IRQ_IN_COMBINER;
 
-        if (np) {
-                if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
-                        pr_info("%s: number of combiners not specified, "
-                                "setting default as %d.\n",
-                                __func__, max_nr);
-                }
-        }
-
-        nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
-
-        irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
-        if (IS_ERR_VALUE(irq_base)) {
-                irq_base = COMBINER_IRQ(0, 0);
-                pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
+        combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL);
+        if (!combiner_data) {
+                pr_warning("%s: could not allocate combiner data\n", __func__);
+                return;
         }
 
-        combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
-                                &combiner_irq_domain_ops, &combiner_data);
+        combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base,
+                                &combiner_irq_domain_ops, combiner_data);
         if (WARN_ON(!combiner_irq_domain)) {
                 pr_warning("%s: irq domain init failed\n", __func__);
                 return;
         }
 
         for (i = 0; i < max_nr; i++) {
-                if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
-                        irq = IRQ_SPI(i);
-                else
-                        irq = exynos4x12_combiner_extra_irq(i);
 #ifdef CONFIG_OF
                 if (np)
                         irq = irq_of_parse_and_map(np, i);
+                else
 #endif
-                combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
-                combiner_cascade_irq(i, irq);
+                        irq = combiner_lookup_irq(i);
+
+                combiner_init_one(&combiner_data[i], i,
+                                  combiner_base + (i >> 2) * 0x10, irq);
+                combiner_cascade_irq(&combiner_data[i], irq);
         }
 }
 
@@ -258,6 +246,8 @@ static int __init combiner_of_init(struct device_node *np,
                                    struct device_node *parent)
 {
         void __iomem *combiner_base;
+        unsigned int max_nr = 20;
+        int irq_base = -1;
 
         combiner_base = of_iomap(np, 0);
         if (!combiner_base) {
@@ -265,7 +255,20 @@ static int __init combiner_of_init(struct device_node *np,
                 return -ENXIO;
         }
 
-        combiner_init(combiner_base, np);
+        if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
+                pr_info("%s: number of combiners not specified, "
+                        "setting default as %d.\n",
+                        __func__, max_nr);
+        }
+
+        /* 
+         * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices
+         * get their IRQ from DT, remove this in order to get dynamic
+         * allocation.
+         */
+        irq_base = 160;
+
+        combiner_init(combiner_base, np, max_nr, irq_base);
 
         return 0;
 }