diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2012-02-22 07:35:21 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2012-02-23 01:57:17 -0500 |
commit | 21f7638e6f05c36b35a36cd4311e08be5dc00bb1 (patch) | |
tree | 2d88f0e8299cbc613dce1509293f349fe6bf93bb | |
parent | c71013597d49c7ca8bb5049f0c7873df2643fad5 (diff) |
tg3: Create timer helper functions
This patch seeks to clean up the timer related code. It begins by
moving one-time timer setup code from tg3_open() to tg3_init_one().
It then creates a function that encapsulates the code needed to start
the timer. A tg3_timer_stop() function was added for parity. Finally,
this patch moves all the timer functions to a more suitable location.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 208 |
1 files changed, 112 insertions, 96 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 21b39c5ffb4b..ec5bc3d04333 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c | |||
@@ -204,6 +204,7 @@ static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits) | |||
204 | #define TG3_RAW_IP_ALIGN 2 | 204 | #define TG3_RAW_IP_ALIGN 2 |
205 | 205 | ||
206 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 | 206 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
207 | #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) | ||
207 | 208 | ||
208 | #define FIRMWARE_TG3 "tigon/tg3.bin" | 209 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
209 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | 210 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" |
@@ -9328,74 +9329,6 @@ static int tg3_init_hw(struct tg3 *tp, int reset_phy) | |||
9328 | return tg3_reset_hw(tp, reset_phy); | 9329 | return tg3_reset_hw(tp, reset_phy); |
9329 | } | 9330 | } |
9330 | 9331 | ||
9331 | /* Restart hardware after configuration changes, self-test, etc. | ||
9332 | * Invoked with tp->lock held. | ||
9333 | */ | ||
9334 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | ||
9335 | __releases(tp->lock) | ||
9336 | __acquires(tp->lock) | ||
9337 | { | ||
9338 | int err; | ||
9339 | |||
9340 | err = tg3_init_hw(tp, reset_phy); | ||
9341 | if (err) { | ||
9342 | netdev_err(tp->dev, | ||
9343 | "Failed to re-initialize device, aborting\n"); | ||
9344 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | ||
9345 | tg3_full_unlock(tp); | ||
9346 | del_timer_sync(&tp->timer); | ||
9347 | tp->irq_sync = 0; | ||
9348 | tg3_napi_enable(tp); | ||
9349 | dev_close(tp->dev); | ||
9350 | tg3_full_lock(tp, 0); | ||
9351 | } | ||
9352 | return err; | ||
9353 | } | ||
9354 | |||
9355 | static void tg3_reset_task(struct work_struct *work) | ||
9356 | { | ||
9357 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | ||
9358 | int err; | ||
9359 | |||
9360 | tg3_full_lock(tp, 0); | ||
9361 | |||
9362 | if (!netif_running(tp->dev)) { | ||
9363 | tg3_flag_clear(tp, RESET_TASK_PENDING); | ||
9364 | tg3_full_unlock(tp); | ||
9365 | return; | ||
9366 | } | ||
9367 | |||
9368 | tg3_full_unlock(tp); | ||
9369 | |||
9370 | tg3_phy_stop(tp); | ||
9371 | |||
9372 | tg3_netif_stop(tp); | ||
9373 | |||
9374 | tg3_full_lock(tp, 1); | ||
9375 | |||
9376 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { | ||
9377 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | ||
9378 | tp->write32_rx_mbox = tg3_write_flush_reg32; | ||
9379 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | ||
9380 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | ||
9381 | } | ||
9382 | |||
9383 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | ||
9384 | err = tg3_init_hw(tp, 1); | ||
9385 | if (err) | ||
9386 | goto out; | ||
9387 | |||
9388 | tg3_netif_start(tp); | ||
9389 | |||
9390 | out: | ||
9391 | tg3_full_unlock(tp); | ||
9392 | |||
9393 | if (!err) | ||
9394 | tg3_phy_start(tp); | ||
9395 | |||
9396 | tg3_flag_clear(tp, RESET_TASK_PENDING); | ||
9397 | } | ||
9398 | |||
9399 | #define TG3_STAT_ADD32(PSTAT, REG) \ | 9332 | #define TG3_STAT_ADD32(PSTAT, REG) \ |
9400 | do { u32 __val = tr32(REG); \ | 9333 | do { u32 __val = tr32(REG); \ |
9401 | (PSTAT)->low += __val; \ | 9334 | (PSTAT)->low += __val; \ |
@@ -9608,6 +9541,108 @@ restart_timer: | |||
9608 | add_timer(&tp->timer); | 9541 | add_timer(&tp->timer); |
9609 | } | 9542 | } |
9610 | 9543 | ||
9544 | static void __devinit tg3_timer_init(struct tg3 *tp) | ||
9545 | { | ||
9546 | if (tg3_flag(tp, TAGGED_STATUS) && | ||
9547 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | ||
9548 | !tg3_flag(tp, 57765_CLASS)) | ||
9549 | tp->timer_offset = HZ; | ||
9550 | else | ||
9551 | tp->timer_offset = HZ / 10; | ||
9552 | |||
9553 | BUG_ON(tp->timer_offset > HZ); | ||
9554 | |||
9555 | tp->timer_multiplier = (HZ / tp->timer_offset); | ||
9556 | tp->asf_multiplier = (HZ / tp->timer_offset) * | ||
9557 | TG3_FW_UPDATE_FREQ_SEC; | ||
9558 | |||
9559 | init_timer(&tp->timer); | ||
9560 | tp->timer.data = (unsigned long) tp; | ||
9561 | tp->timer.function = tg3_timer; | ||
9562 | } | ||
9563 | |||
9564 | static void tg3_timer_start(struct tg3 *tp) | ||
9565 | { | ||
9566 | tp->asf_counter = tp->asf_multiplier; | ||
9567 | tp->timer_counter = tp->timer_multiplier; | ||
9568 | |||
9569 | tp->timer.expires = jiffies + tp->timer_offset; | ||
9570 | add_timer(&tp->timer); | ||
9571 | } | ||
9572 | |||
9573 | static void tg3_timer_stop(struct tg3 *tp) | ||
9574 | { | ||
9575 | del_timer_sync(&tp->timer); | ||
9576 | } | ||
9577 | |||
9578 | /* Restart hardware after configuration changes, self-test, etc. | ||
9579 | * Invoked with tp->lock held. | ||
9580 | */ | ||
9581 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | ||
9582 | __releases(tp->lock) | ||
9583 | __acquires(tp->lock) | ||
9584 | { | ||
9585 | int err; | ||
9586 | |||
9587 | err = tg3_init_hw(tp, reset_phy); | ||
9588 | if (err) { | ||
9589 | netdev_err(tp->dev, | ||
9590 | "Failed to re-initialize device, aborting\n"); | ||
9591 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | ||
9592 | tg3_full_unlock(tp); | ||
9593 | tg3_timer_stop(tp); | ||
9594 | tp->irq_sync = 0; | ||
9595 | tg3_napi_enable(tp); | ||
9596 | dev_close(tp->dev); | ||
9597 | tg3_full_lock(tp, 0); | ||
9598 | } | ||
9599 | return err; | ||
9600 | } | ||
9601 | |||
9602 | static void tg3_reset_task(struct work_struct *work) | ||
9603 | { | ||
9604 | struct tg3 *tp = container_of(work, struct tg3, reset_task); | ||
9605 | int err; | ||
9606 | |||
9607 | tg3_full_lock(tp, 0); | ||
9608 | |||
9609 | if (!netif_running(tp->dev)) { | ||
9610 | tg3_flag_clear(tp, RESET_TASK_PENDING); | ||
9611 | tg3_full_unlock(tp); | ||
9612 | return; | ||
9613 | } | ||
9614 | |||
9615 | tg3_full_unlock(tp); | ||
9616 | |||
9617 | tg3_phy_stop(tp); | ||
9618 | |||
9619 | tg3_netif_stop(tp); | ||
9620 | |||
9621 | tg3_full_lock(tp, 1); | ||
9622 | |||
9623 | if (tg3_flag(tp, TX_RECOVERY_PENDING)) { | ||
9624 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | ||
9625 | tp->write32_rx_mbox = tg3_write_flush_reg32; | ||
9626 | tg3_flag_set(tp, MBOX_WRITE_REORDER); | ||
9627 | tg3_flag_clear(tp, TX_RECOVERY_PENDING); | ||
9628 | } | ||
9629 | |||
9630 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); | ||
9631 | err = tg3_init_hw(tp, 1); | ||
9632 | if (err) | ||
9633 | goto out; | ||
9634 | |||
9635 | tg3_netif_start(tp); | ||
9636 | |||
9637 | out: | ||
9638 | tg3_full_unlock(tp); | ||
9639 | |||
9640 | if (!err) | ||
9641 | tg3_phy_start(tp); | ||
9642 | |||
9643 | tg3_flag_clear(tp, RESET_TASK_PENDING); | ||
9644 | } | ||
9645 | |||
9611 | static int tg3_request_irq(struct tg3 *tp, int irq_num) | 9646 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
9612 | { | 9647 | { |
9613 | irq_handler_t fn; | 9648 | irq_handler_t fn; |
@@ -9973,24 +10008,6 @@ static int tg3_open(struct net_device *dev) | |||
9973 | if (err) { | 10008 | if (err) { |
9974 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | 10009 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
9975 | tg3_free_rings(tp); | 10010 | tg3_free_rings(tp); |
9976 | } else { | ||
9977 | if (tg3_flag(tp, TAGGED_STATUS) && | ||
9978 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | ||
9979 | !tg3_flag(tp, 57765_CLASS)) | ||
9980 | tp->timer_offset = HZ; | ||
9981 | else | ||
9982 | tp->timer_offset = HZ / 10; | ||
9983 | |||
9984 | BUG_ON(tp->timer_offset > HZ); | ||
9985 | tp->timer_counter = tp->timer_multiplier = | ||
9986 | (HZ / tp->timer_offset); | ||
9987 | tp->asf_counter = tp->asf_multiplier = | ||
9988 | ((HZ / tp->timer_offset) * 2); | ||
9989 | |||
9990 | init_timer(&tp->timer); | ||
9991 | tp->timer.expires = jiffies + tp->timer_offset; | ||
9992 | tp->timer.data = (unsigned long) tp; | ||
9993 | tp->timer.function = tg3_timer; | ||
9994 | } | 10011 | } |
9995 | 10012 | ||
9996 | tg3_full_unlock(tp); | 10013 | tg3_full_unlock(tp); |
@@ -10022,7 +10039,7 @@ static int tg3_open(struct net_device *dev) | |||
10022 | 10039 | ||
10023 | tg3_full_lock(tp, 0); | 10040 | tg3_full_lock(tp, 0); |
10024 | 10041 | ||
10025 | add_timer(&tp->timer); | 10042 | tg3_timer_start(tp); |
10026 | tg3_flag_set(tp, INIT_COMPLETE); | 10043 | tg3_flag_set(tp, INIT_COMPLETE); |
10027 | tg3_enable_ints(tp); | 10044 | tg3_enable_ints(tp); |
10028 | 10045 | ||
@@ -10067,7 +10084,7 @@ static int tg3_close(struct net_device *dev) | |||
10067 | 10084 | ||
10068 | netif_tx_stop_all_queues(dev); | 10085 | netif_tx_stop_all_queues(dev); |
10069 | 10086 | ||
10070 | del_timer_sync(&tp->timer); | 10087 | tg3_timer_stop(tp); |
10071 | 10088 | ||
10072 | tg3_phy_stop(tp); | 10089 | tg3_phy_stop(tp); |
10073 | 10090 | ||
@@ -15701,6 +15718,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, | |||
15701 | tg3_frob_aux_power(tp, false); | 15718 | tg3_frob_aux_power(tp, false); |
15702 | } | 15719 | } |
15703 | 15720 | ||
15721 | tg3_timer_init(tp); | ||
15722 | |||
15704 | err = register_netdev(dev); | 15723 | err = register_netdev(dev); |
15705 | if (err) { | 15724 | if (err) { |
15706 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); | 15725 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
@@ -15826,7 +15845,7 @@ static int tg3_suspend(struct device *device) | |||
15826 | tg3_phy_stop(tp); | 15845 | tg3_phy_stop(tp); |
15827 | tg3_netif_stop(tp); | 15846 | tg3_netif_stop(tp); |
15828 | 15847 | ||
15829 | del_timer_sync(&tp->timer); | 15848 | tg3_timer_stop(tp); |
15830 | 15849 | ||
15831 | tg3_full_lock(tp, 1); | 15850 | tg3_full_lock(tp, 1); |
15832 | tg3_disable_ints(tp); | 15851 | tg3_disable_ints(tp); |
@@ -15850,8 +15869,7 @@ static int tg3_suspend(struct device *device) | |||
15850 | if (err2) | 15869 | if (err2) |
15851 | goto out; | 15870 | goto out; |
15852 | 15871 | ||
15853 | tp->timer.expires = jiffies + tp->timer_offset; | 15872 | tg3_timer_start(tp); |
15854 | add_timer(&tp->timer); | ||
15855 | 15873 | ||
15856 | netif_device_attach(dev); | 15874 | netif_device_attach(dev); |
15857 | tg3_netif_start(tp); | 15875 | tg3_netif_start(tp); |
@@ -15885,8 +15903,7 @@ static int tg3_resume(struct device *device) | |||
15885 | if (err) | 15903 | if (err) |
15886 | goto out; | 15904 | goto out; |
15887 | 15905 | ||
15888 | tp->timer.expires = jiffies + tp->timer_offset; | 15906 | tg3_timer_start(tp); |
15889 | add_timer(&tp->timer); | ||
15890 | 15907 | ||
15891 | tg3_netif_start(tp); | 15908 | tg3_netif_start(tp); |
15892 | 15909 | ||
@@ -15934,7 +15951,7 @@ static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev, | |||
15934 | 15951 | ||
15935 | tg3_netif_stop(tp); | 15952 | tg3_netif_stop(tp); |
15936 | 15953 | ||
15937 | del_timer_sync(&tp->timer); | 15954 | tg3_timer_stop(tp); |
15938 | 15955 | ||
15939 | /* Want to make sure that the reset task doesn't run */ | 15956 | /* Want to make sure that the reset task doesn't run */ |
15940 | tg3_reset_task_cancel(tp); | 15957 | tg3_reset_task_cancel(tp); |
@@ -16030,8 +16047,7 @@ static void tg3_io_resume(struct pci_dev *pdev) | |||
16030 | 16047 | ||
16031 | netif_device_attach(netdev); | 16048 | netif_device_attach(netdev); |
16032 | 16049 | ||
16033 | tp->timer.expires = jiffies + tp->timer_offset; | 16050 | tg3_timer_start(tp); |
16034 | add_timer(&tp->timer); | ||
16035 | 16051 | ||
16036 | tg3_netif_start(tp); | 16052 | tg3_netif_start(tp); |
16037 | 16053 | ||