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authorAlex Deucher <alexander.deucher@amd.com>2013-08-06 16:58:53 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-11-08 12:33:41 -0500
commit21e438af6413496a970e491cb4b3e7449f452a10 (patch)
treebb9231f033502603fa2ecf244f4410b645ef06ab
parent939c0d3c08124cd7707168525c47354952c62d8d (diff)
drm/radeon: update cik_tiling_mode_table_init() for hawaii
Hawaii uses a different tiling configuration. Add support for it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/cik.c222
-rw-r--r--drivers/gpu/drm/radeon/cikd.h2
2 files changed, 222 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e91a2403b125..b3b2da671c6c 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1758,9 +1758,227 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
1758 1758
1759 num_pipe_configs = rdev->config.cik.max_tile_pipes; 1759 num_pipe_configs = rdev->config.cik.max_tile_pipes;
1760 if (num_pipe_configs > 8) 1760 if (num_pipe_configs > 8)
1761 num_pipe_configs = 8; /* ??? */ 1761 num_pipe_configs = 16;
1762 1762
1763 if (num_pipe_configs == 8) { 1763 if (num_pipe_configs == 16) {
1764 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1765 switch (reg_offset) {
1766 case 0:
1767 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1768 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1769 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1770 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
1771 break;
1772 case 1:
1773 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1774 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1775 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1776 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
1777 break;
1778 case 2:
1779 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1780 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1781 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1782 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
1783 break;
1784 case 3:
1785 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1786 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1787 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
1789 break;
1790 case 4:
1791 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1792 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1793 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1794 TILE_SPLIT(split_equal_to_row_size));
1795 break;
1796 case 5:
1797 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1798 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1799 break;
1800 case 6:
1801 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1802 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1803 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
1805 break;
1806 case 7:
1807 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1808 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1809 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1810 TILE_SPLIT(split_equal_to_row_size));
1811 break;
1812 case 8:
1813 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1814 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1815 break;
1816 case 9:
1817 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1818 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1819 break;
1820 case 10:
1821 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1822 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1823 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1824 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1825 break;
1826 case 11:
1827 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1828 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1829 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
1830 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1831 break;
1832 case 12:
1833 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1834 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1835 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1836 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1837 break;
1838 case 13:
1839 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1840 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1841 break;
1842 case 14:
1843 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1844 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1845 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1846 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1847 break;
1848 case 16:
1849 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1850 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1851 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
1852 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1853 break;
1854 case 17:
1855 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1856 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1857 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1858 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1859 break;
1860 case 27:
1861 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1862 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1863 break;
1864 case 28:
1865 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1866 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1867 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1868 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1869 break;
1870 case 29:
1871 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1872 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1873 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
1874 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1875 break;
1876 case 30:
1877 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1878 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1879 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1880 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1881 break;
1882 default:
1883 gb_tile_moden = 0;
1884 break;
1885 }
1886 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
1887 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1888 }
1889 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1890 switch (reg_offset) {
1891 case 0:
1892 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1893 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1894 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1895 NUM_BANKS(ADDR_SURF_16_BANK));
1896 break;
1897 case 1:
1898 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1899 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1900 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1901 NUM_BANKS(ADDR_SURF_16_BANK));
1902 break;
1903 case 2:
1904 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1905 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1906 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1907 NUM_BANKS(ADDR_SURF_16_BANK));
1908 break;
1909 case 3:
1910 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1913 NUM_BANKS(ADDR_SURF_16_BANK));
1914 break;
1915 case 4:
1916 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1917 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1918 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1919 NUM_BANKS(ADDR_SURF_8_BANK));
1920 break;
1921 case 5:
1922 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1925 NUM_BANKS(ADDR_SURF_4_BANK));
1926 break;
1927 case 6:
1928 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1931 NUM_BANKS(ADDR_SURF_2_BANK));
1932 break;
1933 case 8:
1934 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1935 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1936 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1937 NUM_BANKS(ADDR_SURF_16_BANK));
1938 break;
1939 case 9:
1940 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1941 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1942 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1943 NUM_BANKS(ADDR_SURF_16_BANK));
1944 break;
1945 case 10:
1946 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1947 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1948 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1949 NUM_BANKS(ADDR_SURF_16_BANK));
1950 break;
1951 case 11:
1952 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1953 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1954 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1955 NUM_BANKS(ADDR_SURF_8_BANK));
1956 break;
1957 case 12:
1958 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1959 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1960 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1961 NUM_BANKS(ADDR_SURF_4_BANK));
1962 break;
1963 case 13:
1964 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1967 NUM_BANKS(ADDR_SURF_2_BANK));
1968 break;
1969 case 14:
1970 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1973 NUM_BANKS(ADDR_SURF_2_BANK));
1974 break;
1975 default:
1976 gb_tile_moden = 0;
1977 break;
1978 }
1979 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1980 }
1981 } else if (num_pipe_configs == 8) {
1764 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1982 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1765 switch (reg_offset) { 1983 switch (reg_offset) {
1766 case 0: 1984 case 0:
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 28cbcc1baa07..8eea4f2cc92c 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -1164,6 +1164,8 @@
1164# define ADDR_SURF_P8_32x32_16x16 12 1164# define ADDR_SURF_P8_32x32_16x16 12
1165# define ADDR_SURF_P8_32x32_16x32 13 1165# define ADDR_SURF_P8_32x32_16x32 13
1166# define ADDR_SURF_P8_32x64_32x32 14 1166# define ADDR_SURF_P8_32x64_32x32 14
1167# define ADDR_SURF_P16_32x32_8x16 16
1168# define ADDR_SURF_P16_32x32_16x16 17
1167# define TILE_SPLIT(x) ((x) << 11) 1169# define TILE_SPLIT(x) ((x) << 11)
1168# define ADDR_SURF_TILE_SPLIT_64B 0 1170# define ADDR_SURF_TILE_SPLIT_64B 0
1169# define ADDR_SURF_TILE_SPLIT_128B 1 1171# define ADDR_SURF_TILE_SPLIT_128B 1
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 00:55:20 -0400