diff options
author | Al Viro <viro@ftp.linux.org.uk> | 2008-01-13 09:17:55 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2008-01-18 14:44:33 -0500 |
commit | 21b645e4c2531631992dc127cf676631a70046c8 (patch) | |
tree | 3afd7065134ccef5312e45010fd2afe4359ab8f5 | |
parent | d50956af74859b4e9ba544a0211a94bc2621c1d9 (diff) |
dl2k: ANAR, ANLPAR fixes
same story, different registers...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r-- | drivers/net/dl2k.c | 74 | ||||
-rw-r--r-- | drivers/net/dl2k.h | 66 |
2 files changed, 42 insertions, 98 deletions
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c index badc60103d34..afeea88a520a 100644 --- a/drivers/net/dl2k.c +++ b/drivers/net/dl2k.c | |||
@@ -1453,7 +1453,7 @@ mii_wait_link (struct net_device *dev, int wait) | |||
1453 | static int | 1453 | static int |
1454 | mii_get_media (struct net_device *dev) | 1454 | mii_get_media (struct net_device *dev) |
1455 | { | 1455 | { |
1456 | ANAR_t negotiate; | 1456 | __u16 negotiate; |
1457 | BMSR_t bmsr; | 1457 | BMSR_t bmsr; |
1458 | MSCR_t mscr; | 1458 | MSCR_t mscr; |
1459 | MSSR_t mssr; | 1459 | MSSR_t mssr; |
@@ -1469,7 +1469,7 @@ mii_get_media (struct net_device *dev) | |||
1469 | /* Auto-Negotiation not completed */ | 1469 | /* Auto-Negotiation not completed */ |
1470 | return -1; | 1470 | return -1; |
1471 | } | 1471 | } |
1472 | negotiate.image = mii_read (dev, phy_addr, MII_ANAR) & | 1472 | negotiate = mii_read (dev, phy_addr, MII_ANAR) & |
1473 | mii_read (dev, phy_addr, MII_ANLPAR); | 1473 | mii_read (dev, phy_addr, MII_ANLPAR); |
1474 | mscr.image = mii_read (dev, phy_addr, MII_MSCR); | 1474 | mscr.image = mii_read (dev, phy_addr, MII_MSCR); |
1475 | mssr.image = mii_read (dev, phy_addr, MII_MSSR); | 1475 | mssr.image = mii_read (dev, phy_addr, MII_MSSR); |
@@ -1481,27 +1481,27 @@ mii_get_media (struct net_device *dev) | |||
1481 | np->speed = 1000; | 1481 | np->speed = 1000; |
1482 | np->full_duplex = 0; | 1482 | np->full_duplex = 0; |
1483 | printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); | 1483 | printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); |
1484 | } else if (negotiate.bits.media_100BX_FD) { | 1484 | } else if (negotiate & MII_ANAR_100BX_FD) { |
1485 | np->speed = 100; | 1485 | np->speed = 100; |
1486 | np->full_duplex = 1; | 1486 | np->full_duplex = 1; |
1487 | printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); | 1487 | printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); |
1488 | } else if (negotiate.bits.media_100BX_HD) { | 1488 | } else if (negotiate & MII_ANAR_100BX_HD) { |
1489 | np->speed = 100; | 1489 | np->speed = 100; |
1490 | np->full_duplex = 0; | 1490 | np->full_duplex = 0; |
1491 | printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); | 1491 | printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); |
1492 | } else if (negotiate.bits.media_10BT_FD) { | 1492 | } else if (negotiate & MII_ANAR_10BT_FD) { |
1493 | np->speed = 10; | 1493 | np->speed = 10; |
1494 | np->full_duplex = 1; | 1494 | np->full_duplex = 1; |
1495 | printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); | 1495 | printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); |
1496 | } else if (negotiate.bits.media_10BT_HD) { | 1496 | } else if (negotiate & MII_ANAR_10BT_HD) { |
1497 | np->speed = 10; | 1497 | np->speed = 10; |
1498 | np->full_duplex = 0; | 1498 | np->full_duplex = 0; |
1499 | printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); | 1499 | printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); |
1500 | } | 1500 | } |
1501 | if (negotiate.bits.pause) { | 1501 | if (negotiate & MII_ANAR_PAUSE) { |
1502 | np->tx_flow &= 1; | 1502 | np->tx_flow &= 1; |
1503 | np->rx_flow &= 1; | 1503 | np->rx_flow &= 1; |
1504 | } else if (negotiate.bits.asymmetric) { | 1504 | } else if (negotiate & MII_ANAR_ASYMMETRIC) { |
1505 | np->tx_flow = 0; | 1505 | np->tx_flow = 0; |
1506 | np->rx_flow &= 1; | 1506 | np->rx_flow &= 1; |
1507 | } | 1507 | } |
@@ -1542,7 +1542,7 @@ mii_set_media (struct net_device *dev) | |||
1542 | PHY_SCR_t pscr; | 1542 | PHY_SCR_t pscr; |
1543 | __u16 bmcr; | 1543 | __u16 bmcr; |
1544 | BMSR_t bmsr; | 1544 | BMSR_t bmsr; |
1545 | ANAR_t anar; | 1545 | __u16 anar; |
1546 | int phy_addr; | 1546 | int phy_addr; |
1547 | struct netdev_private *np; | 1547 | struct netdev_private *np; |
1548 | np = netdev_priv(dev); | 1548 | np = netdev_priv(dev); |
@@ -1552,15 +1552,24 @@ mii_set_media (struct net_device *dev) | |||
1552 | if (np->an_enable) { | 1552 | if (np->an_enable) { |
1553 | /* Advertise capabilities */ | 1553 | /* Advertise capabilities */ |
1554 | bmsr.image = mii_read (dev, phy_addr, MII_BMSR); | 1554 | bmsr.image = mii_read (dev, phy_addr, MII_BMSR); |
1555 | anar.image = mii_read (dev, phy_addr, MII_ANAR); | 1555 | anar = mii_read (dev, phy_addr, MII_ANAR) & |
1556 | anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD; | 1556 | ~MII_ANAR_100BX_FD & |
1557 | anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD; | 1557 | ~MII_ANAR_100BX_HD & |
1558 | anar.bits.media_100BT4 = bmsr.bits.media_100BT4; | 1558 | ~MII_ANAR_100BT4 & |
1559 | anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD; | 1559 | ~MII_ANAR_10BT_FD & |
1560 | anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD; | 1560 | ~MII_ANAR_10BT_HD; |
1561 | anar.bits.pause = 1; | 1561 | if (bmsr.bits.media_100BX_FD) |
1562 | anar.bits.asymmetric = 1; | 1562 | anar |= MII_ANAR_100BX_FD; |
1563 | mii_write (dev, phy_addr, MII_ANAR, anar.image); | 1563 | if (bmsr.bits.media_100BX_HD) |
1564 | anar |= MII_ANAR_100BX_HD; | ||
1565 | if (bmsr.bits.media_100BT4) | ||
1566 | anar |= MII_ANAR_100BT4; | ||
1567 | if (bmsr.bits.media_10BT_FD) | ||
1568 | anar |= MII_ANAR_10BT_FD; | ||
1569 | if (bmsr.bits.media_10BT_HD) | ||
1570 | anar |= MII_ANAR_10BT_HD; | ||
1571 | anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC; | ||
1572 | mii_write (dev, phy_addr, MII_ANAR, anar); | ||
1564 | 1573 | ||
1565 | /* Enable Auto crossover */ | 1574 | /* Enable Auto crossover */ |
1566 | pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR); | 1575 | pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR); |
@@ -1621,7 +1630,7 @@ mii_set_media (struct net_device *dev) | |||
1621 | static int | 1630 | static int |
1622 | mii_get_media_pcs (struct net_device *dev) | 1631 | mii_get_media_pcs (struct net_device *dev) |
1623 | { | 1632 | { |
1624 | ANAR_PCS_t negotiate; | 1633 | __u16 negotiate; |
1625 | BMSR_t bmsr; | 1634 | BMSR_t bmsr; |
1626 | int phy_addr; | 1635 | int phy_addr; |
1627 | struct netdev_private *np; | 1636 | struct netdev_private *np; |
@@ -1635,20 +1644,20 @@ mii_get_media_pcs (struct net_device *dev) | |||
1635 | /* Auto-Negotiation not completed */ | 1644 | /* Auto-Negotiation not completed */ |
1636 | return -1; | 1645 | return -1; |
1637 | } | 1646 | } |
1638 | negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) & | 1647 | negotiate = mii_read (dev, phy_addr, PCS_ANAR) & |
1639 | mii_read (dev, phy_addr, PCS_ANLPAR); | 1648 | mii_read (dev, phy_addr, PCS_ANLPAR); |
1640 | np->speed = 1000; | 1649 | np->speed = 1000; |
1641 | if (negotiate.bits.full_duplex) { | 1650 | if (negotiate & PCS_ANAR_FULL_DUPLEX) { |
1642 | printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); | 1651 | printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); |
1643 | np->full_duplex = 1; | 1652 | np->full_duplex = 1; |
1644 | } else { | 1653 | } else { |
1645 | printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); | 1654 | printk (KERN_INFO "Auto 1000 Mbps, half duplex\n"); |
1646 | np->full_duplex = 0; | 1655 | np->full_duplex = 0; |
1647 | } | 1656 | } |
1648 | if (negotiate.bits.pause) { | 1657 | if (negotiate & PCS_ANAR_PAUSE) { |
1649 | np->tx_flow &= 1; | 1658 | np->tx_flow &= 1; |
1650 | np->rx_flow &= 1; | 1659 | np->rx_flow &= 1; |
1651 | } else if (negotiate.bits.asymmetric) { | 1660 | } else if (negotiate & PCS_ANAR_ASYMMETRIC) { |
1652 | np->tx_flow = 0; | 1661 | np->tx_flow = 0; |
1653 | np->rx_flow &= 1; | 1662 | np->rx_flow &= 1; |
1654 | } | 1663 | } |
@@ -1679,7 +1688,7 @@ mii_set_media_pcs (struct net_device *dev) | |||
1679 | { | 1688 | { |
1680 | __u16 bmcr; | 1689 | __u16 bmcr; |
1681 | ESR_t esr; | 1690 | ESR_t esr; |
1682 | ANAR_PCS_t anar; | 1691 | __u16 anar; |
1683 | int phy_addr; | 1692 | int phy_addr; |
1684 | struct netdev_private *np; | 1693 | struct netdev_private *np; |
1685 | np = netdev_priv(dev); | 1694 | np = netdev_priv(dev); |
@@ -1689,14 +1698,15 @@ mii_set_media_pcs (struct net_device *dev) | |||
1689 | if (np->an_enable) { | 1698 | if (np->an_enable) { |
1690 | /* Advertise capabilities */ | 1699 | /* Advertise capabilities */ |
1691 | esr.image = mii_read (dev, phy_addr, PCS_ESR); | 1700 | esr.image = mii_read (dev, phy_addr, PCS_ESR); |
1692 | anar.image = mii_read (dev, phy_addr, MII_ANAR); | 1701 | anar = mii_read (dev, phy_addr, MII_ANAR) & |
1693 | anar.bits.half_duplex = | 1702 | ~PCS_ANAR_HALF_DUPLEX & |
1694 | esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD; | 1703 | ~PCS_ANAR_FULL_DUPLEX; |
1695 | anar.bits.full_duplex = | 1704 | if (esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD) |
1696 | esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD; | 1705 | anar |= PCS_ANAR_HALF_DUPLEX; |
1697 | anar.bits.pause = 1; | 1706 | if (esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD) |
1698 | anar.bits.asymmetric = 1; | 1707 | anar |= PCS_ANAR_FULL_DUPLEX; |
1699 | mii_write (dev, phy_addr, MII_ANAR, anar.image); | 1708 | anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; |
1709 | mii_write (dev, phy_addr, MII_ANAR, anar); | ||
1700 | 1710 | ||
1701 | /* Soft reset PHY */ | 1711 | /* Soft reset PHY */ |
1702 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); | 1712 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); |
diff --git a/drivers/net/dl2k.h b/drivers/net/dl2k.h index 931fd0e58f3c..e6623085e834 100644 --- a/drivers/net/dl2k.h +++ b/drivers/net/dl2k.h | |||
@@ -357,24 +357,6 @@ enum _mii_bmsr { | |||
357 | }; | 357 | }; |
358 | 358 | ||
359 | /* ANAR */ | 359 | /* ANAR */ |
360 | typedef union t_MII_ANAR { | ||
361 | u16 image; | ||
362 | struct { | ||
363 | u16 selector:5; // bit 4:0 | ||
364 | u16 media_10BT_HD:1; // bit 5 | ||
365 | u16 media_10BT_FD:1; // bit 6 | ||
366 | u16 media_100BX_HD:1; // bit 7 | ||
367 | u16 media_100BX_FD:1; // bit 8 | ||
368 | u16 media_100BT4:1; // bit 9 | ||
369 | u16 pause:1; // bit 10 | ||
370 | u16 asymmetric:1; // bit 11 | ||
371 | u16 _bit12:1; // bit 12 | ||
372 | u16 remote_fault:1; // bit 13 | ||
373 | u16 _bit14:1; // bit 14 | ||
374 | u16 next_page:1; // bit 15 | ||
375 | } bits; | ||
376 | } ANAR_t, *PANAR_t; | ||
377 | |||
378 | enum _mii_anar { | 360 | enum _mii_anar { |
379 | MII_ANAR_NEXT_PAGE = 0x8000, | 361 | MII_ANAR_NEXT_PAGE = 0x8000, |
380 | MII_ANAR_REMOTE_FAULT = 0x4000, | 362 | MII_ANAR_REMOTE_FAULT = 0x4000, |
@@ -390,24 +372,6 @@ enum _mii_anar { | |||
390 | }; | 372 | }; |
391 | 373 | ||
392 | /* ANLPAR */ | 374 | /* ANLPAR */ |
393 | typedef union t_MII_ANLPAR { | ||
394 | u16 image; | ||
395 | struct { | ||
396 | u16 selector:5; // bit 4:0 | ||
397 | u16 media_10BT_HD:1; // bit 5 | ||
398 | u16 media_10BT_FD:1; // bit 6 | ||
399 | u16 media_100BX_HD:1; // bit 7 | ||
400 | u16 media_100BX_FD:1; // bit 8 | ||
401 | u16 media_100BT4:1; // bit 9 | ||
402 | u16 pause:1; // bit 10 | ||
403 | u16 asymmetric:1; // bit 11 | ||
404 | u16 _bit12:1; // bit 12 | ||
405 | u16 remote_fault:1; // bit 13 | ||
406 | u16 _bit14:1; // bit 14 | ||
407 | u16 next_page:1; // bit 15 | ||
408 | } bits; | ||
409 | } ANLPAR_t, *PANLPAR_t; | ||
410 | |||
411 | enum _mii_anlpar { | 375 | enum _mii_anlpar { |
412 | MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, | 376 | MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, |
413 | MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, | 377 | MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, |
@@ -539,21 +503,6 @@ typedef enum t_MII_ADMIN_STATUS { | |||
539 | /* PCS control and status registers bitmap as the same as MII */ | 503 | /* PCS control and status registers bitmap as the same as MII */ |
540 | /* PCS Extended Status register bitmap as the same as MII */ | 504 | /* PCS Extended Status register bitmap as the same as MII */ |
541 | /* PCS ANAR */ | 505 | /* PCS ANAR */ |
542 | typedef union t_PCS_ANAR { | ||
543 | u16 image; | ||
544 | struct { | ||
545 | u16 _bit_4_0:5; // bit 4:0 | ||
546 | u16 full_duplex:1; // bit 5 | ||
547 | u16 half_duplex:1; // bit 6 | ||
548 | u16 asymmetric:1; // bit 7 | ||
549 | u16 pause:1; // bit 8 | ||
550 | u16 _bit_11_9:3; // bit 11:9 | ||
551 | u16 remote_fault:2; // bit 13:12 | ||
552 | u16 _bit_14:1; // bit 14 | ||
553 | u16 next_page:1; // bit 15 | ||
554 | } bits; | ||
555 | } ANAR_PCS_t, *PANAR_PCS_t; | ||
556 | |||
557 | enum _pcs_anar { | 506 | enum _pcs_anar { |
558 | PCS_ANAR_NEXT_PAGE = 0x8000, | 507 | PCS_ANAR_NEXT_PAGE = 0x8000, |
559 | PCS_ANAR_REMOTE_FAULT = 0x3000, | 508 | PCS_ANAR_REMOTE_FAULT = 0x3000, |
@@ -563,21 +512,6 @@ enum _pcs_anar { | |||
563 | PCS_ANAR_FULL_DUPLEX = 0x0020, | 512 | PCS_ANAR_FULL_DUPLEX = 0x0020, |
564 | }; | 513 | }; |
565 | /* PCS ANLPAR */ | 514 | /* PCS ANLPAR */ |
566 | typedef union t_PCS_ANLPAR { | ||
567 | u16 image; | ||
568 | struct { | ||
569 | u16 _bit_4_0:5; // bit 4:0 | ||
570 | u16 full_duplex:1; // bit 5 | ||
571 | u16 half_duplex:1; // bit 6 | ||
572 | u16 asymmetric:1; // bit 7 | ||
573 | u16 pause:1; // bit 8 | ||
574 | u16 _bit_11_9:3; // bit 11:9 | ||
575 | u16 remote_fault:2; // bit 13:12 | ||
576 | u16 _bit_14:1; // bit 14 | ||
577 | u16 next_page:1; // bit 15 | ||
578 | } bits; | ||
579 | } ANLPAR_PCS_t, *PANLPAR_PCS_t; | ||
580 | |||
581 | enum _pcs_anlpar { | 515 | enum _pcs_anlpar { |
582 | PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, | 516 | PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE, |
583 | PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT, | 517 | PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT, |