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authorLinus Torvalds <torvalds@linux-foundation.org>2008-01-29 06:48:03 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-01-29 06:48:03 -0500
commit21af0297c7e56024a5ccc4d8ad2a590f9ec371ba (patch)
tree5d288c1877b1ae9fbe24aa7fabd79565e73d3d2f
parent5ea293a9048d3a58cb0c840fa719d85ad14cba47 (diff)
parenta9d2517c7a5c8028fbc5296d3af3c75597d3d180 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (68 commits) [MIPS] remove Documentation/mips/GT64120.README [MIPS] Malta: remaining bits of the board support code cleanup [MIPS] Malta: make the helper function static [MIPS] Malta: fix braces at single statement blocks [MIPS] Malta, Atlas: move an extern function declaration to the header file [MIPS] Malta: Use C89 style for comments [MIPS] Malta: else should follow close brace in malta_int.c [MIPS] Malta: remove a superfluous comment [MIPS] Malta: include <linux/cpu.h> instead of <asm/cpu.h> [MIPS] Malta, Atlas, Sead: remove an extern from .c files [MIPS] Malta: fix oversized lines in malta_int.c [MIPS] Malta: remove a dead function declaration [MIPS] Malta: use tabs not spaces [MIPS] Malta: set up the screen info in a separate function [MIPS] Malta: check the PCI clock frequency in a separate function [MIPS] Malta: use the KERN_ facility level in printk() [MIPS] Malta: use Linux kernel style for structure initialization [MIPS]: constify function pointer tables [MIPS] compat: handle argument endianess of sys32_(f)truncate64 with merge_64 [MIPS] Cobalt 64-bits kernels can be safely unmarked experimental ...
Diffstat
-rw-r--r--Documentation/mips/00-INDEX2
-rw-r--r--Documentation/mips/GT64120.README65
-rw-r--r--arch/mips/Kconfig181
-rw-r--r--arch/mips/Makefile40
-rw-r--r--arch/mips/au1000/common/au1xxx_irqmap.c21
-rw-r--r--arch/mips/au1000/common/dbdma.c2
-rw-r--r--arch/mips/au1000/db1x00/init.c11
-rw-r--r--arch/mips/au1000/mtx-1/init.c2
-rw-r--r--arch/mips/au1000/mtx-1/platform.c27
-rw-r--r--arch/mips/au1000/pb1000/init.c2
-rw-r--r--arch/mips/au1000/pb1100/init.c2
-rw-r--r--arch/mips/au1000/pb1200/init.c2
-rw-r--r--arch/mips/au1000/pb1500/init.c2
-rw-r--r--arch/mips/au1000/pb1550/init.c2
-rw-r--r--arch/mips/au1000/xxs1500/init.c2
-rw-r--r--arch/mips/basler/excite/Kconfig9
-rw-r--r--arch/mips/basler/excite/excite_iodev.c2
-rw-r--r--arch/mips/basler/excite/excite_prom.c2
-rw-r--r--arch/mips/cobalt/reset.c24
-rw-r--r--arch/mips/configs/atlas_defconfig2
-rw-r--r--arch/mips/configs/bigsur_defconfig2
-rw-r--r--arch/mips/configs/capcella_defconfig2
-rw-r--r--arch/mips/configs/cobalt_defconfig2
-rw-r--r--arch/mips/configs/db1000_defconfig2
-rw-r--r--arch/mips/configs/db1100_defconfig2
-rw-r--r--arch/mips/configs/db1200_defconfig2
-rw-r--r--arch/mips/configs/db1500_defconfig2
-rw-r--r--arch/mips/configs/db1550_defconfig2
-rw-r--r--arch/mips/configs/decstation_defconfig2
-rw-r--r--arch/mips/configs/e55_defconfig2
-rw-r--r--arch/mips/configs/emma2rh_defconfig2
-rw-r--r--arch/mips/configs/excite_defconfig2
-rw-r--r--arch/mips/configs/fulong_defconfig2
-rw-r--r--arch/mips/configs/ip22_defconfig2
-rw-r--r--arch/mips/configs/ip27_defconfig2
-rw-r--r--arch/mips/configs/ip32_defconfig2
-rw-r--r--arch/mips/configs/jazz_defconfig2
-rw-r--r--arch/mips/configs/jmr3927_defconfig17
-rw-r--r--arch/mips/configs/lasat_defconfig2
-rw-r--r--arch/mips/configs/malta_defconfig2
-rw-r--r--arch/mips/configs/mipssim_defconfig2
-rw-r--r--arch/mips/configs/mpc30x_defconfig2
-rw-r--r--arch/mips/configs/msp71xx_defconfig2
-rw-r--r--arch/mips/configs/mtx1_defconfig3
-rw-r--r--arch/mips/configs/pb1100_defconfig2
-rw-r--r--arch/mips/configs/pb1500_defconfig2
-rw-r--r--arch/mips/configs/pb1550_defconfig2
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig2
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig2
-rw-r--r--arch/mips/configs/qemu_defconfig2
-rw-r--r--arch/mips/configs/rbhma4200_defconfig17
-rw-r--r--arch/mips/configs/rbhma4500_defconfig17
-rw-r--r--arch/mips/configs/rm200_defconfig2
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig2
-rw-r--r--arch/mips/configs/sead_defconfig2
-rw-r--r--arch/mips/configs/tb0219_defconfig2
-rw-r--r--arch/mips/configs/tb0226_defconfig2
-rw-r--r--arch/mips/configs/tb0287_defconfig2
-rw-r--r--arch/mips/configs/workpad_defconfig2
-rw-r--r--arch/mips/configs/wrppmc_defconfig2
-rw-r--r--arch/mips/configs/yosemite_defconfig2
-rw-r--r--arch/mips/dec/time.c1
-rw-r--r--arch/mips/defconfig2
-rw-r--r--arch/mips/fw/arc/cmdline.c2
-rw-r--r--arch/mips/fw/arc/init.c8
-rw-r--r--arch/mips/fw/cfe/cfe_api.c184
-rw-r--r--arch/mips/fw/cfe/cfe_api_int.h186
-rw-r--r--arch/mips/fw/lib/Makefile5
-rw-r--r--arch/mips/fw/lib/call_o32.S97
-rw-r--r--arch/mips/fw/sni/Makefile5
-rw-r--r--arch/mips/fw/sni/sniprom.c151
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c2
-rw-r--r--arch/mips/jazz/setup.c7
-rw-r--r--arch/mips/jmr3927/rbhma3100/init.c4
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c60
-rw-r--r--arch/mips/kernel/cpu-bugs64.c47
-rw-r--r--arch/mips/kernel/cpu-probe.c9
-rw-r--r--arch/mips/kernel/genex.S8
-rw-r--r--arch/mips/kernel/kspd.c3
-rw-r--r--arch/mips/kernel/linux32.c30
-rw-r--r--arch/mips/kernel/mips-mt.c1
-rw-r--r--arch/mips/kernel/pcspeaker.c28
-rw-r--r--arch/mips/kernel/proc.c3
-rw-r--r--arch/mips/kernel/rtlx.c1
-rw-r--r--arch/mips/kernel/setup.c7
-rw-r--r--arch/mips/kernel/smp-mt.c193
-rw-r--r--arch/mips/kernel/smp.c53
-rw-r--r--arch/mips/kernel/smtc-proc.c1
-rw-r--r--arch/mips/kernel/smtc.c1
-rw-r--r--arch/mips/kernel/time.c2
-rw-r--r--arch/mips/kernel/vpe.c1
-rw-r--r--arch/mips/lasat/picvue.c2
-rw-r--r--arch/mips/lasat/picvue.h3
-rw-r--r--arch/mips/lasat/picvue_proc.c18
-rw-r--r--arch/mips/lemote/lm2e/pci.c3
-rw-r--r--arch/mips/lemote/lm2e/prom.c2
-rw-r--r--arch/mips/lib/csum_partial.S275
-rw-r--r--arch/mips/lib/memcpy-inatomic.S141
-rw-r--r--arch/mips/lib/memcpy.S250
-rw-r--r--arch/mips/lib/memset.S44
-rw-r--r--arch/mips/lib/strlen_user.S6
-rw-r--r--arch/mips/lib/strncpy_user.S15
-rw-r--r--arch/mips/lib/strnlen_user.S7
-rw-r--r--arch/mips/lib/uncached.c12
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c6
-rw-r--r--arch/mips/mips-boards/generic/init.c8
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c129
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c210
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c68
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c2
-rw-r--r--arch/mips/mipssim/Makefile2
-rw-r--r--arch/mips/mipssim/sim_setup.c16
-rw-r--r--arch/mips/mipssim/sim_smtc.c (renamed from arch/mips/mipssim/sim_smp.c)92
-rw-r--r--arch/mips/mm/c-r4k.c17
-rw-r--r--arch/mips/mm/dma-default.c2
-rw-r--r--arch/mips/mm/pg-r4k.c66
-rw-r--r--arch/mips/mm/tlbex.c252
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c2
-rw-r--r--arch/mips/pci/pci-bcm1480.c4
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c4
-rw-r--r--arch/mips/philips/pnx8550/common/setup.c2
-rw-r--r--arch/mips/philips/pnx8550/common/time.c35
-rw-r--r--arch/mips/philips/pnx8550/jbs/init.c3
-rw-r--r--arch/mips/philips/pnx8550/stb810/prom_init.c2
-rw-r--r--arch/mips/pmc-sierra/yosemite/i2c-yosemite.h96
-rw-r--r--arch/mips/pmc-sierra/yosemite/prom.c7
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c149
-rw-r--r--arch/mips/qemu/Makefile10
-rw-r--r--arch/mips/qemu/q-console.c26
-rw-r--r--arch/mips/qemu/q-firmware.c24
-rw-r--r--arch/mips/qemu/q-irq.c37
-rw-r--r--arch/mips/qemu/q-mem.c5
-rw-r--r--arch/mips/qemu/q-reset.c33
-rw-r--r--arch/mips/qemu/q-setup.c22
-rw-r--r--arch/mips/qemu/q-smp.c55
-rw-r--r--arch/mips/sgi-ip22/Makefile8
-rw-r--r--arch/mips/sgi-ip22/ip22-mc.c4
-rw-r--r--arch/mips/sgi-ip22/ip28-berr.c502
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c1
-rw-r--r--arch/mips/sgi-ip27/ip27-klnuma.c1
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c109
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c101
-rw-r--r--arch/mips/sibyte/cfe/Makefile1
-rw-r--r--arch/mips/sibyte/cfe/setup.c14
-rw-r--r--arch/mips/sibyte/cfe/smp.c110
-rw-r--r--arch/mips/sibyte/sb1250/smp.c100
-rw-r--r--arch/mips/sni/Makefile2
-rw-r--r--arch/mips/sni/a20r.c13
-rw-r--r--arch/mips/sni/eisa.c50
-rw-r--r--arch/mips/sni/irq.c4
-rw-r--r--arch/mips/sni/pcit.c7
-rw-r--r--arch/mips/sni/rm200.c326
-rw-r--r--arch/mips/sni/setup.c143
-rw-r--r--arch/mips/sni/sniprom.c251
-rw-r--r--arch/mips/sni/time.c1
-rw-r--r--arch/mips/tx4927/common/Makefile2
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c186
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c96
-rw-r--r--arch/mips/tx4938/common/Makefile2
-rw-r--r--arch/mips/tx4938/common/setup.c45
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/prom.c1
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c31
-rw-r--r--arch/mips/vr41xx/common/init.c4
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/setup.c4
-rw-r--r--include/asm-mips/addrspace.h2
-rw-r--r--include/asm-mips/asm.h8
-rw-r--r--include/asm-mips/bootinfo.h105
-rw-r--r--include/asm-mips/bugs.h25
-rw-r--r--include/asm-mips/cpu-info.h5
-rw-r--r--include/asm-mips/cpu.h4
-rw-r--r--include/asm-mips/delay.h23
-rw-r--r--include/asm-mips/dma.h7
-rw-r--r--include/asm-mips/fixmap.h10
-rw-r--r--include/asm-mips/fw/cfe/cfe_api.h87
-rw-r--r--include/asm-mips/fw/cfe/cfe_error.h19
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h15
-rw-r--r--include/asm-mips/mach-ip28/cpu-feature-overrides.h50
-rw-r--r--include/asm-mips/mach-ip28/ds1286.h4
-rw-r--r--include/asm-mips/mach-ip28/spaces.h22
-rw-r--r--include/asm-mips/mach-ip28/war.h (renamed from include/asm-mips/mach-qemu/war.h)8
-rw-r--r--include/asm-mips/mach-qemu/cpu-feature-overrides.h32
-rw-r--r--include/asm-mips/mips-boards/generic.h6
-rw-r--r--include/asm-mips/mipsprom.h2
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/msp_regs.h4
-rw-r--r--include/asm-mips/r4kcache.h7
-rw-r--r--include/asm-mips/sgi/ioc.h4
-rw-r--r--include/asm-mips/sibyte/board.h6
-rw-r--r--include/asm-mips/sibyte/sb1250.h2
-rw-r--r--include/asm-mips/sibyte/swarm.h18
-rw-r--r--include/asm-mips/smp-ops.h56
-rw-r--r--include/asm-mips/smp.h64
-rw-r--r--include/asm-mips/sni.h159
-rw-r--r--include/asm-mips/stackframe.h9
-rw-r--r--include/asm-mips/time.h9
-rw-r--r--include/asm-mips/topology.h16
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h1
-rw-r--r--include/asm-mips/uaccess.h13
-rw-r--r--include/asm-mips/war.h62
198 files changed, 3732 insertions, 3047 deletions
diff --git a/Documentation/mips/00-INDEX b/Documentation/mips/00-INDEX
index 3f13bf8043d2..8ae9cffc2262 100644
--- a/Documentation/mips/00-INDEX
+++ b/Documentation/mips/00-INDEX
@@ -2,5 +2,3 @@
2 - this file. 2 - this file.
3AU1xxx_IDE.README 3AU1xxx_IDE.README
4 - README for MIPS AU1XXX IDE driver. 4 - README for MIPS AU1XXX IDE driver.
5GT64120.README
6 - README for dir with info on MIPS boards using GT-64120 or GT-64120A.
diff --git a/Documentation/mips/GT64120.README b/Documentation/mips/GT64120.README
deleted file mode 100644
index 2d0eec91dc59..000000000000
--- a/Documentation/mips/GT64120.README
+++ /dev/null
@@ -1,65 +0,0 @@
1README for arch/mips/gt64120 directory and subdirectories
2
3Jun Sun, jsun@mvista.com or jsun@junsun.net
401/27, 2001
5
6MOTIVATION
7----------
8
9Many MIPS boards share the same system controller (or CPU companian chip),
10such as GT-64120. It is highly desirable to let these boards share
11the same controller code instead of duplicating them.
12
13This directory is meant to hold all MIPS boards that use GT-64120 or GT-64120A.
14
15
16HOW TO ADD A BOARD
17------------------
18
19. Create a subdirectory include/asm/gt64120/<board>.
20
21. Create a file called gt64120_dep.h under that directory.
22
23. Modify include/asm/gt64120/gt64120.h file to include the new gt64120_dep.h
24 based on config options. The board-dep section is at the end of
25 include/asm/gt64120/gt64120.h file. There you can find all required
26 definitions include/asm/gt64120/<board>/gt64120_dep.h file must supply.
27
28. Create a subdirectory arch/mips/gt64120/<board> directory to hold
29 board specific routines.
30
31. The GT-64120 common code is supplied under arch/mips/gt64120/common directory.
32 It includes:
33 1) arch/mips/gt64120/pci.c -
34 common PCI routine, include the top-level pcibios_init()
35 2) arch/mips/gt64120/irq.c -
36 common IRQ routine, include the top-level do_IRQ()
37 [This part really belongs to arch/mips/kernel. jsun]
38 3) arch/mips/gt64120/gt_irq.c -
39 common IRQ routines for GT-64120 chip. Currently it only handles
40 the timer interrupt.
41
42. Board-specific routines are supplied under arch/mips/gt64120/<board> dir.
43 1) arch/mips/gt64120/<board>/pci.c - it provides bus fixup routine
44 2) arch/mips/gt64120/<board>/irq.c - it provides enable/disable irqs
45 and board irq setup routine (irq_setup)
46 3) arch/mips/gt64120/<board>/int-handler.S -
47 The first-level interrupt dispatching routine.
48 4) a bunch of other "normal" stuff (setup, prom, dbg_io, reset, etc)
49
50. Follow other "normal" procedure to modify configuration files, etc.
51
52
53TO-DO LIST
54----------
55
56. Expand arch/mips/gt64120/gt_irq.c to handle all GT-64120 interrupts.
57 We probably need to introduce GT_IRQ_BASE in board-dep header file,
58 which is used the starting irq_nr for all GT irqs.
59
60 A function, gt64120_handle_irq(), will be added so that the first-level
61 irq dispatcher will call this function if it detects an interrupt
62 from GT-64120.
63
64. More support for GT-64120 PCI features (2nd PCI bus, perhaps)
65
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b22c043b6ef8..6b0f85f02c79 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -37,16 +37,6 @@ config BASLER_EXCITE
37 The eXcite is a smart camera platform manufactured by 37 The eXcite is a smart camera platform manufactured by
38 Basler Vision Technologies AG. 38 Basler Vision Technologies AG.
39 39
40config BASLER_EXCITE_PROTOTYPE
41 bool "Support for pre-release units"
42 depends on BASLER_EXCITE
43 default n
44 help
45 Pre-series (prototype) units are different from later ones in
46 some ways. Select this option if you have one of these. Please
47 note that a kernel built with this option selected will not be
48 able to run on normal units.
49
50config BCM47XX 40config BCM47XX
51 bool "BCM47XX based boards" 41 bool "BCM47XX based boards"
52 select CEVT_R4K 42 select CEVT_R4K
@@ -82,7 +72,7 @@ config MIPS_COBALT
82 select SYS_HAS_CPU_NEVADA 72 select SYS_HAS_CPU_NEVADA
83 select SYS_HAS_EARLY_PRINTK 73 select SYS_HAS_EARLY_PRINTK
84 select SYS_SUPPORTS_32BIT_KERNEL 74 select SYS_SUPPORTS_32BIT_KERNEL
85 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 75 select SYS_SUPPORTS_64BIT_KERNEL
86 select SYS_SUPPORTS_LITTLE_ENDIAN 76 select SYS_SUPPORTS_LITTLE_ENDIAN
87 select GENERIC_HARDIRQS_NO__DO_IRQ 77 select GENERIC_HARDIRQS_NO__DO_IRQ
88 78
@@ -91,6 +81,9 @@ config MACH_DECSTATION
91 select BOOT_ELF32 81 select BOOT_ELF32
92 select CEVT_R4K 82 select CEVT_R4K
93 select CSRC_R4K 83 select CSRC_R4K
84 select CPU_DADDI_WORKAROUNDS if 64BIT
85 select CPU_R4000_WORKAROUNDS if 64BIT
86 select CPU_R4400_WORKAROUNDS if 64BIT
94 select DMA_NONCOHERENT 87 select DMA_NONCOHERENT
95 select NO_IOPORT 88 select NO_IOPORT
96 select IRQ_CPU 89 select IRQ_CPU
@@ -124,12 +117,12 @@ config MACH_JAZZ
124 select ARCH_MAY_HAVE_PC_FDC 117 select ARCH_MAY_HAVE_PC_FDC
125 select CEVT_R4K 118 select CEVT_R4K
126 select CSRC_R4K 119 select CSRC_R4K
120 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
127 select GENERIC_ISA_DMA 121 select GENERIC_ISA_DMA
128 select IRQ_CPU 122 select IRQ_CPU
129 select I8253 123 select I8253
130 select I8259 124 select I8259
131 select ISA 125 select ISA
132 select PCSPEAKER
133 select SYS_HAS_CPU_R4X00 126 select SYS_HAS_CPU_R4X00
134 select SYS_SUPPORTS_32BIT_KERNEL 127 select SYS_SUPPORTS_32BIT_KERNEL
135 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 128 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
@@ -187,6 +180,7 @@ config LEMOTE_FULONG
187config MIPS_ATLAS 180config MIPS_ATLAS
188 bool "MIPS Atlas board" 181 bool "MIPS Atlas board"
189 select BOOT_ELF32 182 select BOOT_ELF32
183 select BOOT_RAW
190 select CEVT_R4K 184 select CEVT_R4K
191 select CSRC_R4K 185 select CSRC_R4K
192 select DMA_NONCOHERENT 186 select DMA_NONCOHERENT
@@ -219,6 +213,7 @@ config MIPS_MALTA
219 bool "MIPS Malta board" 213 bool "MIPS Malta board"
220 select ARCH_MAY_HAVE_PC_FDC 214 select ARCH_MAY_HAVE_PC_FDC
221 select BOOT_ELF32 215 select BOOT_ELF32
216 select BOOT_RAW
222 select CEVT_R4K 217 select CEVT_R4K
223 select CSRC_R4K 218 select CSRC_R4K
224 select DMA_NONCOHERENT 219 select DMA_NONCOHERENT
@@ -364,35 +359,6 @@ config PMC_YOSEMITE
364 Yosemite is an evaluation board for the RM9000x2 processor 359 Yosemite is an evaluation board for the RM9000x2 processor
365 manufactured by PMC-Sierra. 360 manufactured by PMC-Sierra.
366 361
367config QEMU
368 bool "Qemu"
369 select CEVT_R4K
370 select CSRC_R4K
371 select DMA_COHERENT
372 select GENERIC_ISA_DMA
373 select HAVE_STD_PC_SERIAL_PORT
374 select I8253
375 select I8259
376 select IRQ_CPU
377 select ISA
378 select PCSPEAKER
379 select SWAP_IO_SPACE
380 select SYS_HAS_CPU_MIPS32_R1
381 select SYS_HAS_EARLY_PRINTK
382 select SYS_SUPPORTS_32BIT_KERNEL
383 select SYS_SUPPORTS_BIG_ENDIAN
384 select SYS_SUPPORTS_LITTLE_ENDIAN
385 select GENERIC_HARDIRQS_NO__DO_IRQ
386 select NR_CPUS_DEFAULT_1
387 select SYS_SUPPORTS_SMP
388 help
389 Qemu is a software emulator which among other architectures also
390 can simulate a MIPS32 4Kc system. This patch adds support for the
391 system architecture that currently is being simulated by Qemu. It
392 will eventually be removed again when Qemu has the capability to
393 simulate actual MIPS hardware platforms. More information on Qemu
394 can be found at http://www.linux-mips.org/wiki/Qemu.
395
396config SGI_IP22 362config SGI_IP22
397 bool "SGI IP22 (Indy/Indigo2)" 363 bool "SGI IP22 (Indy/Indigo2)"
398 select ARC 364 select ARC
@@ -400,6 +366,7 @@ config SGI_IP22
400 select BOOT_ELF32 366 select BOOT_ELF32
401 select CEVT_R4K 367 select CEVT_R4K
402 select CSRC_R4K 368 select CSRC_R4K
369 select DEFAULT_SGI_PARTITION
403 select DMA_NONCOHERENT 370 select DMA_NONCOHERENT
404 select HW_HAS_EISA 371 select HW_HAS_EISA
405 select I8253 372 select I8253
@@ -407,6 +374,12 @@ config SGI_IP22
407 select IP22_CPU_SCACHE 374 select IP22_CPU_SCACHE
408 select IRQ_CPU 375 select IRQ_CPU
409 select GENERIC_ISA_DMA_SUPPORT_BROKEN 376 select GENERIC_ISA_DMA_SUPPORT_BROKEN
377 select SGI_HAS_DS1286
378 select SGI_HAS_I8042
379 select SGI_HAS_INDYDOG
380 select SGI_HAS_SEEQ
381 select SGI_HAS_WD93
382 select SGI_HAS_ZILOG
410 select SWAP_IO_SPACE 383 select SWAP_IO_SPACE
411 select SYS_HAS_CPU_R4X00 384 select SYS_HAS_CPU_R4X00
412 select SYS_HAS_CPU_R5000 385 select SYS_HAS_CPU_R5000
@@ -424,6 +397,7 @@ config SGI_IP27
424 select ARC 397 select ARC
425 select ARC64 398 select ARC64
426 select BOOT_ELF64 399 select BOOT_ELF64
400 select DEFAULT_SGI_PARTITION
427 select DMA_IP27 401 select DMA_IP27
428 select SYS_HAS_EARLY_PRINTK 402 select SYS_HAS_EARLY_PRINTK
429 select HW_HAS_PCI 403 select HW_HAS_PCI
@@ -440,6 +414,36 @@ config SGI_IP27
440 workstations. To compile a Linux kernel that runs on these, say Y 414 workstations. To compile a Linux kernel that runs on these, say Y
441 here. 415 here.
442 416
417config SGI_IP28
418 bool "SGI IP28 (Indigo2 R10k) (EXPERIMENTAL)"
419 depends on EXPERIMENTAL
420 select ARC
421 select ARC64
422 select BOOT_ELF64
423 select CEVT_R4K
424 select CSRC_R4K
425 select DEFAULT_SGI_PARTITION
426 select DMA_NONCOHERENT
427 select GENERIC_ISA_DMA_SUPPORT_BROKEN
428 select IRQ_CPU
429 select HW_HAS_EISA
430 select I8253
431 select I8259
432 select SGI_HAS_DS1286
433 select SGI_HAS_I8042
434 select SGI_HAS_INDYDOG
435 select SGI_HAS_SEEQ
436 select SGI_HAS_WD93
437 select SGI_HAS_ZILOG
438 select SWAP_IO_SPACE
439 select SYS_HAS_CPU_R10000
440 select SYS_HAS_EARLY_PRINTK
441 select SYS_SUPPORTS_64BIT_KERNEL
442 select SYS_SUPPORTS_BIG_ENDIAN
443 help
444 This is the SGI Indigo2 with R10000 processor. To compile a Linux
445 kernel that runs on these, say Y here.
446
443config SGI_IP32 447config SGI_IP32
444 bool "SGI IP32 (O2)" 448 bool "SGI IP32 (O2)"
445 select ARC 449 select ARC
@@ -545,19 +549,6 @@ config SIBYTE_SENTOSA
545 select SYS_SUPPORTS_BIG_ENDIAN 549 select SYS_SUPPORTS_BIG_ENDIAN
546 select SYS_SUPPORTS_LITTLE_ENDIAN 550 select SYS_SUPPORTS_LITTLE_ENDIAN
547 551
548config SIBYTE_PTSWARM
549 bool "Sibyte BCM91250PT-PTSWARM"
550 depends on EXPERIMENTAL
551 select BOOT_ELF32
552 select DMA_COHERENT
553 select NR_CPUS_DEFAULT_2
554 select SIBYTE_SB1250
555 select SWAP_IO_SPACE
556 select SYS_HAS_CPU_SB1
557 select SYS_SUPPORTS_BIG_ENDIAN
558 select SYS_SUPPORTS_HIGHMEM
559 select SYS_SUPPORTS_LITTLE_ENDIAN
560
561config SIBYTE_BIGSUR 552config SIBYTE_BIGSUR
562 bool "Sibyte BCM91480B-BigSur" 553 bool "Sibyte BCM91480B-BigSur"
563 select BOOT_ELF32 554 select BOOT_ELF32
@@ -575,10 +566,12 @@ config SNI_RM
575 bool "SNI RM200/300/400" 566 bool "SNI RM200/300/400"
576 select ARC if CPU_LITTLE_ENDIAN 567 select ARC if CPU_LITTLE_ENDIAN
577 select ARC32 if CPU_LITTLE_ENDIAN 568 select ARC32 if CPU_LITTLE_ENDIAN
569 select SNIPROM if CPU_BIG_ENDIAN
578 select ARCH_MAY_HAVE_PC_FDC 570 select ARCH_MAY_HAVE_PC_FDC
579 select BOOT_ELF32 571 select BOOT_ELF32
580 select CEVT_R4K 572 select CEVT_R4K
581 select CSRC_R4K 573 select CSRC_R4K
574 select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
582 select DMA_NONCOHERENT 575 select DMA_NONCOHERENT
583 select GENERIC_ISA_DMA 576 select GENERIC_ISA_DMA
584 select HW_HAS_EISA 577 select HW_HAS_EISA
@@ -587,7 +580,6 @@ config SNI_RM
587 select I8253 580 select I8253
588 select I8259 581 select I8259
589 select ISA 582 select ISA
590 select PCSPEAKER
591 select SWAP_IO_SPACE if CPU_BIG_ENDIAN 583 select SWAP_IO_SPACE if CPU_BIG_ENDIAN
592 select SYS_HAS_CPU_R4X00 584 select SYS_HAS_CPU_R4X00
593 select SYS_HAS_CPU_R5000 585 select SYS_HAS_CPU_R5000
@@ -690,6 +682,7 @@ config WR_PPMC
690endchoice 682endchoice
691 683
692source "arch/mips/au1000/Kconfig" 684source "arch/mips/au1000/Kconfig"
685source "arch/mips/basler/excite/Kconfig"
693source "arch/mips/jazz/Kconfig" 686source "arch/mips/jazz/Kconfig"
694source "arch/mips/lasat/Kconfig" 687source "arch/mips/lasat/Kconfig"
695source "arch/mips/pmc-sierra/Kconfig" 688source "arch/mips/pmc-sierra/Kconfig"
@@ -797,10 +790,6 @@ config DMA_COHERENT
797config DMA_IP27 790config DMA_IP27
798 bool 791 bool
799 792
800config DMA_IP32
801 bool
802 select DMA_NEED_PCI_MAP_STATE
803
804config DMA_NONCOHERENT 793config DMA_NONCOHERENT
805 bool 794 bool
806 select DMA_NEED_PCI_MAP_STATE 795 select DMA_NEED_PCI_MAP_STATE
@@ -956,16 +945,40 @@ config EMMA2RH
956config SERIAL_RM9000 945config SERIAL_RM9000
957 bool 946 bool
958 947
948config SGI_HAS_DS1286
949 bool
950
951config SGI_HAS_INDYDOG
952 bool
953
954config SGI_HAS_SEEQ
955 bool
956
957config SGI_HAS_WD93
958 bool
959
960config SGI_HAS_ZILOG
961 bool
962
963config SGI_HAS_I8042
964 bool
965
966config DEFAULT_SGI_PARTITION
967 bool
968
959config ARC32 969config ARC32
960 bool 970 bool
961 971
972config SNIPROM
973 bool
974
962config BOOT_ELF32 975config BOOT_ELF32
963 bool 976 bool
964 977
965config MIPS_L1_CACHE_SHIFT 978config MIPS_L1_CACHE_SHIFT
966 int 979 int
967 default "4" if MACH_DECSTATION 980 default "4" if MACH_DECSTATION
968 default "7" if SGI_IP27 || SNI_RM 981 default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
969 default "4" if PMC_MSP4200_EVAL 982 default "4" if PMC_MSP4200_EVAL
970 default "5" 983 default "5"
971 984
@@ -974,7 +987,7 @@ config HAVE_STD_PC_SERIAL_PORT
974 987
975config ARC_CONSOLE 988config ARC_CONSOLE
976 bool "ARC console support" 989 bool "ARC console support"
977 depends on SGI_IP22 || (SNI_RM && CPU_LITTLE_ENDIAN) 990 depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN)
978 991
979config ARC_MEMORY 992config ARC_MEMORY
980 bool 993 bool
@@ -983,7 +996,7 @@ config ARC_MEMORY
983 996
984config ARC_PROMLIB 997config ARC_PROMLIB
985 bool 998 bool
986 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32 999 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32
987 default y 1000 default y
988 1001
989config ARC64 1002config ARC64
@@ -1443,7 +1456,9 @@ config MIPS_MT_SMP
1443 select MIPS_MT 1456 select MIPS_MT
1444 select NR_CPUS_DEFAULT_2 1457 select NR_CPUS_DEFAULT_2
1445 select SMP 1458 select SMP
1459 select SYS_SUPPORTS_SCHED_SMT if SMP
1446 select SYS_SUPPORTS_SMP 1460 select SYS_SUPPORTS_SMP
1461 select SMP_UP
1447 help 1462 help
1448 This is a kernel model which is also known a VSMP or lately 1463 This is a kernel model which is also known a VSMP or lately
1449 has been marketesed into SMVP. 1464 has been marketesed into SMVP.
@@ -1460,6 +1475,7 @@ config MIPS_MT_SMTC
1460 select NR_CPUS_DEFAULT_8 1475 select NR_CPUS_DEFAULT_8
1461 select SMP 1476 select SMP
1462 select SYS_SUPPORTS_SMP 1477 select SYS_SUPPORTS_SMP
1478 select SMP_UP
1463 help 1479 help
1464 This is a kernel model which is known a SMTC or lately has been 1480 This is a kernel model which is known a SMTC or lately has been
1465 marketesed into SMVP. 1481 marketesed into SMVP.
@@ -1469,6 +1485,19 @@ endchoice
1469config MIPS_MT 1485config MIPS_MT
1470 bool 1486 bool
1471 1487
1488config SCHED_SMT
1489 bool "SMT (multithreading) scheduler support"
1490 depends on SYS_SUPPORTS_SCHED_SMT
1491 default n
1492 help
1493 SMT scheduler support improves the CPU scheduler's decision making
1494 when dealing with MIPS MT enabled cores at a cost of slightly
1495 increased overhead in some places. If unsure say N here.
1496
1497config SYS_SUPPORTS_SCHED_SMT
1498 bool
1499
1500
1472config SYS_SUPPORTS_MULTITHREADING 1501config SYS_SUPPORTS_MULTITHREADING
1473 bool 1502 bool
1474 1503
@@ -1589,15 +1618,6 @@ config CPU_HAS_SMARTMIPS
1589config CPU_HAS_WB 1618config CPU_HAS_WB
1590 bool 1619 bool
1591 1620
1592config 64BIT_CONTEXT
1593 bool "Save 64bit integer registers"
1594 depends on 32BIT && CPU_LOONGSON2
1595 help
1596 Loongson2 CPU is 64bit , when used in 32BIT mode, its integer
1597 registers can still be accessed as 64bit, mainly for multimedia
1598 instructions. We must have all 64bit save/restored to make sure
1599 those instructions to get correct result.
1600
1601# 1621#
1602# Vectored interrupt mode is an R2 feature 1622# Vectored interrupt mode is an R2 feature
1603# 1623#
@@ -1619,6 +1639,19 @@ config GENERIC_CLOCKEVENTS_BROADCAST
1619 bool 1639 bool
1620 1640
1621# 1641#
1642# CPU non-features
1643#
1644config CPU_DADDI_WORKAROUNDS
1645 bool
1646
1647config CPU_R4000_WORKAROUNDS
1648 bool
1649 select CPU_R4400_WORKAROUNDS
1650
1651config CPU_R4400_WORKAROUNDS
1652 bool
1653
1654#
1622# Use the generic interrupt handling code in kernel/irq/: 1655# Use the generic interrupt handling code in kernel/irq/:
1623# 1656#
1624config GENERIC_HARDIRQS 1657config GENERIC_HARDIRQS
@@ -1721,6 +1754,9 @@ config SMP
1721 1754
1722 If you don't know what to do here, say N. 1755 If you don't know what to do here, say N.
1723 1756
1757config SMP_UP
1758 bool
1759
1724config SYS_SUPPORTS_SMP 1760config SYS_SUPPORTS_SMP
1725 bool 1761 bool
1726 1762
@@ -1978,9 +2014,6 @@ config MMU
1978config I8253 2014config I8253
1979 bool 2015 bool
1980 2016
1981config PCSPEAKER
1982 bool
1983
1984config ZONE_DMA32 2017config ZONE_DMA32
1985 bool 2018 bool
1986 2019
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a1f8d8b96b03..3fb7f3065c92 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -141,6 +141,10 @@ cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
141cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ 141cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
142 -Wa,--trap 142 -Wa,--trap
143 143
144cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
145cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
146cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
147
144ifdef CONFIG_CPU_SB1 148ifdef CONFIG_CPU_SB1
145ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 149ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
146MODFLAGS += -msb1-pass1-workarounds 150MODFLAGS += -msb1-pass1-workarounds
@@ -152,6 +156,8 @@ endif
152# 156#
153libs-$(CONFIG_ARC) += arch/mips/fw/arc/ 157libs-$(CONFIG_ARC) += arch/mips/fw/arc/
154libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ 158libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
159libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
160libs-y += arch/mips/fw/lib/
155libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ 161libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
156 162
157# 163#
@@ -308,7 +314,7 @@ core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/
308cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas 314cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas
309cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips 315cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips
310load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 316load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000
311all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec 317all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin
312 318
313# 319#
314# MIPS Malta board 320# MIPS Malta board
@@ -316,7 +322,7 @@ all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec
316core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ 322core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/
317cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips 323cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips
318load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 324load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
319all-$(CONFIG_MIPS_MALTA) := vmlinux.srec 325all-$(CONFIG_MIPS_MALTA) := vmlinux.bin
320 326
321# 327#
322# MIPS SEAD board 328# MIPS SEAD board
@@ -349,14 +355,6 @@ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite
349load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 355load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
350 356
351# 357#
352# Qemu simulating MIPS32 4Kc
353#
354core-$(CONFIG_QEMU) += arch/mips/qemu/
355cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu
356load-$(CONFIG_QEMU) += 0xffffffff80010000
357all-$(CONFIG_QEMU) := vmlinux.bin
358
359#
360# Basler eXcite 358# Basler eXcite
361# 359#
362core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ 360core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
@@ -475,6 +473,20 @@ endif
475endif 473endif
476 474
477# 475#
476# SGI IP28 (Indigo2 R10k)
477#
478# Set the load address to >= 0xa800000020080000 if you want to leave space for
479# symmon, 0xa800000020004000 for production kernels ? Note that the value must
480# be 16kb aligned or the handling of the current variable will break.
481# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
482#
483#core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o
484core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
485cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28
486#cflags-$(CONFIG_SGI_IP28) += -Iinclude/asm-mips/mach-ip28
487load-$(CONFIG_SGI_IP28) += 0xa800000020004000
488
489#
478# SGI-IP32 (O2) 490# SGI-IP32 (O2)
479# 491#
480# Set the load address to >= 80069000 if you want to leave space for symmon, 492# Set the load address to >= 80069000 if you want to leave space for symmon,
@@ -602,9 +614,11 @@ ifdef CONFIG_64BIT
602 endif 614 endif
603 endif 615 endif
604 616
605 ifeq ($(KBUILD_SYM32), y) 617 ifeq ($(KBUILD_SYM32)$(call cc-option-yn,-msym32), yy)
606 ifeq ($(call cc-option-yn,-msym32), y) 618 cflags-y += -msym32 -DKBUILD_64BIT_SYM32
607 cflags-y += -msym32 -DKBUILD_64BIT_SYM32 619 else
620 ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y)
621 $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32)
608 endif 622 endif
609 endif 623 endif
610endif 624endif
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c
index 98a4e34b0248..37a10a01de9d 100644
--- a/arch/mips/au1000/common/au1xxx_irqmap.c
+++ b/arch/mips/au1000/common/au1xxx_irqmap.c
@@ -25,27 +25,10 @@
25 * with this program; if not, write to the Free Software Foundation, Inc., 25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */ 27 */
28#include <linux/errno.h>
29#include <linux/init.h> 28#include <linux/init.h>
30#include <linux/irq.h> 29#include <linux/kernel.h>
31#include <linux/kernel_stat.h>
32#include <linux/module.h>
33#include <linux/signal.h>
34#include <linux/sched.h>
35#include <linux/types.h>
36#include <linux/interrupt.h>
37#include <linux/ioport.h>
38#include <linux/timex.h>
39#include <linux/slab.h>
40#include <linux/random.h>
41#include <linux/delay.h>
42#include <linux/bitops.h>
43 30
44#include <asm/bootinfo.h> 31#include <au1000.h>
45#include <asm/io.h>
46#include <asm/mipsregs.h>
47#include <asm/system.h>
48#include <asm/mach-au1x00/au1000.h>
49 32
50/* The IC0 interrupt table. This is processor, rather than 33/* The IC0 interrupt table. This is processor, rather than
51 * board dependent, so no reason to keep this info in the board 34 * board dependent, so no reason to keep this info in the board
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index edf91f41a786..428ed275a0f6 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -179,7 +179,7 @@ static dbdev_tab_t dbdev_tab[] = {
179 { 0, 0, 0, 0, 0, 0, 0 }, 179 { 0, 0, 0, 0, 0, 0, 0 },
180}; 180};
181 181
182#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) 182#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
183 183
184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
185 185
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 43298fd9459c..e822c123eab8 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -57,17 +57,6 @@ void __init prom_init(void)
57 prom_argv = (char **) fw_arg1; 57 prom_argv = (char **) fw_arg1;
58 prom_envp = (char **) fw_arg2; 58 prom_envp = (char **) fw_arg2;
59 59
60 /* Set the platform # */
61#if defined(CONFIG_MIPS_DB1550)
62 mips_machtype = MACH_DB1550;
63#elif defined(CONFIG_MIPS_DB1500)
64 mips_machtype = MACH_DB1500;
65#elif defined(CONFIG_MIPS_DB1100)
66 mips_machtype = MACH_DB1100;
67#else
68 mips_machtype = MACH_DB1000;
69#endif
70
71 prom_init_cmdline(); 60 prom_init_cmdline();
72 61
73 memsize_str = prom_getenv("memsize"); 62 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c
index cdeae3212a2d..e700fd312a24 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/au1000/mtx-1/init.c
@@ -54,8 +54,6 @@ void __init prom_init(void)
54 prom_argv = (char **) fw_arg1; 54 prom_argv = (char **) fw_arg1;
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machtype = MACH_MTX1; /* set the platform # */
58
59 prom_init_cmdline(); 57 prom_init_cmdline();
60 58
61 memsize_str = prom_getenv("memsize"); 59 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/mtx-1/platform.c b/arch/mips/au1000/mtx-1/platform.c
index 49c0fb409fea..ce8637b3afa9 100644
--- a/arch/mips/au1000/mtx-1/platform.c
+++ b/arch/mips/au1000/mtx-1/platform.c
@@ -22,9 +22,32 @@
22#include <linux/types.h> 22#include <linux/types.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/leds.h> 24#include <linux/leds.h>
25#include <linux/gpio_keys.h>
26#include <linux/input.h>
25 27
26#include <asm/gpio.h> 28#include <asm/gpio.h>
27 29
30static struct gpio_keys_button mtx1_gpio_button[] = {
31 {
32 .gpio = 207,
33 .code = BTN_0,
34 .desc = "System button",
35 }
36};
37
38static struct gpio_keys_platform_data mtx1_buttons_data = {
39 .buttons = mtx1_gpio_button,
40 .nbuttons = ARRAY_SIZE(mtx1_gpio_button),
41};
42
43static struct platform_device mtx1_button = {
44 .name = "gpio-keys",
45 .id = -1,
46 .dev = {
47 .platform_data = &mtx1_buttons_data,
48 }
49};
50
28static struct resource mtx1_wdt_res[] = { 51static struct resource mtx1_wdt_res[] = {
29 [0] = { 52 [0] = {
30 .start = 15, 53 .start = 15,
@@ -66,11 +89,13 @@ static struct platform_device mtx1_gpio_leds = {
66 89
67static struct __initdata platform_device * mtx1_devs[] = { 90static struct __initdata platform_device * mtx1_devs[] = {
68 &mtx1_gpio_leds, 91 &mtx1_gpio_leds,
69 &mtx1_wdt 92 &mtx1_wdt,
93 &mtx1_button
70}; 94};
71 95
72static int __init mtx1_register_devices(void) 96static int __init mtx1_register_devices(void)
73{ 97{
98 gpio_direction_input(207);
74 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); 99 return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
75} 100}
76 101
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index ddccaf6997d0..2515b9fb24af 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -52,8 +52,6 @@ void __init prom_init(void)
52 prom_argv = (char **) fw_arg1; 52 prom_argv = (char **) fw_arg1;
53 prom_envp = (char **) fw_arg2; 53 prom_envp = (char **) fw_arg2;
54 54
55 mips_machtype = MACH_PB1000;
56
57 prom_init_cmdline(); 55 prom_init_cmdline();
58 memsize_str = prom_getenv("memsize"); 56 memsize_str = prom_getenv("memsize");
59 if (!memsize_str) { 57 if (!memsize_str) {
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c
index c93fd39b4aba..490c3801c275 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/au1000/pb1100/init.c
@@ -53,8 +53,6 @@ void __init prom_init(void)
53 prom_argv = (char **) fw_arg1; 53 prom_argv = (char **) fw_arg1;
54 prom_envp = (char **) fw_arg3; 54 prom_envp = (char **) fw_arg3;
55 55
56 mips_machtype = MACH_PB1100;
57
58 prom_init_cmdline(); 56 prom_init_cmdline();
59 57
60 memsize_str = prom_getenv("memsize"); 58 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
index c251570749ee..069ed45f04f2 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/au1000/pb1200/init.c
@@ -53,8 +53,6 @@ void __init prom_init(void)
53 prom_argv = (char **) fw_arg1; 53 prom_argv = (char **) fw_arg1;
54 prom_envp = (char **) fw_arg2; 54 prom_envp = (char **) fw_arg2;
55 55
56 mips_machtype = MACH_PB1200;
57
58 prom_init_cmdline(); 56 prom_init_cmdline();
59 memsize_str = prom_getenv("memsize"); 57 memsize_str = prom_getenv("memsize");
60 if (!memsize_str) { 58 if (!memsize_str) {
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/au1000/pb1500/init.c
index 507d4b204161..db558c967048 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/au1000/pb1500/init.c
@@ -53,8 +53,6 @@ void __init prom_init(void)
53 prom_argv = (char **) fw_arg1; 53 prom_argv = (char **) fw_arg1;
54 prom_envp = (char **) fw_arg2; 54 prom_envp = (char **) fw_arg2;
55 55
56 mips_machtype = MACH_PB1500;
57
58 prom_init_cmdline(); 56 prom_init_cmdline();
59 memsize_str = prom_getenv("memsize"); 57 memsize_str = prom_getenv("memsize");
60 if (!memsize_str) { 58 if (!memsize_str) {
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c
index b03eee601e36..b716363ea564 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/au1000/pb1550/init.c
@@ -53,8 +53,6 @@ void __init prom_init(void)
53 prom_argv = (char **) fw_arg1; 53 prom_argv = (char **) fw_arg1;
54 prom_envp = (char **) fw_arg2; 54 prom_envp = (char **) fw_arg2;
55 55
56 mips_machtype = MACH_PB1550;
57
58 prom_init_cmdline(); 56 prom_init_cmdline();
59 memsize_str = prom_getenv("memsize"); 57 memsize_str = prom_getenv("memsize");
60 if (!memsize_str) { 58 if (!memsize_str) {
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index 6532939f377a..7e6878c1b0a5 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -52,8 +52,6 @@ void __init prom_init(void)
52 prom_argv = (char **) fw_arg1; 52 prom_argv = (char **) fw_arg1;
53 prom_envp = (char **) fw_arg2; 53 prom_envp = (char **) fw_arg2;
54 54
55 mips_machtype = MACH_XXS1500; /* set the platform # */
56
57 prom_init_cmdline(); 55 prom_init_cmdline();
58 56
59 memsize_str = prom_getenv("memsize"); 57 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/basler/excite/Kconfig b/arch/mips/basler/excite/Kconfig
new file mode 100644
index 000000000000..ba506075608b
--- /dev/null
+++ b/arch/mips/basler/excite/Kconfig
@@ -0,0 +1,9 @@
1config BASLER_EXCITE_PROTOTYPE
2 bool "Support for pre-release units"
3 depends on BASLER_EXCITE
4 default n
5 help
6 Pre-series (prototype) units are different from later ones in
7 some ways. Select this option if you have one of these. Please
8 note that a kernel built with this option selected will not be
9 able to run on normal units.
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
index 6af0b21ebc32..476d20e08d0e 100644
--- a/arch/mips/basler/excite/excite_iodev.c
+++ b/arch/mips/basler/excite/excite_iodev.c
@@ -48,7 +48,7 @@ static DECLARE_WAIT_QUEUE_HEAD(wq);
48 48
49 49
50 50
51static struct file_operations fops = 51static const struct file_operations fops =
52{ 52{
53 .owner = THIS_MODULE, 53 .owner = THIS_MODULE,
54 .open = iodev_open, 54 .open = iodev_open,
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
index 2d752c2f6e59..68d8bc597e34 100644
--- a/arch/mips/basler/excite/excite_prom.c
+++ b/arch/mips/basler/excite/excite_prom.c
@@ -135,8 +135,6 @@ void __init prom_init(void)
135#ifdef CONFIG_64BIT 135#ifdef CONFIG_64BIT
136# error 64 bit support not implemented 136# error 64 bit support not implemented
137#endif /* CONFIG_64BIT */ 137#endif /* CONFIG_64BIT */
138
139 mips_machtype = MACH_TITAN_EXCITE;
140} 138}
141 139
142/* This is called from free_initmem(), so we need to provide it */ 140/* This is called from free_initmem(), so we need to provide it */
diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c
index 71eb4ccc4bc1..516b4428df4e 100644
--- a/arch/mips/cobalt/reset.c
+++ b/arch/mips/cobalt/reset.c
@@ -10,9 +10,10 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/jiffies.h>
14#include <linux/leds.h> 13#include <linux/leds.h>
15 14
15#include <asm/processor.h>
16
16#include <cobalt.h> 17#include <cobalt.h>
17 18
18#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000)) 19#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
@@ -29,28 +30,15 @@ device_initcall(ledtrig_power_off_init);
29 30
30void cobalt_machine_halt(void) 31void cobalt_machine_halt(void)
31{ 32{
32 int state, last, diff;
33 unsigned long mark;
34
35 /* 33 /*
36 * turn on power off LED on RaQ 34 * turn on power off LED on RaQ
37 *
38 * restart if ENTER and SELECT are pressed
39 */ 35 */
40
41 last = COBALT_KEY_PORT;
42
43 led_trigger_event(power_off_led_trigger, LED_FULL); 36 led_trigger_event(power_off_led_trigger, LED_FULL);
44 37
45 for (state = 0;;) { 38 local_irq_disable();
46 diff = COBALT_KEY_PORT ^ last; 39 while (1) {
47 last ^= diff; 40 if (cpu_wait)
48 41 cpu_wait();
49 if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
50 writeb(RESET, RESET_PORT);
51
52 for (mark = jiffies; jiffies - mark < HZ;)
53 ;
54 } 42 }
55} 43}
56 44
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 62bcc887f2ca..3443f6cd57bb 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -37,7 +37,6 @@ CONFIG_MIPS_ATLAS=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_MIPS_ATLAS=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 3c70c9d16d01..abf70d74e9d7 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_SIBYTE_BIGSUR=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 8ecbbb226c76..a94f14b5c8fa 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 36c13039e237..b7295e988381 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -24,7 +24,6 @@ CONFIG_MIPS_COBALT=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MIPS_COBALT=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 5a8b7acb7dd7..36578968d386 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_DB1000=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_DB1000=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index d4ed90bca269..5a90740c363a 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_DB1100=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_DB1100=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index a055657e6983..76f37a1159fe 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_DB1200=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_DB1200=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 0ad08cf446ec..508c91944f30 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_DB1500=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_DB1500=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 057c7d429c80..0c2c70d21db9 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_DB1550=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_DB1550=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 2fb350432669..58c2cd68c3a7 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -37,7 +37,6 @@ CONFIG_MACH_DECSTATION=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_MACH_DECSTATION=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index d0d07faeb844..90d81f5dcebc 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index d73d965f7615..f9a003c2b3a1 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41CONFIG_MARKEINS=y 40CONFIG_MARKEINS=y
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_MARKEINS=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 17a866057fd4..15efacc75d73 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -38,7 +38,6 @@ CONFIG_BASLER_EXCITE=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_BASLER_EXCITE=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig
index 4ef39a0527cc..5887a1735fba 100644
--- a/arch/mips/configs/fulong_defconfig
+++ b/arch/mips/configs/fulong_defconfig
@@ -23,7 +23,6 @@ CONFIG_LEMOTE_FULONG=y
23# CONFIG_PNX8550_STB810 is not set 23# CONFIG_PNX8550_STB810 is not set
24# CONFIG_MACH_VR41XX is not set 24# CONFIG_MACH_VR41XX is not set
25# CONFIG_PMC_YOSEMITE is not set 25# CONFIG_PMC_YOSEMITE is not set
26# CONFIG_QEMU is not set
27# CONFIG_MARKEINS is not set 26# CONFIG_MARKEINS is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
@@ -33,7 +32,6 @@ CONFIG_LEMOTE_FULONG=y
33# CONFIG_SIBYTE_SENTOSA is not set 32# CONFIG_SIBYTE_SENTOSA is not set
34# CONFIG_SIBYTE_RHONE is not set 33# CONFIG_SIBYTE_RHONE is not set
35# CONFIG_SIBYTE_CARMEL is not set 34# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_PTSWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_CRHINE is not set 36# CONFIG_SIBYTE_CRHINE is not set
39# CONFIG_SIBYTE_CRHONE is not set 37# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 670039bb1a7c..4f5e56c9335e 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -25,7 +25,6 @@ CONFIG_ZONE_DMA=y
25# CONFIG_PNX8550_STB810 is not set 25# CONFIG_PNX8550_STB810 is not set
26# CONFIG_PMC_MSP is not set 26# CONFIG_PMC_MSP is not set
27# CONFIG_PMC_YOSEMITE is not set 27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29CONFIG_SGI_IP22=y 28CONFIG_SGI_IP22=y
30# CONFIG_SGI_IP27 is not set 29# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP32 is not set 30# CONFIG_SGI_IP32 is not set
@@ -36,7 +35,6 @@ CONFIG_SGI_IP22=y
36# CONFIG_SIBYTE_SWARM is not set 35# CONFIG_SIBYTE_SWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set 36# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_SENTOSA is not set 37# CONFIG_SIBYTE_SENTOSA is not set
39# CONFIG_SIBYTE_PTSWARM is not set
40# CONFIG_SIBYTE_BIGSUR is not set 38# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set 39# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set 40# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 892d4c38fd0d..f40e437bd9e5 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -24,7 +24,6 @@ CONFIG_MIPS=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29CONFIG_SGI_IP27=y 28CONFIG_SGI_IP27=y
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_SGI_IP27=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index 47f49b60c5d6..2c5c624c5d42 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_SGI_IP32=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index fa655e247ecc..56148745e8f2 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -37,7 +37,6 @@ CONFIG_MACH_JAZZ=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_MACH_JAZZ=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index eb96791c33ea..a7cd67753aac 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -24,7 +24,6 @@ CONFIG_MIPS=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MIPS=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41CONFIG_TOSHIBA_JMR3927=y 39CONFIG_TOSHIBA_JMR3927=y
@@ -464,7 +462,6 @@ CONFIG_SERIAL_TXX9_STDSERIAL=y
464CONFIG_LEGACY_PTYS=y 462CONFIG_LEGACY_PTYS=y
465CONFIG_LEGACY_PTY_COUNT=256 463CONFIG_LEGACY_PTY_COUNT=256
466# CONFIG_IPMI_HANDLER is not set 464# CONFIG_IPMI_HANDLER is not set
467# CONFIG_WATCHDOG is not set
468# CONFIG_HW_RANDOM is not set 465# CONFIG_HW_RANDOM is not set
469# CONFIG_RTC is not set 466# CONFIG_RTC is not set
470# CONFIG_R3964 is not set 467# CONFIG_R3964 is not set
@@ -482,6 +479,20 @@ CONFIG_DEVPORT=y
482# CONFIG_W1 is not set 479# CONFIG_W1 is not set
483# CONFIG_POWER_SUPPLY is not set 480# CONFIG_POWER_SUPPLY is not set
484# CONFIG_HWMON is not set 481# CONFIG_HWMON is not set
482CONFIG_WATCHDOG=y
483# CONFIG_WATCHDOG_NOWAYOUT is not set
484
485#
486# Watchdog Device Drivers
487#
488# CONFIG_SOFT_WATCHDOG is not set
489CONFIG_TXX9_WDT=y
490
491#
492# PCI-based Watchdog Cards
493#
494# CONFIG_PCIPCWATCHDOG is not set
495# CONFIG_WDTPCI is not set
485 496
486# 497#
487# Multifunction device drivers 498# Multifunction device drivers
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index 2c665fcef089..e6aef999854c 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -25,7 +25,6 @@ CONFIG_LASAT=y
25# CONFIG_PNX8550_STB810 is not set 25# CONFIG_PNX8550_STB810 is not set
26# CONFIG_PMC_MSP is not set 26# CONFIG_PMC_MSP is not set
27# CONFIG_PMC_YOSEMITE is not set 27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29# CONFIG_SGI_IP22 is not set 28# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set 29# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP32 is not set 30# CONFIG_SGI_IP32 is not set
@@ -36,7 +35,6 @@ CONFIG_LASAT=y
36# CONFIG_SIBYTE_SWARM is not set 35# CONFIG_SIBYTE_SWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set 36# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_SENTOSA is not set 37# CONFIG_SIBYTE_SENTOSA is not set
39# CONFIG_SIBYTE_PTSWARM is not set
40# CONFIG_SIBYTE_BIGSUR is not set 38# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set 39# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set 40# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 4b7e43c9f69a..3d0da952811c 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_MALTA=y
25# CONFIG_PNX8550_STB810 is not set 25# CONFIG_PNX8550_STB810 is not set
26# CONFIG_PMC_MSP is not set 26# CONFIG_PMC_MSP is not set
27# CONFIG_PMC_YOSEMITE is not set 27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29# CONFIG_SGI_IP22 is not set 28# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set 29# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP32 is not set 30# CONFIG_SGI_IP32 is not set
@@ -36,7 +35,6 @@ CONFIG_MIPS_MALTA=y
36# CONFIG_SIBYTE_SWARM is not set 35# CONFIG_SIBYTE_SWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set 36# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_SENTOSA is not set 37# CONFIG_SIBYTE_SENTOSA is not set
39# CONFIG_SIBYTE_PTSWARM is not set
40# CONFIG_SIBYTE_BIGSUR is not set 38# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set 39# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set 40# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 61b72f5a953e..6db0bdaefb27 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -26,7 +26,6 @@ CONFIG_MIPS_SIM=y
26# CONFIG_PNX8550_STB810 is not set 26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set 27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set 28# CONFIG_PMC_YOSEMITE is not set
29# CONFIG_QEMU is not set
30# CONFIG_SGI_IP22 is not set 29# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set 30# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP32 is not set 31# CONFIG_SGI_IP32 is not set
@@ -37,7 +36,6 @@ CONFIG_MIPS_SIM=y
37# CONFIG_SIBYTE_SWARM is not set 36# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set 37# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set 38# CONFIG_SIBYTE_SENTOSA is not set
40# CONFIG_SIBYTE_PTSWARM is not set
41# CONFIG_SIBYTE_BIGSUR is not set 39# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set 40# CONFIG_SNI_RM is not set
43# CONFIG_TOSHIBA_JMR3927 is not set 41# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 8334350d7229..27e23fc9363a 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 69278999c9a2..b12b73f6d74f 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -38,7 +38,6 @@ CONFIG_ZONE_DMA=y
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39CONFIG_PMC_MSP=y 39CONFIG_PMC_MSP=y
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_PMC_MSP=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index b536d7c63790..fa3aa3919448 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_ALCHEMY=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_ALCHEMY=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
@@ -1617,6 +1615,7 @@ CONFIG_INPUT_EVBUG=m
1617# 1615#
1618CONFIG_INPUT_KEYBOARD=y 1616CONFIG_INPUT_KEYBOARD=y
1619CONFIG_KEYBOARD_ATKBD=y 1617CONFIG_KEYBOARD_ATKBD=y
1618CONFIG_KEYBOARD_GPIO=y
1620CONFIG_KEYBOARD_SUNKBD=m 1619CONFIG_KEYBOARD_SUNKBD=m
1621CONFIG_KEYBOARD_LKKBD=m 1620CONFIG_KEYBOARD_LKKBD=m
1622CONFIG_KEYBOARD_XTKBD=m 1621CONFIG_KEYBOARD_XTKBD=m
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 703d28db05b9..1d0157d3a5bb 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_PB1100=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_PB1100=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 82f0c5cee0dc..d0491a05ee58 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_PB1500=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_PB1500=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 147a4fc7fdd8..16d78d3cd2aa 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -38,7 +38,6 @@ CONFIG_MIPS_PB1550=y
38# CONFIG_PNX8550_STB810 is not set 38# CONFIG_PNX8550_STB810 is not set
39# CONFIG_MACH_VR41XX is not set 39# CONFIG_MACH_VR41XX is not set
40# CONFIG_PMC_YOSEMITE is not set 40# CONFIG_PMC_YOSEMITE is not set
41# CONFIG_QEMU is not set
42# CONFIG_MARKEINS is not set 41# CONFIG_MARKEINS is not set
43# CONFIG_SGI_IP22 is not set 42# CONFIG_SGI_IP22 is not set
44# CONFIG_SGI_IP27 is not set 43# CONFIG_SGI_IP27 is not set
@@ -48,7 +47,6 @@ CONFIG_MIPS_PB1550=y
48# CONFIG_SIBYTE_SENTOSA is not set 47# CONFIG_SIBYTE_SENTOSA is not set
49# CONFIG_SIBYTE_RHONE is not set 48# CONFIG_SIBYTE_RHONE is not set
50# CONFIG_SIBYTE_CARMEL is not set 49# CONFIG_SIBYTE_CARMEL is not set
51# CONFIG_SIBYTE_PTSWARM is not set
52# CONFIG_SIBYTE_LITTLESUR is not set 50# CONFIG_SIBYTE_LITTLESUR is not set
53# CONFIG_SIBYTE_CRHINE is not set 51# CONFIG_SIBYTE_CRHINE is not set
54# CONFIG_SIBYTE_CRHONE is not set 52# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index f6906b069e04..518a60892b78 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -37,7 +37,6 @@ CONFIG_PNX8550_JBS=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_PNX8550_JBS=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index b741f81696fb..68351eb81bc8 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37CONFIG_PNX8550_STB810=y 37CONFIG_PNX8550_STB810=y
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_PNX8550_STB810=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index b3caf5125c15..72ca147f9422 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40CONFIG_QEMU=y
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_QEMU=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/rbhma4200_defconfig b/arch/mips/configs/rbhma4200_defconfig
index 9383a598094b..470f6f4d3ea2 100644
--- a/arch/mips/configs/rbhma4200_defconfig
+++ b/arch/mips/configs/rbhma4200_defconfig
@@ -24,7 +24,6 @@ CONFIG_MIPS=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MIPS=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
@@ -431,7 +429,6 @@ CONFIG_UNIX98_PTYS=y
431CONFIG_LEGACY_PTYS=y 429CONFIG_LEGACY_PTYS=y
432CONFIG_LEGACY_PTY_COUNT=256 430CONFIG_LEGACY_PTY_COUNT=256
433# CONFIG_IPMI_HANDLER is not set 431# CONFIG_IPMI_HANDLER is not set
434# CONFIG_WATCHDOG is not set
435# CONFIG_HW_RANDOM is not set 432# CONFIG_HW_RANDOM is not set
436# CONFIG_RTC is not set 433# CONFIG_RTC is not set
437# CONFIG_R3964 is not set 434# CONFIG_R3964 is not set
@@ -449,6 +446,20 @@ CONFIG_DEVPORT=y
449# CONFIG_W1 is not set 446# CONFIG_W1 is not set
450# CONFIG_POWER_SUPPLY is not set 447# CONFIG_POWER_SUPPLY is not set
451# CONFIG_HWMON is not set 448# CONFIG_HWMON is not set
449CONFIG_WATCHDOG=y
450# CONFIG_WATCHDOG_NOWAYOUT is not set
451
452#
453# Watchdog Device Drivers
454#
455# CONFIG_SOFT_WATCHDOG is not set
456CONFIG_TXX9_WDT=m
457
458#
459# PCI-based Watchdog Cards
460#
461# CONFIG_PCIPCWATCHDOG is not set
462# CONFIG_WDTPCI is not set
452 463
453# 464#
454# Multifunction device drivers 465# Multifunction device drivers
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index d1b56cc0fd7c..5a39f56b175e 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -24,7 +24,6 @@ CONFIG_MIPS=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MIPS=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
@@ -450,7 +448,6 @@ CONFIG_UNIX98_PTYS=y
450CONFIG_LEGACY_PTYS=y 448CONFIG_LEGACY_PTYS=y
451CONFIG_LEGACY_PTY_COUNT=256 449CONFIG_LEGACY_PTY_COUNT=256
452# CONFIG_IPMI_HANDLER is not set 450# CONFIG_IPMI_HANDLER is not set
453# CONFIG_WATCHDOG is not set
454# CONFIG_HW_RANDOM is not set 451# CONFIG_HW_RANDOM is not set
455# CONFIG_RTC is not set 452# CONFIG_RTC is not set
456# CONFIG_R3964 is not set 453# CONFIG_R3964 is not set
@@ -479,6 +476,20 @@ CONFIG_SPI_AT25=y
479# CONFIG_W1 is not set 476# CONFIG_W1 is not set
480# CONFIG_POWER_SUPPLY is not set 477# CONFIG_POWER_SUPPLY is not set
481# CONFIG_HWMON is not set 478# CONFIG_HWMON is not set
479CONFIG_WATCHDOG=y
480# CONFIG_WATCHDOG_NOWAYOUT is not set
481
482#
483# Watchdog Device Drivers
484#
485# CONFIG_SOFT_WATCHDOG is not set
486CONFIG_TXX9_WDT=m
487
488#
489# PCI-based Watchdog Cards
490#
491# CONFIG_PCIPCWATCHDOG is not set
492# CONFIG_WDTPCI is not set
482 493
483# 494#
484# Multifunction device drivers 495# Multifunction device drivers
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index fc388118b114..56371b860eb0 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_ZONE_DMA=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index c2798229cbfb..117470b60e34 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_SIBYTE_SWARM=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 2b6282d132a8..3ee75b15c0b0 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -37,7 +37,6 @@ CONFIG_MIPS_SEAD=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_MIPS_SEAD=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index 326aa7aa40ea..af82e1a1823c 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index 9fd0faeacf53..a95385b24546 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 499b6bd7ee68..40d4a40a970e 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index b52256ca0b53..edf90b321fe6 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -24,7 +24,6 @@ CONFIG_MACH_VR41XX=y
24# CONFIG_PNX8550_STB810 is not set 24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set 25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set 26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set 27# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set 28# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set 29# CONFIG_SGI_IP32 is not set
@@ -35,7 +34,6 @@ CONFIG_MACH_VR41XX=y
35# CONFIG_SIBYTE_SWARM is not set 34# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set 35# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set 36# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set 37# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set 38# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set 39# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 7e410e10fed7..2e3c683b2052 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -37,7 +37,6 @@ CONFIG_WR_PPMC=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39# CONFIG_PMC_YOSEMITE is not set 39# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_WR_PPMC=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index acaf0e21bb00..b6178ffbc523 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -37,7 +37,6 @@ CONFIG_ZONE_DMA=y
37# CONFIG_PNX8550_STB810 is not set 37# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 38# CONFIG_MACH_VR41XX is not set
39CONFIG_PMC_YOSEMITE=y 39CONFIG_PMC_YOSEMITE=y
40# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set 40# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 41# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 42# CONFIG_SGI_IP27 is not set
@@ -47,7 +46,6 @@ CONFIG_PMC_YOSEMITE=y
47# CONFIG_SIBYTE_SENTOSA is not set 46# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set 47# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set 48# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 49# CONFIG_SIBYTE_LITTLESUR is not set
52# CONFIG_SIBYTE_CRHINE is not set 50# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set 51# CONFIG_SIBYTE_CRHONE is not set
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 820e5331205f..60349062595a 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -161,7 +161,6 @@ static cycle_t dec_ioasic_hpt_read(void)
161 161
162void __init plat_time_init(void) 162void __init plat_time_init(void)
163{ 163{
164 mips_timer_state = dec_timer_state;
165 mips_timer_ack = dec_timer_ack; 164 mips_timer_ack = dec_timer_ack;
166 165
167 if (!cpu_has_counter && IOASIC) 166 if (!cpu_has_counter && IOASIC)
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index 670039bb1a7c..4f5e56c9335e 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -25,7 +25,6 @@ CONFIG_ZONE_DMA=y
25# CONFIG_PNX8550_STB810 is not set 25# CONFIG_PNX8550_STB810 is not set
26# CONFIG_PMC_MSP is not set 26# CONFIG_PMC_MSP is not set
27# CONFIG_PMC_YOSEMITE is not set 27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29CONFIG_SGI_IP22=y 28CONFIG_SGI_IP22=y
30# CONFIG_SGI_IP27 is not set 29# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP32 is not set 30# CONFIG_SGI_IP32 is not set
@@ -36,7 +35,6 @@ CONFIG_SGI_IP22=y
36# CONFIG_SIBYTE_SWARM is not set 35# CONFIG_SIBYTE_SWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set 36# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_SENTOSA is not set 37# CONFIG_SIBYTE_SENTOSA is not set
39# CONFIG_SIBYTE_PTSWARM is not set
40# CONFIG_SIBYTE_BIGSUR is not set 38# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set 39# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set 40# CONFIG_TOSHIBA_JMR3927 is not set
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index fd604ef28823..4ca4eef934a5 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -52,7 +52,7 @@ static char * __init move_firmware_args(char* cp)
52 strcat(cp, used_arc[i][1]); 52 strcat(cp, used_arc[i][1]);
53 cp += strlen(used_arc[i][1]); 53 cp += strlen(used_arc[i][1]);
54 /* ... and now the argument */ 54 /* ... and now the argument */
55 s = strstr(prom_argv(actr), "="); 55 s = strchr(prom_argv(actr), '=');
56 if (s) { 56 if (s) {
57 s++; 57 s++;
58 strcpy(cp, s); 58 strcpy(cp, s);
diff --git a/arch/mips/fw/arc/init.c b/arch/mips/fw/arc/init.c
index e2f75b13312f..3ad8788b6eaa 100644
--- a/arch/mips/fw/arc/init.c
+++ b/arch/mips/fw/arc/init.c
@@ -12,6 +12,7 @@
12 12
13#include <asm/bootinfo.h> 13#include <asm/bootinfo.h>
14#include <asm/sgialib.h> 14#include <asm/sgialib.h>
15#include <asm/smp-ops.h>
15 16
16#undef DEBUG_PROM_INIT 17#undef DEBUG_PROM_INIT
17 18
@@ -48,4 +49,11 @@ void __init prom_init(void)
48 ArcRead(0, &c, 1, &cnt); 49 ArcRead(0, &c, 1, &cnt);
49 ArcEnterInteractiveMode(); 50 ArcEnterInteractiveMode();
50#endif 51#endif
52#ifdef CONFIG_SGI_IP27
53 {
54 extern struct plat_smp_ops ip27_smp_ops;
55
56 register_smp_ops(&ip27_smp_ops);
57 }
58#endif
51} 59}
diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
index a9f69e4e40ac..717db74f7c6e 100644
--- a/arch/mips/fw/cfe/cfe_api.c
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -16,19 +16,16 @@
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18
19/* ********************************************************************* 19/*
20 * 20 *
21 * Broadcom Common Firmware Environment (CFE) 21 * Broadcom Common Firmware Environment (CFE)
22 * 22 *
23 * Device Function stubs File: cfe_api.c 23 * This module contains device function stubs (small routines to
24 * 24 * call the standard "iocb" interface entry point to CFE).
25 * This module contains device function stubs (small routines to 25 * There should be one routine here per iocb function call.
26 * call the standard "iocb" interface entry point to CFE). 26 *
27 * There should be one routine here per iocb function call. 27 * Authors: Mitch Lichtenberg, Chris Demetriou
28 * 28 */
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32 29
33#include <asm/fw/cfe/cfe_api.h> 30#include <asm/fw/cfe/cfe_api.h>
34#include "cfe_api_int.h" 31#include "cfe_api_int.h"
@@ -37,12 +34,8 @@
37#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n)) 34#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n))
38#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x)) 35#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x))
39 36
40#ifdef CFE_API_IMPL_NAMESPACE 37int cfe_iocb_dispatch(struct cfe_xiocb *xiocb);
41#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a)
42#endif
43int cfe_iocb_dispatch(cfe_xiocb_t * xiocb);
44 38
45#if defined(CFE_API_common) || defined(CFE_API_ALL)
46/* 39/*
47 * Declare the dispatch function with args of "intptr_t". 40 * Declare the dispatch function with args of "intptr_t".
48 * This makes sure whatever model we're compiling in 41 * This makes sure whatever model we're compiling in
@@ -53,27 +46,25 @@ int cfe_iocb_dispatch(cfe_xiocb_t * xiocb);
53 */ 46 */
54 47
55static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; 48static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0;
56static cfe_xuint_t cfe_handle = 0; 49static u64 cfe_handle = 0;
57 50
58int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept) 51int cfe_init(u64 handle, u64 ept)
59{ 52{
60 cfe_dispfunc = NATIVE_FROM_XPTR(ept); 53 cfe_dispfunc = NATIVE_FROM_XPTR(ept);
61 cfe_handle = handle; 54 cfe_handle = handle;
62 return 0; 55 return 0;
63} 56}
64 57
65int cfe_iocb_dispatch(cfe_xiocb_t * xiocb) 58int cfe_iocb_dispatch(struct cfe_xiocb * xiocb)
66{ 59{
67 if (!cfe_dispfunc) 60 if (!cfe_dispfunc)
68 return -1; 61 return -1;
69 return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb); 62 return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb);
70} 63}
71#endif /* CFE_API_common || CFE_API_ALL */
72 64
73#if defined(CFE_API_close) || defined(CFE_API_ALL)
74int cfe_close(int handle) 65int cfe_close(int handle)
75{ 66{
76 cfe_xiocb_t xiocb; 67 struct cfe_xiocb xiocb;
77 68
78 xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE; 69 xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
79 xiocb.xiocb_status = 0; 70 xiocb.xiocb_status = 0;
@@ -86,18 +77,16 @@ int cfe_close(int handle)
86 return xiocb.xiocb_status; 77 return xiocb.xiocb_status;
87 78
88} 79}
89#endif /* CFE_API_close || CFE_API_ALL */
90 80
91#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL)
92int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) 81int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
93{ 82{
94 cfe_xiocb_t xiocb; 83 struct cfe_xiocb xiocb;
95 84
96 xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; 85 xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
97 xiocb.xiocb_status = 0; 86 xiocb.xiocb_status = 0;
98 xiocb.xiocb_handle = 0; 87 xiocb.xiocb_handle = 0;
99 xiocb.xiocb_flags = 0; 88 xiocb.xiocb_flags = 0;
100 xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); 89 xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
101 xiocb.plist.xiocb_cpuctl.cpu_number = cpu; 90 xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
102 xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START; 91 xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
103 xiocb.plist.xiocb_cpuctl.gp_val = gp; 92 xiocb.plist.xiocb_cpuctl.gp_val = gp;
@@ -109,18 +98,16 @@ int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
109 98
110 return xiocb.xiocb_status; 99 return xiocb.xiocb_status;
111} 100}
112#endif /* CFE_API_cpu_start || CFE_API_ALL */
113 101
114#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL)
115int cfe_cpu_stop(int cpu) 102int cfe_cpu_stop(int cpu)
116{ 103{
117 cfe_xiocb_t xiocb; 104 struct cfe_xiocb xiocb;
118 105
119 xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; 106 xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
120 xiocb.xiocb_status = 0; 107 xiocb.xiocb_status = 0;
121 xiocb.xiocb_handle = 0; 108 xiocb.xiocb_handle = 0;
122 xiocb.xiocb_flags = 0; 109 xiocb.xiocb_flags = 0;
123 xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); 110 xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
124 xiocb.plist.xiocb_cpuctl.cpu_number = cpu; 111 xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
125 xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP; 112 xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
126 113
@@ -128,18 +115,16 @@ int cfe_cpu_stop(int cpu)
128 115
129 return xiocb.xiocb_status; 116 return xiocb.xiocb_status;
130} 117}
131#endif /* CFE_API_cpu_stop || CFE_API_ALL */
132 118
133#if defined(CFE_API_enumenv) || defined(CFE_API_ALL)
134int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) 119int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
135{ 120{
136 cfe_xiocb_t xiocb; 121 struct cfe_xiocb xiocb;
137 122
138 xiocb.xiocb_fcode = CFE_CMD_ENV_SET; 123 xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
139 xiocb.xiocb_status = 0; 124 xiocb.xiocb_status = 0;
140 xiocb.xiocb_handle = 0; 125 xiocb.xiocb_handle = 0;
141 xiocb.xiocb_flags = 0; 126 xiocb.xiocb_flags = 0;
142 xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); 127 xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
143 xiocb.plist.xiocb_envbuf.enum_idx = idx; 128 xiocb.plist.xiocb_envbuf.enum_idx = idx;
144 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); 129 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
145 xiocb.plist.xiocb_envbuf.name_length = namelen; 130 xiocb.plist.xiocb_envbuf.name_length = namelen;
@@ -150,20 +135,17 @@ int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
150 135
151 return xiocb.xiocb_status; 136 return xiocb.xiocb_status;
152} 137}
153#endif /* CFE_API_enumenv || CFE_API_ALL */
154 138
155#if defined(CFE_API_enummem) || defined(CFE_API_ALL)
156int 139int
157cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length, 140cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type)
158 cfe_xuint_t * type)
159{ 141{
160 cfe_xiocb_t xiocb; 142 struct cfe_xiocb xiocb;
161 143
162 xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM; 144 xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
163 xiocb.xiocb_status = 0; 145 xiocb.xiocb_status = 0;
164 xiocb.xiocb_handle = 0; 146 xiocb.xiocb_handle = 0;
165 xiocb.xiocb_flags = flags; 147 xiocb.xiocb_flags = flags;
166 xiocb.xiocb_psize = sizeof(xiocb_meminfo_t); 148 xiocb.xiocb_psize = sizeof(struct xiocb_meminfo);
167 xiocb.plist.xiocb_meminfo.mi_idx = idx; 149 xiocb.plist.xiocb_meminfo.mi_idx = idx;
168 150
169 cfe_iocb_dispatch(&xiocb); 151 cfe_iocb_dispatch(&xiocb);
@@ -177,30 +159,26 @@ cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length,
177 159
178 return 0; 160 return 0;
179} 161}
180#endif /* CFE_API_enummem || CFE_API_ALL */
181 162
182#if defined(CFE_API_exit) || defined(CFE_API_ALL)
183int cfe_exit(int warm, int status) 163int cfe_exit(int warm, int status)
184{ 164{
185 cfe_xiocb_t xiocb; 165 struct cfe_xiocb xiocb;
186 166
187 xiocb.xiocb_fcode = CFE_CMD_FW_RESTART; 167 xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
188 xiocb.xiocb_status = 0; 168 xiocb.xiocb_status = 0;
189 xiocb.xiocb_handle = 0; 169 xiocb.xiocb_handle = 0;
190 xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0; 170 xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
191 xiocb.xiocb_psize = sizeof(xiocb_exitstat_t); 171 xiocb.xiocb_psize = sizeof(struct xiocb_exitstat);
192 xiocb.plist.xiocb_exitstat.status = status; 172 xiocb.plist.xiocb_exitstat.status = status;
193 173
194 cfe_iocb_dispatch(&xiocb); 174 cfe_iocb_dispatch(&xiocb);
195 175
196 return xiocb.xiocb_status; 176 return xiocb.xiocb_status;
197} 177}
198#endif /* CFE_API_exit || CFE_API_ALL */
199 178
200#if defined(CFE_API_flushcache) || defined(CFE_API_ALL)
201int cfe_flushcache(int flg) 179int cfe_flushcache(int flg)
202{ 180{
203 cfe_xiocb_t xiocb; 181 struct cfe_xiocb xiocb;
204 182
205 xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE; 183 xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
206 xiocb.xiocb_status = 0; 184 xiocb.xiocb_status = 0;
@@ -212,34 +190,30 @@ int cfe_flushcache(int flg)
212 190
213 return xiocb.xiocb_status; 191 return xiocb.xiocb_status;
214} 192}
215#endif /* CFE_API_flushcache || CFE_API_ALL */
216 193
217#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL)
218int cfe_getdevinfo(char *name) 194int cfe_getdevinfo(char *name)
219{ 195{
220 cfe_xiocb_t xiocb; 196 struct cfe_xiocb xiocb;
221 197
222 xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO; 198 xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO;
223 xiocb.xiocb_status = 0; 199 xiocb.xiocb_status = 0;
224 xiocb.xiocb_handle = 0; 200 xiocb.xiocb_handle = 0;
225 xiocb.xiocb_flags = 0; 201 xiocb.xiocb_flags = 0;
226 xiocb.xiocb_psize = sizeof(xiocb_buffer_t); 202 xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
227 xiocb.plist.xiocb_buffer.buf_offset = 0; 203 xiocb.plist.xiocb_buffer.buf_offset = 0;
228 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); 204 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
229 xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); 205 xiocb.plist.xiocb_buffer.buf_length = strlen(name);
230 206
231 cfe_iocb_dispatch(&xiocb); 207 cfe_iocb_dispatch(&xiocb);
232 208
233 if (xiocb.xiocb_status < 0) 209 if (xiocb.xiocb_status < 0)
234 return xiocb.xiocb_status; 210 return xiocb.xiocb_status;
235 return xiocb.plist.xiocb_buffer.buf_devflags; 211 return xiocb.plist.xiocb_buffer.buf_ioctlcmd;
236} 212}
237#endif /* CFE_API_getdevinfo || CFE_API_ALL */
238 213
239#if defined(CFE_API_getenv) || defined(CFE_API_ALL)
240int cfe_getenv(char *name, char *dest, int destlen) 214int cfe_getenv(char *name, char *dest, int destlen)
241{ 215{
242 cfe_xiocb_t xiocb; 216 struct cfe_xiocb xiocb;
243 217
244 *dest = 0; 218 *dest = 0;
245 219
@@ -247,10 +221,10 @@ int cfe_getenv(char *name, char *dest, int destlen)
247 xiocb.xiocb_status = 0; 221 xiocb.xiocb_status = 0;
248 xiocb.xiocb_handle = 0; 222 xiocb.xiocb_handle = 0;
249 xiocb.xiocb_flags = 0; 223 xiocb.xiocb_flags = 0;
250 xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); 224 xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
251 xiocb.plist.xiocb_envbuf.enum_idx = 0; 225 xiocb.plist.xiocb_envbuf.enum_idx = 0;
252 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); 226 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
253 xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); 227 xiocb.plist.xiocb_envbuf.name_length = strlen(name);
254 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest); 228 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest);
255 xiocb.plist.xiocb_envbuf.val_length = destlen; 229 xiocb.plist.xiocb_envbuf.val_length = destlen;
256 230
@@ -258,18 +232,16 @@ int cfe_getenv(char *name, char *dest, int destlen)
258 232
259 return xiocb.xiocb_status; 233 return xiocb.xiocb_status;
260} 234}
261#endif /* CFE_API_getenv || CFE_API_ALL */
262 235
263#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL)
264int cfe_getfwinfo(cfe_fwinfo_t * info) 236int cfe_getfwinfo(cfe_fwinfo_t * info)
265{ 237{
266 cfe_xiocb_t xiocb; 238 struct cfe_xiocb xiocb;
267 239
268 xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO; 240 xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO;
269 xiocb.xiocb_status = 0; 241 xiocb.xiocb_status = 0;
270 xiocb.xiocb_handle = 0; 242 xiocb.xiocb_handle = 0;
271 xiocb.xiocb_flags = 0; 243 xiocb.xiocb_flags = 0;
272 xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t); 244 xiocb.xiocb_psize = sizeof(struct xiocb_fwinfo);
273 245
274 cfe_iocb_dispatch(&xiocb); 246 cfe_iocb_dispatch(&xiocb);
275 247
@@ -292,12 +264,10 @@ int cfe_getfwinfo(cfe_fwinfo_t * info)
292 264
293 return 0; 265 return 0;
294} 266}
295#endif /* CFE_API_getfwinfo || CFE_API_ALL */
296 267
297#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL)
298int cfe_getstdhandle(int flg) 268int cfe_getstdhandle(int flg)
299{ 269{
300 cfe_xiocb_t xiocb; 270 struct cfe_xiocb xiocb;
301 271
302 xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE; 272 xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
303 xiocb.xiocb_status = 0; 273 xiocb.xiocb_status = 0;
@@ -311,23 +281,17 @@ int cfe_getstdhandle(int flg)
311 return xiocb.xiocb_status; 281 return xiocb.xiocb_status;
312 return xiocb.xiocb_handle; 282 return xiocb.xiocb_handle;
313} 283}
314#endif /* CFE_API_getstdhandle || CFE_API_ALL */
315 284
316#if defined(CFE_API_getticks) || defined(CFE_API_ALL)
317int64_t 285int64_t
318#ifdef CFE_API_IMPL_NAMESPACE
319__cfe_getticks(void)
320#else
321cfe_getticks(void) 286cfe_getticks(void)
322#endif
323{ 287{
324 cfe_xiocb_t xiocb; 288 struct cfe_xiocb xiocb;
325 289
326 xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME; 290 xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
327 xiocb.xiocb_status = 0; 291 xiocb.xiocb_status = 0;
328 xiocb.xiocb_handle = 0; 292 xiocb.xiocb_handle = 0;
329 xiocb.xiocb_flags = 0; 293 xiocb.xiocb_flags = 0;
330 xiocb.xiocb_psize = sizeof(xiocb_time_t); 294 xiocb.xiocb_psize = sizeof(struct xiocb_time);
331 xiocb.plist.xiocb_time.ticks = 0; 295 xiocb.plist.xiocb_time.ticks = 0;
332 296
333 cfe_iocb_dispatch(&xiocb); 297 cfe_iocb_dispatch(&xiocb);
@@ -335,18 +299,16 @@ cfe_getticks(void)
335 return xiocb.plist.xiocb_time.ticks; 299 return xiocb.plist.xiocb_time.ticks;
336 300
337} 301}
338#endif /* CFE_API_getticks || CFE_API_ALL */
339 302
340#if defined(CFE_API_inpstat) || defined(CFE_API_ALL)
341int cfe_inpstat(int handle) 303int cfe_inpstat(int handle)
342{ 304{
343 cfe_xiocb_t xiocb; 305 struct cfe_xiocb xiocb;
344 306
345 xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT; 307 xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
346 xiocb.xiocb_status = 0; 308 xiocb.xiocb_status = 0;
347 xiocb.xiocb_handle = handle; 309 xiocb.xiocb_handle = handle;
348 xiocb.xiocb_flags = 0; 310 xiocb.xiocb_flags = 0;
349 xiocb.xiocb_psize = sizeof(xiocb_inpstat_t); 311 xiocb.xiocb_psize = sizeof(struct xiocb_inpstat);
350 xiocb.plist.xiocb_inpstat.inp_status = 0; 312 xiocb.plist.xiocb_inpstat.inp_status = 0;
351 313
352 cfe_iocb_dispatch(&xiocb); 314 cfe_iocb_dispatch(&xiocb);
@@ -355,20 +317,18 @@ int cfe_inpstat(int handle)
355 return xiocb.xiocb_status; 317 return xiocb.xiocb_status;
356 return xiocb.plist.xiocb_inpstat.inp_status; 318 return xiocb.plist.xiocb_inpstat.inp_status;
357} 319}
358#endif /* CFE_API_inpstat || CFE_API_ALL */
359 320
360#if defined(CFE_API_ioctl) || defined(CFE_API_ALL)
361int 321int
362cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, 322cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
363 int length, int *retlen, cfe_xuint_t offset) 323 int length, int *retlen, u64 offset)
364{ 324{
365 cfe_xiocb_t xiocb; 325 struct cfe_xiocb xiocb;
366 326
367 xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL; 327 xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
368 xiocb.xiocb_status = 0; 328 xiocb.xiocb_status = 0;
369 xiocb.xiocb_handle = handle; 329 xiocb.xiocb_handle = handle;
370 xiocb.xiocb_flags = 0; 330 xiocb.xiocb_flags = 0;
371 xiocb.xiocb_psize = sizeof(xiocb_buffer_t); 331 xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
372 xiocb.plist.xiocb_buffer.buf_offset = offset; 332 xiocb.plist.xiocb_buffer.buf_offset = offset;
373 xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum; 333 xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum;
374 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); 334 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
@@ -380,21 +340,19 @@ cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
380 *retlen = xiocb.plist.xiocb_buffer.buf_retlen; 340 *retlen = xiocb.plist.xiocb_buffer.buf_retlen;
381 return xiocb.xiocb_status; 341 return xiocb.xiocb_status;
382} 342}
383#endif /* CFE_API_ioctl || CFE_API_ALL */
384 343
385#if defined(CFE_API_open) || defined(CFE_API_ALL)
386int cfe_open(char *name) 344int cfe_open(char *name)
387{ 345{
388 cfe_xiocb_t xiocb; 346 struct cfe_xiocb xiocb;
389 347
390 xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN; 348 xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
391 xiocb.xiocb_status = 0; 349 xiocb.xiocb_status = 0;
392 xiocb.xiocb_handle = 0; 350 xiocb.xiocb_handle = 0;
393 xiocb.xiocb_flags = 0; 351 xiocb.xiocb_flags = 0;
394 xiocb.xiocb_psize = sizeof(xiocb_buffer_t); 352 xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
395 xiocb.plist.xiocb_buffer.buf_offset = 0; 353 xiocb.plist.xiocb_buffer.buf_offset = 0;
396 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); 354 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
397 xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); 355 xiocb.plist.xiocb_buffer.buf_length = strlen(name);
398 356
399 cfe_iocb_dispatch(&xiocb); 357 cfe_iocb_dispatch(&xiocb);
400 358
@@ -402,27 +360,21 @@ int cfe_open(char *name)
402 return xiocb.xiocb_status; 360 return xiocb.xiocb_status;
403 return xiocb.xiocb_handle; 361 return xiocb.xiocb_handle;
404} 362}
405#endif /* CFE_API_open || CFE_API_ALL */
406 363
407#if defined(CFE_API_read) || defined(CFE_API_ALL)
408int cfe_read(int handle, unsigned char *buffer, int length) 364int cfe_read(int handle, unsigned char *buffer, int length)
409{ 365{
410 return cfe_readblk(handle, 0, buffer, length); 366 return cfe_readblk(handle, 0, buffer, length);
411} 367}
412#endif /* CFE_API_read || CFE_API_ALL */
413 368
414#if defined(CFE_API_readblk) || defined(CFE_API_ALL) 369int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
415int
416cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer,
417 int length)
418{ 370{
419 cfe_xiocb_t xiocb; 371 struct cfe_xiocb xiocb;
420 372
421 xiocb.xiocb_fcode = CFE_CMD_DEV_READ; 373 xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
422 xiocb.xiocb_status = 0; 374 xiocb.xiocb_status = 0;
423 xiocb.xiocb_handle = handle; 375 xiocb.xiocb_handle = handle;
424 xiocb.xiocb_flags = 0; 376 xiocb.xiocb_flags = 0;
425 xiocb.xiocb_psize = sizeof(xiocb_buffer_t); 377 xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
426 xiocb.plist.xiocb_buffer.buf_offset = offset; 378 xiocb.plist.xiocb_buffer.buf_offset = offset;
427 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); 379 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
428 xiocb.plist.xiocb_buffer.buf_length = length; 380 xiocb.plist.xiocb_buffer.buf_length = length;
@@ -433,62 +385,41 @@ cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer,
433 return xiocb.xiocb_status; 385 return xiocb.xiocb_status;
434 return xiocb.plist.xiocb_buffer.buf_retlen; 386 return xiocb.plist.xiocb_buffer.buf_retlen;
435} 387}
436#endif /* CFE_API_readblk || CFE_API_ALL */
437 388
438#if defined(CFE_API_setenv) || defined(CFE_API_ALL)
439int cfe_setenv(char *name, char *val) 389int cfe_setenv(char *name, char *val)
440{ 390{
441 cfe_xiocb_t xiocb; 391 struct cfe_xiocb xiocb;
442 392
443 xiocb.xiocb_fcode = CFE_CMD_ENV_SET; 393 xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
444 xiocb.xiocb_status = 0; 394 xiocb.xiocb_status = 0;
445 xiocb.xiocb_handle = 0; 395 xiocb.xiocb_handle = 0;
446 xiocb.xiocb_flags = 0; 396 xiocb.xiocb_flags = 0;
447 xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); 397 xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
448 xiocb.plist.xiocb_envbuf.enum_idx = 0; 398 xiocb.plist.xiocb_envbuf.enum_idx = 0;
449 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); 399 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
450 xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); 400 xiocb.plist.xiocb_envbuf.name_length = strlen(name);
451 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); 401 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
452 xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val); 402 xiocb.plist.xiocb_envbuf.val_length = strlen(val);
453 403
454 cfe_iocb_dispatch(&xiocb); 404 cfe_iocb_dispatch(&xiocb);
455 405
456 return xiocb.xiocb_status; 406 return xiocb.xiocb_status;
457} 407}
458#endif /* CFE_API_setenv || CFE_API_ALL */
459
460#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \
461 && !defined(CFE_API_STRLEN_CUSTOM)
462int cfe_strlen(char *name)
463{
464 int count = 0;
465
466 while (*name++)
467 count++;
468 408
469 return count;
470}
471#endif /* CFE_API_strlen || CFE_API_ALL */
472
473#if defined(CFE_API_write) || defined(CFE_API_ALL)
474int cfe_write(int handle, unsigned char *buffer, int length) 409int cfe_write(int handle, unsigned char *buffer, int length)
475{ 410{
476 return cfe_writeblk(handle, 0, buffer, length); 411 return cfe_writeblk(handle, 0, buffer, length);
477} 412}
478#endif /* CFE_API_write || CFE_API_ALL */
479 413
480#if defined(CFE_API_writeblk) || defined(CFE_API_ALL) 414int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
481int
482cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer,
483 int length)
484{ 415{
485 cfe_xiocb_t xiocb; 416 struct cfe_xiocb xiocb;
486 417
487 xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE; 418 xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
488 xiocb.xiocb_status = 0; 419 xiocb.xiocb_status = 0;
489 xiocb.xiocb_handle = handle; 420 xiocb.xiocb_handle = handle;
490 xiocb.xiocb_flags = 0; 421 xiocb.xiocb_flags = 0;
491 xiocb.xiocb_psize = sizeof(xiocb_buffer_t); 422 xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
492 xiocb.plist.xiocb_buffer.buf_offset = offset; 423 xiocb.plist.xiocb_buffer.buf_offset = offset;
493 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); 424 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
494 xiocb.plist.xiocb_buffer.buf_length = length; 425 xiocb.plist.xiocb_buffer.buf_length = length;
@@ -499,4 +430,3 @@ cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer,
499 return xiocb.xiocb_status; 430 return xiocb.xiocb_status;
500 return xiocb.plist.xiocb_buffer.buf_retlen; 431 return xiocb.plist.xiocb_buffer.buf_retlen;
501} 432}
502#endif /* CFE_API_writeblk || CFE_API_ALL */
diff --git a/arch/mips/fw/cfe/cfe_api_int.h b/arch/mips/fw/cfe/cfe_api_int.h
index f7e5a64b55f3..d9759e646956 100644
--- a/arch/mips/fw/cfe/cfe_api_int.h
+++ b/arch/mips/fw/cfe/cfe_api_int.h
@@ -15,28 +15,12 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Device function prototypes File: cfe_api_int.h
24 *
25 * This header defines all internal types and macros for the
26 * library. This is stuff that's not exported to an app
27 * using the library.
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#ifndef CFE_API_INT_H 18#ifndef CFE_API_INT_H
34#define CFE_API_INT_H 19#define CFE_API_INT_H
35 20
36/* ********************************************************************* 21/*
37 * Constants 22 * Constants.
38 ********************************************************************* */ 23 */
39
40#define CFE_CMD_FW_GETINFO 0 24#define CFE_CMD_FW_GETINFO 0
41#define CFE_CMD_FW_RESTART 1 25#define CFE_CMD_FW_RESTART 1
42#define CFE_CMD_FW_BOOT 2 26#define CFE_CMD_FW_BOOT 2
@@ -64,89 +48,101 @@
64 48
65#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ 49#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
66 50
67/* ********************************************************************* 51/*
68 * Structures 52 * Structures.
69 ********************************************************************* */ 53 */
70 54
71typedef uint64_t cfe_xuint_t; 55/* eeek, signed "pointers" */
72typedef int64_t cfe_xint_t; 56typedef s64 cfe_xptr_t;
73typedef int64_t cfe_xptr_t;
74 57
75typedef struct xiocb_buffer_s { 58struct xiocb_buffer {
76 cfe_xuint_t buf_offset; /* offset on device (bytes) */ 59 u64 buf_offset; /* offset on device (bytes) */
77 cfe_xptr_t buf_ptr; /* pointer to a buffer */ 60 cfe_xptr_t buf_ptr; /* pointer to a buffer */
78 cfe_xuint_t buf_length; /* length of this buffer */ 61 u64 buf_length; /* length of this buffer */
79 cfe_xuint_t buf_retlen; /* returned length (for read ops) */ 62 u64 buf_retlen; /* returned length (for read ops) */
80 cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ 63 u64 buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
81} xiocb_buffer_t; 64};
82
83#define buf_devflags buf_ioctlcmd /* returned device info flags */
84 65
85typedef struct xiocb_inpstat_s { 66struct xiocb_inpstat {
86 cfe_xuint_t inp_status; /* 1 means input available */ 67 u64 inp_status; /* 1 means input available */
87} xiocb_inpstat_t; 68};
88 69
89typedef struct xiocb_envbuf_s { 70struct xiocb_envbuf {
90 cfe_xint_t enum_idx; /* 0-based enumeration index */ 71 s64 enum_idx; /* 0-based enumeration index */
91 cfe_xptr_t name_ptr; /* name string buffer */ 72 cfe_xptr_t name_ptr; /* name string buffer */
92 cfe_xint_t name_length; /* size of name buffer */ 73 s64 name_length; /* size of name buffer */
93 cfe_xptr_t val_ptr; /* value string buffer */ 74 cfe_xptr_t val_ptr; /* value string buffer */
94 cfe_xint_t val_length; /* size of value string buffer */ 75 s64 val_length; /* size of value string buffer */
95} xiocb_envbuf_t; 76};
96 77
97typedef struct xiocb_cpuctl_s { 78struct xiocb_cpuctl {
98 cfe_xuint_t cpu_number; /* cpu number to control */ 79 u64 cpu_number; /* cpu number to control */
99 cfe_xuint_t cpu_command; /* command to issue to CPU */ 80 u64 cpu_command; /* command to issue to CPU */
100 cfe_xuint_t start_addr; /* CPU start address */ 81 u64 start_addr; /* CPU start address */
101 cfe_xuint_t gp_val; /* starting GP value */ 82 u64 gp_val; /* starting GP value */
102 cfe_xuint_t sp_val; /* starting SP value */ 83 u64 sp_val; /* starting SP value */
103 cfe_xuint_t a1_val; /* starting A1 value */ 84 u64 a1_val; /* starting A1 value */
104} xiocb_cpuctl_t; 85};
105 86
106typedef struct xiocb_time_s { 87struct xiocb_time {
107 cfe_xint_t ticks; /* current time in ticks */ 88 s64 ticks; /* current time in ticks */
108} xiocb_time_t; 89};
109 90
110typedef struct xiocb_exitstat_s { 91struct xiocb_exitstat{
111 cfe_xint_t status; 92 s64 status;
112} xiocb_exitstat_t; 93};
113 94
114typedef struct xiocb_meminfo_s { 95struct xiocb_meminfo {
115 cfe_xint_t mi_idx; /* 0-based enumeration index */ 96 s64 mi_idx; /* 0-based enumeration index */
116 cfe_xint_t mi_type; /* type of memory block */ 97 s64 mi_type; /* type of memory block */
117 cfe_xuint_t mi_addr; /* physical start address */ 98 u64 mi_addr; /* physical start address */
118 cfe_xuint_t mi_size; /* block size */ 99 u64 mi_size; /* block size */
119} xiocb_meminfo_t; 100};
120 101
121typedef struct xiocb_fwinfo_s { 102struct xiocb_fwinfo {
122 cfe_xint_t fwi_version; /* major, minor, eco version */ 103 s64 fwi_version; /* major, minor, eco version */
123 cfe_xint_t fwi_totalmem; /* total installed mem */ 104 s64 fwi_totalmem; /* total installed mem */
124 cfe_xint_t fwi_flags; /* various flags */ 105 s64 fwi_flags; /* various flags */
125 cfe_xint_t fwi_boardid; /* board ID */ 106 s64 fwi_boardid; /* board ID */
126 cfe_xint_t fwi_bootarea_va; /* VA of boot area */ 107 s64 fwi_bootarea_va; /* VA of boot area */
127 cfe_xint_t fwi_bootarea_pa; /* PA of boot area */ 108 s64 fwi_bootarea_pa; /* PA of boot area */
128 cfe_xint_t fwi_bootarea_size; /* size of boot area */ 109 s64 fwi_bootarea_size; /* size of boot area */
129 cfe_xint_t fwi_reserved1; 110 s64 fwi_reserved1;
130 cfe_xint_t fwi_reserved2; 111 s64 fwi_reserved2;
131 cfe_xint_t fwi_reserved3; 112 s64 fwi_reserved3;
132} xiocb_fwinfo_t; 113};
133 114
134typedef struct cfe_xiocb_s { 115struct cfe_xiocb {
135 cfe_xuint_t xiocb_fcode; /* IOCB function code */ 116 u64 xiocb_fcode; /* IOCB function code */
136 cfe_xint_t xiocb_status; /* return status */ 117 s64 xiocb_status; /* return status */
137 cfe_xint_t xiocb_handle; /* file/device handle */ 118 s64 xiocb_handle; /* file/device handle */
138 cfe_xuint_t xiocb_flags; /* flags for this IOCB */ 119 u64 xiocb_flags; /* flags for this IOCB */
139 cfe_xuint_t xiocb_psize; /* size of parameter list */ 120 u64 xiocb_psize; /* size of parameter list */
140 union { 121 union {
141 xiocb_buffer_t xiocb_buffer; /* buffer parameters */ 122 /* buffer parameters */
142 xiocb_inpstat_t xiocb_inpstat; /* input status parameters */ 123 struct xiocb_buffer xiocb_buffer;
143 xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */ 124
144 xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */ 125 /* input status parameters */
145 xiocb_time_t xiocb_time; /* timer parameters */ 126 struct xiocb_inpstat xiocb_inpstat;
146 xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */ 127
147 xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */ 128 /* environment function parameters */
148 xiocb_exitstat_t xiocb_exitstat; /* Exit Status */ 129 struct xiocb_envbuf xiocb_envbuf;
130
131 /* CPU control parameters */
132 struct xiocb_cpuctl xiocb_cpuctl;
133
134 /* timer parameters */
135 struct xiocb_time xiocb_time;
136
137 /* memory arena info parameters */
138 struct xiocb_meminfo xiocb_meminfo;
139
140 /* firmware information */
141 struct xiocb_fwinfo xiocb_fwinfo;
142
143 /* Exit Status */
144 struct xiocb_exitstat xiocb_exitstat;
149 } plist; 145 } plist;
150} cfe_xiocb_t; 146};
151 147
152#endif /* CFE_API_INT_H */ 148#endif /* CFE_API_INT_H */
diff --git a/arch/mips/fw/lib/Makefile b/arch/mips/fw/lib/Makefile
new file mode 100644
index 000000000000..84befc968fc4
--- /dev/null
+++ b/arch/mips/fw/lib/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for generic prom monitor library routines under Linux.
3#
4
5lib-$(CONFIG_64BIT) += call_o32.o
diff --git a/arch/mips/fw/lib/call_o32.S b/arch/mips/fw/lib/call_o32.S
new file mode 100644
index 000000000000..bdf7d1d4081a
--- /dev/null
+++ b/arch/mips/fw/lib/call_o32.S
@@ -0,0 +1,97 @@
1/*
2 * arch/mips/dec/prom/call_o32.S
3 *
4 * O32 interface for the 64 (or N32) ABI.
5 *
6 * Copyright (C) 2002 Maciej W. Rozycki
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#include <asm/asm.h>
15#include <asm/regdef.h>
16
17/* Maximum number of arguments supported. Must be even! */
18#define O32_ARGC 32
19/* Number of static registers we save. */
20#define O32_STATC 11
21/* Frame size for static register */
22#define O32_FRAMESZ (SZREG * O32_STATC)
23/* Frame size on new stack */
24#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC)
25
26 .text
27
28/*
29 * O32 function call dispatcher, for interfacing 32-bit ROM routines.
30 *
31 * The standard 64 (N32) calling sequence is supported, with a0
32 * holding a function pointer, a1 a new stack pointer, a2-a7 -- its
33 * first six arguments and the stack -- remaining ones (up to O32_ARGC,
34 * including a2-a7). Static registers, gp and fp are preserved, v0 holds
35 * a result. This code relies on the called o32 function for sp and ra
36 * restoration and this dispatcher has to be placed in a KSEGx (or KUSEG)
37 * address space. Any pointers passed have to point to addresses within
38 * one of these spaces as well.
39 */
40NESTED(call_o32, O32_FRAMESZ, ra)
41 REG_SUBU sp,O32_FRAMESZ
42
43 REG_S ra,O32_FRAMESZ-1*SZREG(sp)
44 REG_S fp,O32_FRAMESZ-2*SZREG(sp)
45 REG_S gp,O32_FRAMESZ-3*SZREG(sp)
46 REG_S s7,O32_FRAMESZ-4*SZREG(sp)
47 REG_S s6,O32_FRAMESZ-5*SZREG(sp)
48 REG_S s5,O32_FRAMESZ-6*SZREG(sp)
49 REG_S s4,O32_FRAMESZ-7*SZREG(sp)
50 REG_S s3,O32_FRAMESZ-8*SZREG(sp)
51 REG_S s2,O32_FRAMESZ-9*SZREG(sp)
52 REG_S s1,O32_FRAMESZ-10*SZREG(sp)
53 REG_S s0,O32_FRAMESZ-11*SZREG(sp)
54
55 move jp,a0
56 REG_SUBU s0,a1,O32_FRAMESZ_NEW
57 REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0)
58
59 sll a0,a2,zero
60 sll a1,a3,zero
61 sll a2,a4,zero
62 sll a3,a5,zero
63 sw a6,0x10(s0)
64 sw a7,0x14(s0)
65
66 PTR_LA t0,O32_FRAMESZ(sp)
67 PTR_LA t1,0x18(s0)
68 li t2,O32_ARGC-6
691:
70 lw t3,(t0)
71 REG_ADDU t0,SZREG
72 sw t3,(t1)
73 REG_SUBU t2,1
74 REG_ADDU t1,4
75 bnez t2,1b
76
77 move sp,s0
78
79 jalr jp
80
81 REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp)
82
83 REG_L s0,O32_FRAMESZ-11*SZREG(sp)
84 REG_L s1,O32_FRAMESZ-10*SZREG(sp)
85 REG_L s2,O32_FRAMESZ-9*SZREG(sp)
86 REG_L s3,O32_FRAMESZ-8*SZREG(sp)
87 REG_L s4,O32_FRAMESZ-7*SZREG(sp)
88 REG_L s5,O32_FRAMESZ-6*SZREG(sp)
89 REG_L s6,O32_FRAMESZ-5*SZREG(sp)
90 REG_L s7,O32_FRAMESZ-4*SZREG(sp)
91 REG_L gp,O32_FRAMESZ-3*SZREG(sp)
92 REG_L fp,O32_FRAMESZ-2*SZREG(sp)
93 REG_L ra,O32_FRAMESZ-1*SZREG(sp)
94
95 REG_ADDU sp,O32_FRAMESZ
96 jr ra
97END(call_o32)
diff --git a/arch/mips/fw/sni/Makefile b/arch/mips/fw/sni/Makefile
new file mode 100644
index 000000000000..d9740a3788e2
--- /dev/null
+++ b/arch/mips/fw/sni/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the SNI prom monitor routines under Linux.
3#
4
5lib-$(CONFIG_SNIPROM) += sniprom.o
diff --git a/arch/mips/fw/sni/sniprom.c b/arch/mips/fw/sni/sniprom.c
new file mode 100644
index 000000000000..96ba99202758
--- /dev/null
+++ b/arch/mips/fw/sni/sniprom.c
@@ -0,0 +1,151 @@
1/*
2 * Big Endian PROM code for SNI RM machines
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
9 * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/string.h>
15#include <linux/console.h>
16
17#include <asm/addrspace.h>
18#include <asm/sni.h>
19#include <asm/mipsprom.h>
20#include <asm/mipsregs.h>
21#include <asm/bootinfo.h>
22
23/* special SNI prom calls */
24/*
25 * This does not exist in all proms - SINIX compares
26 * the prom env variable "version" against "2.0008"
27 * or greater. If lesser it tries to probe interesting
28 * registers
29 */
30#define PROM_GET_MEMCONF 58
31#define PROM_GET_HWCONF 61
32
33#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
34#define PROM_ENTRY(x) (PROM_VEC + (x))
35
36#define ___prom_putchar ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR))
37#define ___prom_getenv ((char *(*)(char *))PROM_ENTRY(PROM_GETENV))
38#define ___prom_get_memconf ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF))
39#define ___prom_get_hwconf ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF))
40
41#ifdef CONFIG_64BIT
42
43static u8 o32_stk[16384];
44#define O32_STK &o32_stk[sizeof(o32_stk)]
45
46#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
47 __asm__(#fun " = call_o32")
48
49int __PROM_O32(__prom_putchar, (int *(*)(int), void *, int));
50char *__PROM_O32(__prom_getenv, (char *(*)(char *), void *, char *));
51void __PROM_O32(__prom_get_memconf, (void (*)(void *), void *, void *));
52u32 __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *));
53
54#define _prom_putchar(x) __prom_putchar(___prom_putchar, O32_STK, x)
55#define _prom_getenv(x) __prom_getenv(___prom_getenv, O32_STK, x)
56#define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x)
57#define _prom_get_hwconf() __prom_get_hwconf(___prom_get_hwconf, O32_STK)
58
59#else
60#define _prom_putchar(x) ___prom_putchar(x)
61#define _prom_getenv(x) ___prom_getenv(x)
62#define _prom_get_memconf(x) ___prom_get_memconf(x)
63#define _prom_get_hwconf(x) ___prom_get_hwconf(x)
64#endif
65
66void prom_putchar(char c)
67{
68 _prom_putchar(c);
69}
70
71
72char *prom_getenv(char *s)
73{
74 return _prom_getenv(s);
75}
76
77void *prom_get_hwconf(void)
78{
79 u32 hwconf = _prom_get_hwconf();
80
81 if (hwconf == 0xffffffff)
82 return NULL;
83
84 return (void *)CKSEG1ADDR(hwconf);
85}
86
87void __init prom_free_prom_memory(void)
88{
89}
90
91/*
92 * /proc/cpuinfo system type
93 *
94 */
95char *system_type = "Unknown";
96const char *get_system_type(void)
97{
98 return system_type;
99}
100
101static void __init sni_mem_init(void)
102{
103 int i, memsize;
104 struct membank {
105 u32 size;
106 u32 base;
107 u32 size2;
108 u32 pad1;
109 u32 pad2;
110 } memconf[8];
111 int brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
112
113
114 /* MemSIZE from prom in 16MByte chunks */
115 memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
116
117 pr_debug("IDProm memsize: %u MByte\n", memsize);
118
119 /* get memory bank layout from prom */
120 _prom_get_memconf(&memconf);
121
122 pr_debug("prom_get_mem_conf memory configuration:\n");
123 for (i = 0; i < 8 && memconf[i].size; i++) {
124 if (brd_type == SNI_BRD_PCI_TOWER ||
125 brd_type == SNI_BRD_PCI_TOWER_CPLUS) {
126 if (memconf[i].base >= 0x20000000 &&
127 memconf[i].base < 0x30000000)
128 memconf[i].base -= 0x20000000;
129 }
130 pr_debug("Bank%d: %08x @ %08x\n", i,
131 memconf[i].size, memconf[i].base);
132 add_memory_region(memconf[i].base, memconf[i].size,
133 BOOT_MEM_RAM);
134 }
135}
136
137void __init prom_init(void)
138{
139 int argc = fw_arg0;
140 u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1);
141 int i;
142
143 sni_mem_init();
144
145 /* copy prom cmdline parameters to kernel cmdline */
146 for (i = 1; i < argc; i++) {
147 strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i]));
148 if (i < (argc - 1))
149 strcat(arcs_cmdline, " ");
150 }
151}
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index 51f6b7862460..728ef6a80edd 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -121,8 +121,6 @@ const char *get_system_type(void)
121 */ 121 */
122void __init prom_init(void) 122void __init prom_init(void)
123{ 123{
124 mips_machtype = MACH_WRPPMC;
125
126 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); 124 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
127 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); 125 add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA);
128 126
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index a7857973ca03..a7947199c99b 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -200,12 +200,19 @@ static struct platform_device jazz_cmos_pdev = {
200 .resource = jazz_cmos_rsrc 200 .resource = jazz_cmos_rsrc
201}; 201};
202 202
203static struct platform_device pcspeaker_pdev = {
204 .name = "pcspkr",
205 .id = -1,
206};
207
203static int __init jazz_setup_devinit(void) 208static int __init jazz_setup_devinit(void)
204{ 209{
205 platform_device_register(&jazz_serial8250_device); 210 platform_device_register(&jazz_serial8250_device);
206 platform_device_register(&jazz_esp_pdev); 211 platform_device_register(&jazz_esp_pdev);
207 platform_device_register(&jazz_sonic_pdev); 212 platform_device_register(&jazz_sonic_pdev);
208 platform_device_register(&jazz_cmos_pdev); 213 platform_device_register(&jazz_cmos_pdev);
214 platform_device_register(&pcspeaker_pdev);
215
209 return 0; 216 return 0;
210} 217}
211 218
diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c
index b643f75ec9a5..700b9cf8eb9d 100644
--- a/arch/mips/jmr3927/rbhma3100/init.c
+++ b/arch/mips/jmr3927/rbhma3100/init.c
@@ -52,10 +52,6 @@ void __init prom_init(void)
52 puts("Warning: TX3927 TLB off\n"); 52 puts("Warning: TX3927 TLB off\n");
53#endif 53#endif
54 54
55#ifdef CONFIG_TOSHIBA_JMR3927
56 mips_machtype = MACH_TOSHIBA_JMR3927;
57#endif
58
59 prom_init_cmdline(); 55 prom_init_cmdline();
60 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); 56 add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
61} 57}
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 06e01c8f4e3a..c886d804d303 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -29,21 +29,17 @@
29 29
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/kdev_t.h>
33#include <linux/types.h> 32#include <linux/types.h>
34#include <linux/pci.h> 33#include <linux/pci.h>
35#include <linux/ide.h>
36#include <linux/ioport.h> 34#include <linux/ioport.h>
37#include <linux/delay.h> 35#include <linux/delay.h>
38#include <linux/pm.h> 36#include <linux/pm.h>
39#include <linux/platform_device.h> 37#include <linux/platform_device.h>
38#include <linux/clk.h>
40#ifdef CONFIG_SERIAL_TXX9 39#ifdef CONFIG_SERIAL_TXX9
41#include <linux/tty.h>
42#include <linux/serial.h>
43#include <linux/serial_core.h> 40#include <linux/serial_core.h>
44#endif 41#endif
45 42
46#include <asm/addrspace.h>
47#include <asm/txx9tmr.h> 43#include <asm/txx9tmr.h>
48#include <asm/reboot.h> 44#include <asm/reboot.h>
49#include <asm/jmr3927/jmr3927.h> 45#include <asm/jmr3927/jmr3927.h>
@@ -238,6 +234,8 @@ static void __init tx3927_setup(void)
238 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; 234 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
239 /* Disable PCI snoop */ 235 /* Disable PCI snoop */
240 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; 236 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
237 /* do reset on watchdog */
238 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
241 239
242#ifdef DO_WRITE_THROUGH 240#ifdef DO_WRITE_THROUGH
243 /* Enable PCI SNOOP - with write through only */ 241 /* Enable PCI SNOOP - with write through only */
@@ -388,3 +386,55 @@ static int __init jmr3927_rtc_init(void)
388 return IS_ERR(dev) ? PTR_ERR(dev) : 0; 386 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
389} 387}
390device_initcall(jmr3927_rtc_init); 388device_initcall(jmr3927_rtc_init);
389
390/* Watchdog support */
391
392static int __init txx9_wdt_init(unsigned long base)
393{
394 struct resource res = {
395 .start = base,
396 .end = base + 0x100 - 1,
397 .flags = IORESOURCE_MEM,
398 };
399 struct platform_device *dev =
400 platform_device_register_simple("txx9wdt", -1, &res, 1);
401 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
402}
403
404static int __init jmr3927_wdt_init(void)
405{
406 return txx9_wdt_init(TX3927_TMR_REG(2));
407}
408device_initcall(jmr3927_wdt_init);
409
410/* Minimum CLK support */
411
412struct clk *clk_get(struct device *dev, const char *id)
413{
414 if (!strcmp(id, "imbus_clk"))
415 return (struct clk *)JMR3927_IMCLK;
416 return ERR_PTR(-ENOENT);
417}
418EXPORT_SYMBOL(clk_get);
419
420int clk_enable(struct clk *clk)
421{
422 return 0;
423}
424EXPORT_SYMBOL(clk_enable);
425
426void clk_disable(struct clk *clk)
427{
428}
429EXPORT_SYMBOL(clk_disable);
430
431unsigned long clk_get_rate(struct clk *clk)
432{
433 return (unsigned long)clk;
434}
435EXPORT_SYMBOL(clk_get_rate);
436
437void clk_put(struct clk *clk)
438{
439}
440EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index af78456d4138..417bb3e336ac 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -18,6 +18,15 @@
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/system.h> 19#include <asm/system.h>
20 20
21static char bug64hit[] __initdata =
22 "reliable operation impossible!\n%s";
23static char nowar[] __initdata =
24 "Please report to <linux-mips@linux-mips.org>.";
25static char r4kwar[] __initdata =
26 "Enable CPU_R4000_WORKAROUNDS to rectify.";
27static char daddiwar[] __initdata =
28 "Enable CPU_DADDI_WORKAROUNDS to rectify.";
29
21static inline void align_mod(const int align, const int mod) 30static inline void align_mod(const int align, const int mod)
22{ 31{
23 asm volatile( 32 asm volatile(
@@ -155,13 +164,7 @@ static inline void check_mult_sh(void)
155 } 164 }
156 165
157 printk("no.\n"); 166 printk("no.\n");
158 panic("Reliable operation impossible!\n" 167 panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
159#ifndef CONFIG_CPU_R4000
160 "Configure for R4000 to enable the workaround."
161#else
162 "Please report to <linux-mips@linux-mips.org>."
163#endif
164 );
165} 168}
166 169
167static volatile int daddi_ov __initdata = 0; 170static volatile int daddi_ov __initdata = 0;
@@ -233,15 +236,11 @@ static inline void check_daddi(void)
233 } 236 }
234 237
235 printk("no.\n"); 238 printk("no.\n");
236 panic("Reliable operation impossible!\n" 239 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
237#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
238 "Configure for R4000 or R4400 to enable the workaround."
239#else
240 "Please report to <linux-mips@linux-mips.org>."
241#endif
242 );
243} 240}
244 241
242int daddiu_bug __initdata = -1;
243
245static inline void check_daddiu(void) 244static inline void check_daddiu(void)
246{ 245{
247 long v, w, tmp; 246 long v, w, tmp;
@@ -281,7 +280,9 @@ static inline void check_daddiu(void)
281 : "=&r" (v), "=&r" (w), "=&r" (tmp) 280 : "=&r" (v), "=&r" (w), "=&r" (tmp)
282 : "I" (0xffffffffffffdb9aUL), "I" (0x1234)); 281 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
283 282
284 if (v == w) { 283 daddiu_bug = v != w;
284
285 if (!daddiu_bug) {
285 printk("no.\n"); 286 printk("no.\n");
286 return; 287 return;
287 } 288 }
@@ -303,18 +304,16 @@ static inline void check_daddiu(void)
303 } 304 }
304 305
305 printk("no.\n"); 306 printk("no.\n");
306 panic("Reliable operation impossible!\n" 307 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
307#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
308 "Configure for R4000 or R4400 to enable the workaround."
309#else
310 "Please report to <linux-mips@linux-mips.org>."
311#endif
312 );
313} 308}
314 309
315void __init check_bugs64(void) 310void __init check_bugs64_early(void)
316{ 311{
317 check_mult_sh(); 312 check_mult_sh();
318 check_daddi();
319 check_daddiu(); 313 check_daddiu();
320} 314}
315
316void __init check_bugs64(void)
317{
318 check_daddi();
319}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5c2794391bf5..5861a432a52f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -188,6 +188,8 @@ static inline void check_wait(void)
188 case CPU_AU1500: 188 case CPU_AU1500:
189 case CPU_AU1550: 189 case CPU_AU1550:
190 case CPU_AU1200: 190 case CPU_AU1200:
191 case CPU_AU1210:
192 case CPU_AU1250:
191 if (allow_au1k_wait) 193 if (allow_au1k_wait)
192 cpu_wait = au1k_wait; 194 cpu_wait = au1k_wait;
193 break; 195 break;
@@ -733,6 +735,11 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
733 break; 735 break;
734 case 4: 736 case 4:
735 c->cputype = CPU_AU1200; 737 c->cputype = CPU_AU1200;
738 if (2 == (c->processor_id & 0xff))
739 c->cputype = CPU_AU1250;
740 break;
741 case 5:
742 c->cputype = CPU_AU1210;
736 break; 743 break;
737 default: 744 default:
738 panic("Unknown Au Core!"); 745 panic("Unknown Au Core!");
@@ -858,6 +865,8 @@ static __init const char *cpu_to_name(struct cpuinfo_mips *c)
858 case CPU_AU1100: name = "Au1100"; break; 865 case CPU_AU1100: name = "Au1100"; break;
859 case CPU_AU1550: name = "Au1550"; break; 866 case CPU_AU1550: name = "Au1550"; break;
860 case CPU_AU1200: name = "Au1200"; break; 867 case CPU_AU1200: name = "Au1200"; break;
868 case CPU_AU1210: name = "Au1210"; break;
869 case CPU_AU1250: name = "Au1250"; break;
861 case CPU_4KEC: name = "MIPS 4KEc"; break; 870 case CPU_4KEC: name = "MIPS 4KEc"; break;
862 case CPU_4KSC: name = "MIPS 4KSc"; break; 871 case CPU_4KSC: name = "MIPS 4KSc"; break;
863 case CPU_VR41XX: name = "NEC Vr41xx"; break; 872 case CPU_VR41XX: name = "NEC Vr41xx"; break;
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index e76a76bf0b3d..c6ada98ee042 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -6,7 +6,7 @@
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle 6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc. 8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki 9 * Copyright (C) 2002, 2007 Maciej W. Rozycki
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12 12
@@ -471,7 +471,13 @@ NESTED(nmi_handler, PT_SIZE, sp)
471 jr k0 471 jr k0
472 rfe 472 rfe
473#else 473#else
474#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
474 LONG_ADDIU k0, 4 /* stall on $k0 */ 475 LONG_ADDIU k0, 4 /* stall on $k0 */
476#else
477 .set at=v1
478 LONG_ADDIU k0, 4
479 .set noat
480#endif
475 MTC0 k0, CP0_EPC 481 MTC0 k0, CP0_EPC
476 /* I hope three instructions between MTC0 and ERET are enough... */ 482 /* I hope three instructions between MTC0 and ERET are enough... */
477 ori k1, _THREAD_MASK 483 ori k1, _THREAD_MASK
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index d2c2e00e5864..f6704ab16306 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -161,8 +161,7 @@ static unsigned int translate_open_flags(int flags)
161 int i; 161 int i;
162 unsigned int ret = 0; 162 unsigned int ret = 0;
163 163
164 for (i = 0; i < (sizeof(open_flags_table) / sizeof(struct apsp_table)); 164 for (i = 0; i < ARRAY_SIZE(open_flags_table); i++) {
165 i++) {
166 if( (flags & open_flags_table[i].sp) ) { 165 if( (flags & open_flags_table[i].sp) ) {
167 ret |= open_flags_table[i].ap; 166 ret |= open_flags_table[i].ap;
168 } 167 }
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 2b8ec1102e86..65af3cc90abb 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -174,36 +174,16 @@ struct rlimit32 {
174 int rlim_max; 174 int rlim_max;
175}; 175};
176 176
177#ifdef __MIPSEB__ 177asmlinkage long sys32_truncate64(const char __user * path,
178asmlinkage long sys32_truncate64(const char __user * path, unsigned long __dummy, 178 unsigned long __dummy, int a2, int a3)
179 int length_hi, int length_lo)
180#endif
181#ifdef __MIPSEL__
182asmlinkage long sys32_truncate64(const char __user * path, unsigned long __dummy,
183 int length_lo, int length_hi)
184#endif
185{ 179{
186 loff_t length; 180 return sys_truncate(path, merge_64(a2, a3));
187
188 length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo;
189
190 return sys_truncate(path, length);
191} 181}
192 182
193#ifdef __MIPSEB__
194asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy, 183asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy,
195 int length_hi, int length_lo) 184 int a2, int a3)
196#endif
197#ifdef __MIPSEL__
198asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy,
199 int length_lo, int length_hi)
200#endif
201{ 185{
202 loff_t length; 186 return sys_ftruncate(fd, merge_64(a2, a3));
203
204 length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo;
205
206 return sys_ftruncate(fd, length);
207} 187}
208 188
209static inline long 189static inline long
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index 3d6b1ec1f328..640fb0cc6e39 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -17,7 +17,6 @@
17#include <asm/system.h> 17#include <asm/system.h>
18#include <asm/hardirq.h> 18#include <asm/hardirq.h>
19#include <asm/mmu_context.h> 19#include <asm/mmu_context.h>
20#include <asm/smp.h>
21#include <asm/mipsmtregs.h> 20#include <asm/mipsmtregs.h>
22#include <asm/r4kcache.h> 21#include <asm/r4kcache.h>
23#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
diff --git a/arch/mips/kernel/pcspeaker.c b/arch/mips/kernel/pcspeaker.c
deleted file mode 100644
index 475df6904219..000000000000
--- a/arch/mips/kernel/pcspeaker.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) 2006 IBM Corporation
3 *
4 * Implements device information for i8253 timer chip
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation
9 */
10
11#include <linux/platform_device.h>
12
13static __init int add_pcspkr(void)
14{
15 struct platform_device *pd;
16 int ret;
17
18 pd = platform_device_alloc("pcspkr", -1);
19 if (!pd)
20 return -ENOMEM;
21
22 ret = platform_device_add(pd);
23 if (ret)
24 platform_device_put(pd);
25
26 return ret;
27}
28device_initcall(add_pcspkr);
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 6e6e947cce1e..36f065398243 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -62,6 +62,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
62 ); 62 );
63 seq_printf(m, "shadow register sets\t: %d\n", 63 seq_printf(m, "shadow register sets\t: %d\n",
64 cpu_data[n].srsets); 64 cpu_data[n].srsets);
65 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
65 66
66 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 67 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
67 cpu_has_vce ? "%u" : "not available"); 68 cpu_has_vce ? "%u" : "not available");
@@ -89,7 +90,7 @@ static void c_stop(struct seq_file *m, void *v)
89{ 90{
90} 91}
91 92
92struct seq_operations cpuinfo_op = { 93const struct seq_operations cpuinfo_op = {
93 .start = c_start, 94 .start = c_start,
94 .next = c_next, 95 .next = c_next,
95 .stop = c_stop, 96 .stop = c_stop,
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 1ba00c15505b..0233798f7155 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -40,7 +40,6 @@
40#include <asm/atomic.h> 40#include <asm/atomic.h>
41#include <asm/cpu.h> 41#include <asm/cpu.h>
42#include <asm/processor.h> 42#include <asm/processor.h>
43#include <asm/mips_mt.h>
44#include <asm/system.h> 43#include <asm/system.h>
45#include <asm/vpe.h> 44#include <asm/vpe.h>
46#include <asm/rtlx.h> 45#include <asm/rtlx.h>
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index f8a535afce39..269c252d956f 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -8,7 +8,7 @@
8 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle 8 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle
9 * Copyright (C) 1996 Stoned Elipot 9 * Copyright (C) 1996 Stoned Elipot
10 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 * Copyright (C) 2000 2001, 2002 Maciej W. Rozycki 11 * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h> 14#include <linux/ioport.h>
@@ -24,10 +24,12 @@
24 24
25#include <asm/addrspace.h> 25#include <asm/addrspace.h>
26#include <asm/bootinfo.h> 26#include <asm/bootinfo.h>
27#include <asm/bugs.h>
27#include <asm/cache.h> 28#include <asm/cache.h>
28#include <asm/cpu.h> 29#include <asm/cpu.h>
29#include <asm/sections.h> 30#include <asm/sections.h>
30#include <asm/setup.h> 31#include <asm/setup.h>
32#include <asm/smp-ops.h>
31#include <asm/system.h> 33#include <asm/system.h>
32 34
33struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; 35struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;
@@ -561,6 +563,7 @@ void __init setup_arch(char **cmdline_p)
561 } 563 }
562#endif 564#endif
563 cpu_report(); 565 cpu_report();
566 check_bugs_early();
564 567
565#if defined(CONFIG_VT) 568#if defined(CONFIG_VT)
566#if defined(CONFIG_VGA_CONSOLE) 569#if defined(CONFIG_VGA_CONSOLE)
@@ -573,9 +576,7 @@ void __init setup_arch(char **cmdline_p)
573 arch_mem_init(cmdline_p); 576 arch_mem_init(cmdline_p);
574 577
575 resource_init(); 578 resource_init();
576#ifdef CONFIG_SMP
577 plat_smp_setup(); 579 plat_smp_setup();
578#endif
579} 580}
580 581
581static int __init fpu_disable(char *s) 582static int __init fpu_disable(char *s)
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 94e210cc6cb6..89e6f6aa5166 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -22,6 +22,7 @@
22#include <linux/cpumask.h> 22#include <linux/cpumask.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/compiler.h> 24#include <linux/compiler.h>
25#include <linux/smp.h>
25 26
26#include <asm/atomic.h> 27#include <asm/atomic.h>
27#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
@@ -30,7 +31,6 @@
30#include <asm/system.h> 31#include <asm/system.h>
31#include <asm/hardirq.h> 32#include <asm/hardirq.h>
32#include <asm/mmu_context.h> 33#include <asm/mmu_context.h>
33#include <asm/smp.h>
34#include <asm/time.h> 34#include <asm/time.h>
35#include <asm/mipsregs.h> 35#include <asm/mipsregs.h>
36#include <asm/mipsmtregs.h> 36#include <asm/mipsmtregs.h>
@@ -215,68 +215,67 @@ static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
215 write_tc_c0_tchalt(TCHALT_H); 215 write_tc_c0_tchalt(TCHALT_H);
216} 216}
217 217
218/* 218static void vsmp_send_ipi_single(int cpu, unsigned int action)
219 * Common setup before any secondaries are started
220 * Make sure all CPU's are in a sensible state before we boot any of the
221 * secondarys
222 */
223void __init plat_smp_setup(void)
224{ 219{
225 unsigned int mvpconf0, ntc, tc, ncpu = 0; 220 int i;
226 221 unsigned long flags;
227#ifdef CONFIG_MIPS_MT_FPAFF 222 int vpflags;
228 /* If we have an FPU, enroll ourselves in the FPU-full mask */
229 if (cpu_has_fpu)
230 cpu_set(0, mt_fpu_cpumask);
231#endif /* CONFIG_MIPS_MT_FPAFF */
232 if (!cpu_has_mipsmt)
233 return;
234
235 /* disable MT so we can configure */
236 dvpe();
237 dmt();
238 223
239 /* Put MVPE's into 'configuration state' */ 224 local_irq_save(flags);
240 set_c0_mvpcontrol(MVPCONTROL_VPC);
241 225
242 mvpconf0 = read_c0_mvpconf0(); 226 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
243 ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
244 227
245 /* we'll always have more TC's than VPE's, so loop setting everything 228 switch (action) {
246 to a sensible state */ 229 case SMP_CALL_FUNCTION:
247 for (tc = 0; tc <= ntc; tc++) { 230 i = C_SW1;
248 settc(tc); 231 break;
249 232
250 smp_tc_init(tc, mvpconf0); 233 case SMP_RESCHEDULE_YOURSELF:
251 ncpu = smp_vpe_init(tc, mvpconf0, ncpu); 234 default:
235 i = C_SW0;
236 break;
252 } 237 }
253 238
254 /* Release config state */ 239 /* 1:1 mapping of vpe and tc... */
255 clear_c0_mvpcontrol(MVPCONTROL_VPC); 240 settc(cpu);
241 write_vpe_c0_cause(read_vpe_c0_cause() | i);
242 evpe(vpflags);
256 243
257 /* We'll wait until starting the secondaries before starting MVPE */ 244 local_irq_restore(flags);
245}
258 246
259 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); 247static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action)
248{
249 unsigned int i;
250
251 for_each_cpu_mask(i, mask)
252 vsmp_send_ipi_single(i, action);
260} 253}
261 254
262void __init plat_prepare_cpus(unsigned int max_cpus) 255static void __cpuinit vsmp_init_secondary(void)
263{ 256{
264 mips_mt_set_cpuoptions(); 257 /* Enable per-cpu interrupts */
265 258
266 /* set up ipi interrupts */ 259 /* This is Malta specific: IPI,performance and timer inetrrupts */
267 if (cpu_has_vint) { 260 write_c0_status((read_c0_status() & ~ST0_IM ) |
268 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 261 (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
269 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 262}
270 }
271 263
272 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 264static void __cpuinit vsmp_smp_finish(void)
273 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 265{
266 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
274 267
275 setup_irq(cpu_ipi_resched_irq, &irq_resched); 268#ifdef CONFIG_MIPS_MT_FPAFF
276 setup_irq(cpu_ipi_call_irq, &irq_call); 269 /* If we have an FPU, enroll ourselves in the FPU-full mask */
270 if (cpu_has_fpu)
271 cpu_set(smp_processor_id(), mt_fpu_cpumask);
272#endif /* CONFIG_MIPS_MT_FPAFF */
277 273
278 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); 274 local_irq_enable();
279 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); 275}
276
277static void vsmp_cpus_done(void)
278{
280} 279}
281 280
282/* 281/*
@@ -287,7 +286,7 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
287 * (unsigned long)idle->thread_info the gp 286 * (unsigned long)idle->thread_info the gp
288 * assumes a 1:1 mapping of TC => VPE 287 * assumes a 1:1 mapping of TC => VPE
289 */ 288 */
290void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) 289static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
291{ 290{
292 struct thread_info *gp = task_thread_info(idle); 291 struct thread_info *gp = task_thread_info(idle);
293 dvpe(); 292 dvpe();
@@ -321,57 +320,81 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
321 evpe(EVPE_ENABLE); 320 evpe(EVPE_ENABLE);
322} 321}
323 322
324void __cpuinit prom_init_secondary(void) 323/*
325{ 324 * Common setup before any secondaries are started
326 /* Enable per-cpu interrupts */ 325 * Make sure all CPU's are in a sensible state before we boot any of the
327 326 * secondarys
328 /* This is Malta specific: IPI,performance and timer inetrrupts */ 327 */
329 write_c0_status((read_c0_status() & ~ST0_IM ) | 328static void __init vsmp_smp_setup(void)
330 (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
331}
332
333void __cpuinit prom_smp_finish(void)
334{ 329{
335 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); 330 unsigned int mvpconf0, ntc, tc, ncpu = 0;
331 unsigned int nvpe;
336 332
337#ifdef CONFIG_MIPS_MT_FPAFF 333#ifdef CONFIG_MIPS_MT_FPAFF
338 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 334 /* If we have an FPU, enroll ourselves in the FPU-full mask */
339 if (cpu_has_fpu) 335 if (cpu_has_fpu)
340 cpu_set(smp_processor_id(), mt_fpu_cpumask); 336 cpu_set(0, mt_fpu_cpumask);
341#endif /* CONFIG_MIPS_MT_FPAFF */ 337#endif /* CONFIG_MIPS_MT_FPAFF */
338 if (!cpu_has_mipsmt)
339 return;
342 340
343 local_irq_enable(); 341 /* disable MT so we can configure */
344} 342 dvpe();
343 dmt();
345 344
346void prom_cpus_done(void) 345 /* Put MVPE's into 'configuration state' */
347{ 346 set_c0_mvpcontrol(MVPCONTROL_VPC);
348}
349 347
350void core_send_ipi(int cpu, unsigned int action) 348 mvpconf0 = read_c0_mvpconf0();
351{ 349 ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
352 int i;
353 unsigned long flags;
354 int vpflags;
355 350
356 local_irq_save(flags); 351 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
352 smp_num_siblings = nvpe;
357 353
358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ 354 /* we'll always have more TC's than VPE's, so loop setting everything
355 to a sensible state */
356 for (tc = 0; tc <= ntc; tc++) {
357 settc(tc);
359 358
360 switch (action) { 359 smp_tc_init(tc, mvpconf0);
361 case SMP_CALL_FUNCTION: 360 ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
362 i = C_SW1; 361 }
363 break;
364 362
365 case SMP_RESCHEDULE_YOURSELF: 363 /* Release config state */
366 default: 364 clear_c0_mvpcontrol(MVPCONTROL_VPC);
367 i = C_SW0; 365
368 break; 366 /* We'll wait until starting the secondaries before starting MVPE */
367
368 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
369}
370
371static void __init vsmp_prepare_cpus(unsigned int max_cpus)
372{
373 mips_mt_set_cpuoptions();
374
375 /* set up ipi interrupts */
376 if (cpu_has_vint) {
377 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
378 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
369 } 379 }
370 380
371 /* 1:1 mapping of vpe and tc... */ 381 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
372 settc(cpu); 382 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
373 write_vpe_c0_cause(read_vpe_c0_cause() | i);
374 evpe(vpflags);
375 383
376 local_irq_restore(flags); 384 setup_irq(cpu_ipi_resched_irq, &irq_resched);
385 setup_irq(cpu_ipi_call_irq, &irq_call);
386
387 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
388 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
377} 389}
390
391struct plat_smp_ops vsmp_smp_ops = {
392 .send_ipi_single = vsmp_send_ipi_single,
393 .send_ipi_mask = vsmp_send_ipi_mask,
394 .init_secondary = vsmp_init_secondary,
395 .smp_finish = vsmp_smp_finish,
396 .cpus_done = vsmp_cpus_done,
397 .boot_secondary = vsmp_boot_secondary,
398 .smp_setup = vsmp_smp_setup,
399 .prepare_cpus = vsmp_prepare_cpus,
400};
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 63989e9df4f9..1e5dfc28294a 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -37,7 +37,6 @@
37#include <asm/processor.h> 37#include <asm/processor.h>
38#include <asm/system.h> 38#include <asm/system.h>
39#include <asm/mmu_context.h> 39#include <asm/mmu_context.h>
40#include <asm/smp.h>
41#include <asm/time.h> 40#include <asm/time.h>
42 41
43#ifdef CONFIG_MIPS_MT_SMTC 42#ifdef CONFIG_MIPS_MT_SMTC
@@ -56,6 +55,44 @@ EXPORT_SYMBOL(cpu_online_map);
56extern void __init calibrate_delay(void); 55extern void __init calibrate_delay(void);
57extern void cpu_idle(void); 56extern void cpu_idle(void);
58 57
58/* Number of TCs (or siblings in Intel speak) per CPU core */
59int smp_num_siblings = 1;
60EXPORT_SYMBOL(smp_num_siblings);
61
62/* representing the TCs (or siblings in Intel speak) of each logical CPU */
63cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
64EXPORT_SYMBOL(cpu_sibling_map);
65
66/* representing cpus for which sibling maps can be computed */
67static cpumask_t cpu_sibling_setup_map;
68
69static inline void set_cpu_sibling_map(int cpu)
70{
71 int i;
72
73 cpu_set(cpu, cpu_sibling_setup_map);
74
75 if (smp_num_siblings > 1) {
76 for_each_cpu_mask(i, cpu_sibling_setup_map) {
77 if (cpu_data[cpu].core == cpu_data[i].core) {
78 cpu_set(i, cpu_sibling_map[cpu]);
79 cpu_set(cpu, cpu_sibling_map[i]);
80 }
81 }
82 } else
83 cpu_set(cpu, cpu_sibling_map[cpu]);
84}
85
86struct plat_smp_ops *mp_ops;
87
88__cpuinit void register_smp_ops(struct plat_smp_ops *ops)
89{
90 if (ops)
91 printk(KERN_WARNING "Overriding previous set SMP ops\n");
92
93 mp_ops = ops;
94}
95
59/* 96/*
60 * First C code run on the secondary CPUs after being started up by 97 * First C code run on the secondary CPUs after being started up by
61 * the master. 98 * the master.
@@ -72,7 +109,7 @@ asmlinkage __cpuinit void start_secondary(void)
72 cpu_report(); 109 cpu_report();
73 per_cpu_trap_init(); 110 per_cpu_trap_init();
74 mips_clockevent_init(); 111 mips_clockevent_init();
75 prom_init_secondary(); 112 mp_ops->init_secondary();
76 113
77 /* 114 /*
78 * XXX parity protection should be folded in here when it's converted 115 * XXX parity protection should be folded in here when it's converted
@@ -84,7 +121,8 @@ asmlinkage __cpuinit void start_secondary(void)
84 cpu = smp_processor_id(); 121 cpu = smp_processor_id();
85 cpu_data[cpu].udelay_val = loops_per_jiffy; 122 cpu_data[cpu].udelay_val = loops_per_jiffy;
86 123
87 prom_smp_finish(); 124 mp_ops->smp_finish();
125 set_cpu_sibling_map(cpu);
88 126
89 cpu_set(cpu, cpu_callin_map); 127 cpu_set(cpu, cpu_callin_map);
90 128
@@ -155,7 +193,7 @@ int smp_call_function_mask(cpumask_t mask, void (*func) (void *info),
155 smp_mb(); 193 smp_mb();
156 194
157 /* Send a message to all other CPUs and wait for them to respond */ 195 /* Send a message to all other CPUs and wait for them to respond */
158 core_send_ipi_mask(mask, SMP_CALL_FUNCTION); 196 mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
159 197
160 /* Wait for response */ 198 /* Wait for response */
161 /* FIXME: lock-up detection, backtrace on lock-up */ 199 /* FIXME: lock-up detection, backtrace on lock-up */
@@ -249,7 +287,7 @@ void smp_send_stop(void)
249 287
250void __init smp_cpus_done(unsigned int max_cpus) 288void __init smp_cpus_done(unsigned int max_cpus)
251{ 289{
252 prom_cpus_done(); 290 mp_ops->cpus_done();
253} 291}
254 292
255/* called from main before smp_init() */ 293/* called from main before smp_init() */
@@ -257,7 +295,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
257{ 295{
258 init_new_context(current, &init_mm); 296 init_new_context(current, &init_mm);
259 current_thread_info()->cpu = 0; 297 current_thread_info()->cpu = 0;
260 plat_prepare_cpus(max_cpus); 298 mp_ops->prepare_cpus(max_cpus);
299 set_cpu_sibling_map(0);
261#ifndef CONFIG_HOTPLUG_CPU 300#ifndef CONFIG_HOTPLUG_CPU
262 cpu_present_map = cpu_possible_map; 301 cpu_present_map = cpu_possible_map;
263#endif 302#endif
@@ -295,7 +334,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
295 if (IS_ERR(idle)) 334 if (IS_ERR(idle))
296 panic(KERN_ERR "Fork failed for CPU %d", cpu); 335 panic(KERN_ERR "Fork failed for CPU %d", cpu);
297 336
298 prom_boot_secondary(cpu, idle); 337 mp_ops->boot_secondary(cpu, idle);
299 338
300 /* 339 /*
301 * Trust is futile. We should really have timeouts ... 340 * Trust is futile. We should really have timeouts ...
diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c
index 6f3709996172..fe256559c997 100644
--- a/arch/mips/kernel/smtc-proc.c
+++ b/arch/mips/kernel/smtc-proc.c
@@ -14,7 +14,6 @@
14#include <asm/system.h> 14#include <asm/system.h>
15#include <asm/hardirq.h> 15#include <asm/hardirq.h>
16#include <asm/mmu_context.h> 16#include <asm/mmu_context.h>
17#include <asm/smp.h>
18#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
19#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
20#include <linux/proc_fs.h> 19#include <linux/proc_fs.h>
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 9c92d42996cb..85f700e58131 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -16,7 +16,6 @@
16#include <asm/hazards.h> 16#include <asm/hazards.h>
17#include <asm/irq.h> 17#include <asm/irq.h>
18#include <asm/mmu_context.h> 18#include <asm/mmu_context.h>
19#include <asm/smp.h>
20#include <asm/mipsregs.h> 19#include <asm/mipsregs.h>
21#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
22#include <asm/time.h> 21#include <asm/time.h>
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 2995be1ab3ca..9f85d4cecc5b 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -50,8 +50,6 @@ int update_persistent_clock(struct timespec now)
50 return rtc_mips_set_mmss(now.tv_sec); 50 return rtc_mips_set_mmss(now.tv_sec);
51} 51}
52 52
53int (*mips_timer_state)(void);
54
55int null_perf_irq(void) 53int null_perf_irq(void)
56{ 54{
57 return 0; 55 return 0;
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index c06eb812a95e..eed2dc4273e0 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -53,7 +53,6 @@
53#include <asm/system.h> 53#include <asm/system.h>
54#include <asm/vpe.h> 54#include <asm/vpe.h>
55#include <asm/kspd.h> 55#include <asm/kspd.h>
56#include <asm/mips_mt.h>
57 56
58typedef void *vpe_handle; 57typedef void *vpe_handle;
59 58
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
index 6471d0663fd8..d3d04c392e25 100644
--- a/arch/mips/lasat/picvue.c
+++ b/arch/mips/lasat/picvue.c
@@ -22,8 +22,6 @@
22 22
23struct pvc_defs *picvue; 23struct pvc_defs *picvue;
24 24
25DECLARE_MUTEX(pvc_sem);
26
27static void pvc_reg_write(u32 val) 25static void pvc_reg_write(u32 val)
28{ 26{
29 *picvue->reg = val; 27 *picvue->reg = val;
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
index 2a96bf971897..91df55371127 100644
--- a/arch/mips/lasat/picvue.h
+++ b/arch/mips/lasat/picvue.h
@@ -4,8 +4,6 @@
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <asm/semaphore.h>
8
9struct pvc_defs { 7struct pvc_defs {
10 volatile u32 *reg; 8 volatile u32 *reg;
11 u32 data_shift; 9 u32 data_shift;
@@ -45,4 +43,3 @@ void pvc_move(u8 cmd);
45void pvc_clear(void); 43void pvc_clear(void);
46void pvc_home(void); 44void pvc_home(void);
47 45
48extern struct semaphore pvc_sem;
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 9947c1525822..0bb6037afba3 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -13,9 +13,11 @@
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14 14
15#include <linux/timer.h> 15#include <linux/timer.h>
16#include <linux/mutex.h>
16 17
17#include "picvue.h" 18#include "picvue.h"
18 19
20static DEFINE_MUTEX(pvc_mutex);
19static char pvc_lines[PVC_NLINES][PVC_LINELEN+1]; 21static char pvc_lines[PVC_NLINES][PVC_LINELEN+1];
20static int pvc_linedata[PVC_NLINES]; 22static int pvc_linedata[PVC_NLINES];
21static struct proc_dir_entry *pvc_display_dir; 23static struct proc_dir_entry *pvc_display_dir;
@@ -48,9 +50,9 @@ static int pvc_proc_read_line(char *page, char **start,
48 return 0; 50 return 0;
49 } 51 }
50 52
51 down(&pvc_sem); 53 mutex_lock(&pvc_mutex);
52 page += sprintf(page, "%s\n", pvc_lines[lineno]); 54 page += sprintf(page, "%s\n", pvc_lines[lineno]);
53 up(&pvc_sem); 55 mutex_unlock(&pvc_mutex);
54 56
55 return page - origpage; 57 return page - origpage;
56} 58}
@@ -73,10 +75,10 @@ static int pvc_proc_write_line(struct file *file, const char *buffer,
73 if (buffer[count-1] == '\n') 75 if (buffer[count-1] == '\n')
74 count--; 76 count--;
75 77
76 down(&pvc_sem); 78 mutex_lock(&pvc_mutex);
77 strncpy(pvc_lines[lineno], buffer, count); 79 strncpy(pvc_lines[lineno], buffer, count);
78 pvc_lines[lineno][count] = '\0'; 80 pvc_lines[lineno][count] = '\0';
79 up(&pvc_sem); 81 mutex_unlock(&pvc_mutex);
80 82
81 tasklet_schedule(&pvc_display_tasklet); 83 tasklet_schedule(&pvc_display_tasklet);
82 84
@@ -89,7 +91,7 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
89 int origcount = count; 91 int origcount = count;
90 int cmd = simple_strtol(buffer, NULL, 10); 92 int cmd = simple_strtol(buffer, NULL, 10);
91 93
92 down(&pvc_sem); 94 mutex_lock(&pvc_mutex);
93 if (scroll_interval != 0) 95 if (scroll_interval != 0)
94 del_timer(&timer); 96 del_timer(&timer);
95 97
@@ -106,7 +108,7 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
106 } 108 }
107 add_timer(&timer); 109 add_timer(&timer);
108 } 110 }
109 up(&pvc_sem); 111 mutex_unlock(&pvc_mutex);
110 112
111 return origcount; 113 return origcount;
112} 114}
@@ -117,9 +119,9 @@ static int pvc_proc_read_scroll(char *page, char **start,
117{ 119{
118 char *origpage = page; 120 char *origpage = page;
119 121
120 down(&pvc_sem); 122 mutex_lock(&pvc_mutex);
121 page += sprintf(page, "%d\n", scroll_dir * scroll_interval); 123 page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
122 up(&pvc_sem); 124 mutex_unlock(&pvc_mutex);
123 125
124 return page - origpage; 126 return page - origpage;
125} 127}
diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c
index 1ade1cef3899..c1e41f15cc7e 100644
--- a/arch/mips/lemote/lm2e/pci.c
+++ b/arch/mips/lemote/lm2e/pci.c
@@ -81,9 +81,6 @@ static void __init ict_pcimap(void)
81 81
82static int __init pcibios_init(void) 82static int __init pcibios_init(void)
83{ 83{
84 extern int pci_probe_only;
85 pci_probe_only = 0;
86
87 ict_pcimap(); 84 ict_pcimap();
88 register_pci_controller(&loongson2e_pci_controller); 85 register_pci_controller(&loongson2e_pci_controller);
89 86
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c
index 824336812198..7edc15dfed6c 100644
--- a/arch/mips/lemote/lm2e/prom.c
+++ b/arch/mips/lemote/lm2e/prom.c
@@ -57,8 +57,6 @@ void __init prom_init(void)
57 arg = (int *)fw_arg1; 57 arg = (int *)fw_arg1;
58 env = (int *)fw_arg2; 58 env = (int *)fw_arg2;
59 59
60 mips_machtype = MACH_LEMOTE_FULONG;
61
62 prom_init_cmdline(); 60 prom_init_cmdline();
63 61
64 if ((strstr(arcs_cmdline, "console=")) == NULL) 62 if ((strstr(arcs_cmdline, "console=")) == NULL)
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index c0a77fe038be..8d7784122c14 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -7,6 +7,7 @@
7 * 7 *
8 * Copyright (C) 1998, 1999 Ralf Baechle 8 * Copyright (C) 1998, 1999 Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2007 Maciej W. Rozycki
10 */ 11 */
11#include <linux/errno.h> 12#include <linux/errno.h>
12#include <asm/asm.h> 13#include <asm/asm.h>
@@ -52,9 +53,12 @@
52#define UNIT(unit) ((unit)*NBYTES) 53#define UNIT(unit) ((unit)*NBYTES)
53 54
54#define ADDC(sum,reg) \ 55#define ADDC(sum,reg) \
56 .set push; \
57 .set noat; \
55 ADD sum, reg; \ 58 ADD sum, reg; \
56 sltu v1, sum, reg; \ 59 sltu v1, sum, reg; \
57 ADD sum, v1 60 ADD sum, v1; \
61 .set pop
58 62
59#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ 63#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
60 LOAD _t0, (offset + UNIT(0))(src); \ 64 LOAD _t0, (offset + UNIT(0))(src); \
@@ -92,13 +96,13 @@ LEAF(csum_partial)
92 move t7, zero 96 move t7, zero
93 97
94 sltiu t8, a1, 0x8 98 sltiu t8, a1, 0x8
95 bnez t8, small_csumcpy /* < 8 bytes to copy */ 99 bnez t8, .Lsmall_csumcpy /* < 8 bytes to copy */
96 move t2, a1 100 move t2, a1
97 101
98 andi t7, src, 0x1 /* odd buffer? */ 102 andi t7, src, 0x1 /* odd buffer? */
99 103
100hword_align: 104.Lhword_align:
101 beqz t7, word_align 105 beqz t7, .Lword_align
102 andi t8, src, 0x2 106 andi t8, src, 0x2
103 107
104 lbu t0, (src) 108 lbu t0, (src)
@@ -110,8 +114,8 @@ hword_align:
110 PTR_ADDU src, src, 0x1 114 PTR_ADDU src, src, 0x1
111 andi t8, src, 0x2 115 andi t8, src, 0x2
112 116
113word_align: 117.Lword_align:
114 beqz t8, dword_align 118 beqz t8, .Ldword_align
115 sltiu t8, a1, 56 119 sltiu t8, a1, 56
116 120
117 lhu t0, (src) 121 lhu t0, (src)
@@ -120,12 +124,12 @@ word_align:
120 sltiu t8, a1, 56 124 sltiu t8, a1, 56
121 PTR_ADDU src, src, 0x2 125 PTR_ADDU src, src, 0x2
122 126
123dword_align: 127.Ldword_align:
124 bnez t8, do_end_words 128 bnez t8, .Ldo_end_words
125 move t8, a1 129 move t8, a1
126 130
127 andi t8, src, 0x4 131 andi t8, src, 0x4
128 beqz t8, qword_align 132 beqz t8, .Lqword_align
129 andi t8, src, 0x8 133 andi t8, src, 0x8
130 134
131 lw t0, 0x00(src) 135 lw t0, 0x00(src)
@@ -134,8 +138,8 @@ dword_align:
134 PTR_ADDU src, src, 0x4 138 PTR_ADDU src, src, 0x4
135 andi t8, src, 0x8 139 andi t8, src, 0x8
136 140
137qword_align: 141.Lqword_align:
138 beqz t8, oword_align 142 beqz t8, .Loword_align
139 andi t8, src, 0x10 143 andi t8, src, 0x10
140 144
141#ifdef USE_DOUBLE 145#ifdef USE_DOUBLE
@@ -152,8 +156,8 @@ qword_align:
152 PTR_ADDU src, src, 0x8 156 PTR_ADDU src, src, 0x8
153 andi t8, src, 0x10 157 andi t8, src, 0x10
154 158
155oword_align: 159.Loword_align:
156 beqz t8, begin_movement 160 beqz t8, .Lbegin_movement
157 LONG_SRL t8, a1, 0x7 161 LONG_SRL t8, a1, 0x7
158 162
159#ifdef USE_DOUBLE 163#ifdef USE_DOUBLE
@@ -168,51 +172,55 @@ oword_align:
168 PTR_ADDU src, src, 0x10 172 PTR_ADDU src, src, 0x10
169 LONG_SRL t8, a1, 0x7 173 LONG_SRL t8, a1, 0x7
170 174
171begin_movement: 175.Lbegin_movement:
172 beqz t8, 1f 176 beqz t8, 1f
173 andi t2, a1, 0x40 177 andi t2, a1, 0x40
174 178
175move_128bytes: 179.Lmove_128bytes:
176 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) 180 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
177 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) 181 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
178 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4) 182 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
179 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4) 183 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
180 LONG_SUBU t8, t8, 0x01 184 LONG_SUBU t8, t8, 0x01
181 bnez t8, move_128bytes 185 .set reorder /* DADDI_WAR */
182 PTR_ADDU src, src, 0x80 186 PTR_ADDU src, src, 0x80
187 bnez t8, .Lmove_128bytes
188 .set noreorder
183 189
1841: 1901:
185 beqz t2, 1f 191 beqz t2, 1f
186 andi t2, a1, 0x20 192 andi t2, a1, 0x20
187 193
188move_64bytes: 194.Lmove_64bytes:
189 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) 195 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
190 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) 196 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
191 PTR_ADDU src, src, 0x40 197 PTR_ADDU src, src, 0x40
192 198
1931: 1991:
194 beqz t2, do_end_words 200 beqz t2, .Ldo_end_words
195 andi t8, a1, 0x1c 201 andi t8, a1, 0x1c
196 202
197move_32bytes: 203.Lmove_32bytes:
198 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) 204 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
199 andi t8, a1, 0x1c 205 andi t8, a1, 0x1c
200 PTR_ADDU src, src, 0x20 206 PTR_ADDU src, src, 0x20
201 207
202do_end_words: 208.Ldo_end_words:
203 beqz t8, small_csumcpy 209 beqz t8, .Lsmall_csumcpy
204 andi t2, a1, 0x3 210 andi t2, a1, 0x3
205 LONG_SRL t8, t8, 0x2 211 LONG_SRL t8, t8, 0x2
206 212
207end_words: 213.Lend_words:
208 lw t0, (src) 214 lw t0, (src)
209 LONG_SUBU t8, t8, 0x1 215 LONG_SUBU t8, t8, 0x1
210 ADDC(sum, t0) 216 ADDC(sum, t0)
211 bnez t8, end_words 217 .set reorder /* DADDI_WAR */
212 PTR_ADDU src, src, 0x4 218 PTR_ADDU src, src, 0x4
219 bnez t8, .Lend_words
220 .set noreorder
213 221
214/* unknown src alignment and < 8 bytes to go */ 222/* unknown src alignment and < 8 bytes to go */
215small_csumcpy: 223.Lsmall_csumcpy:
216 move a1, t2 224 move a1, t2
217 225
218 andi t0, a1, 4 226 andi t0, a1, 4
@@ -246,6 +254,8 @@ small_csumcpy:
2461: ADDC(sum, t1) 2541: ADDC(sum, t1)
247 255
248 /* fold checksum */ 256 /* fold checksum */
257 .set push
258 .set noat
249#ifdef USE_DOUBLE 259#ifdef USE_DOUBLE
250 dsll32 v1, sum, 0 260 dsll32 v1, sum, 0
251 daddu sum, v1 261 daddu sum, v1
@@ -266,6 +276,7 @@ small_csumcpy:
266 srl sum, sum, 8 276 srl sum, sum, 8
267 or sum, v1 277 or sum, v1
268 andi sum, 0xffff 278 andi sum, 0xffff
279 .set pop
2691: 2801:
270 .set reorder 281 .set reorder
271 /* Add the passed partial csum. */ 282 /* Add the passed partial csum. */
@@ -373,7 +384,11 @@ small_csumcpy:
373 384
374#define ADDRMASK (NBYTES-1) 385#define ADDRMASK (NBYTES-1)
375 386
387#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
376 .set noat 388 .set noat
389#else
390 .set at=v1
391#endif
377 392
378LEAF(__csum_partial_copy_user) 393LEAF(__csum_partial_copy_user)
379 PTR_ADDU AT, src, len /* See (1) above. */ 394 PTR_ADDU AT, src, len /* See (1) above. */
@@ -398,95 +413,101 @@ FEXPORT(csum_partial_copy_nocheck)
398 */ 413 */
399 sltu t2, len, NBYTES 414 sltu t2, len, NBYTES
400 and t1, dst, ADDRMASK 415 and t1, dst, ADDRMASK
401 bnez t2, copy_bytes_checklen 416 bnez t2, .Lcopy_bytes_checklen
402 and t0, src, ADDRMASK 417 and t0, src, ADDRMASK
403 andi odd, dst, 0x1 /* odd buffer? */ 418 andi odd, dst, 0x1 /* odd buffer? */
404 bnez t1, dst_unaligned 419 bnez t1, .Ldst_unaligned
405 nop 420 nop
406 bnez t0, src_unaligned_dst_aligned 421 bnez t0, .Lsrc_unaligned_dst_aligned
407 /* 422 /*
408 * use delay slot for fall-through 423 * use delay slot for fall-through
409 * src and dst are aligned; need to compute rem 424 * src and dst are aligned; need to compute rem
410 */ 425 */
411both_aligned: 426.Lboth_aligned:
412 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter 427 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
413 beqz t0, cleanup_both_aligned # len < 8*NBYTES 428 beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
414 nop 429 nop
415 SUB len, 8*NBYTES # subtract here for bgez loop 430 SUB len, 8*NBYTES # subtract here for bgez loop
416 .align 4 431 .align 4
4171: 4321:
418EXC( LOAD t0, UNIT(0)(src), l_exc) 433EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
419EXC( LOAD t1, UNIT(1)(src), l_exc_copy) 434EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
420EXC( LOAD t2, UNIT(2)(src), l_exc_copy) 435EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
421EXC( LOAD t3, UNIT(3)(src), l_exc_copy) 436EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
422EXC( LOAD t4, UNIT(4)(src), l_exc_copy) 437EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
423EXC( LOAD t5, UNIT(5)(src), l_exc_copy) 438EXC( LOAD t5, UNIT(5)(src), .Ll_exc_copy)
424EXC( LOAD t6, UNIT(6)(src), l_exc_copy) 439EXC( LOAD t6, UNIT(6)(src), .Ll_exc_copy)
425EXC( LOAD t7, UNIT(7)(src), l_exc_copy) 440EXC( LOAD t7, UNIT(7)(src), .Ll_exc_copy)
426 SUB len, len, 8*NBYTES 441 SUB len, len, 8*NBYTES
427 ADD src, src, 8*NBYTES 442 ADD src, src, 8*NBYTES
428EXC( STORE t0, UNIT(0)(dst), s_exc) 443EXC( STORE t0, UNIT(0)(dst), .Ls_exc)
429 ADDC(sum, t0) 444 ADDC(sum, t0)
430EXC( STORE t1, UNIT(1)(dst), s_exc) 445EXC( STORE t1, UNIT(1)(dst), .Ls_exc)
431 ADDC(sum, t1) 446 ADDC(sum, t1)
432EXC( STORE t2, UNIT(2)(dst), s_exc) 447EXC( STORE t2, UNIT(2)(dst), .Ls_exc)
433 ADDC(sum, t2) 448 ADDC(sum, t2)
434EXC( STORE t3, UNIT(3)(dst), s_exc) 449EXC( STORE t3, UNIT(3)(dst), .Ls_exc)
435 ADDC(sum, t3) 450 ADDC(sum, t3)
436EXC( STORE t4, UNIT(4)(dst), s_exc) 451EXC( STORE t4, UNIT(4)(dst), .Ls_exc)
437 ADDC(sum, t4) 452 ADDC(sum, t4)
438EXC( STORE t5, UNIT(5)(dst), s_exc) 453EXC( STORE t5, UNIT(5)(dst), .Ls_exc)
439 ADDC(sum, t5) 454 ADDC(sum, t5)
440EXC( STORE t6, UNIT(6)(dst), s_exc) 455EXC( STORE t6, UNIT(6)(dst), .Ls_exc)
441 ADDC(sum, t6) 456 ADDC(sum, t6)
442EXC( STORE t7, UNIT(7)(dst), s_exc) 457EXC( STORE t7, UNIT(7)(dst), .Ls_exc)
443 ADDC(sum, t7) 458 ADDC(sum, t7)
459 .set reorder /* DADDI_WAR */
460 ADD dst, dst, 8*NBYTES
444 bgez len, 1b 461 bgez len, 1b
445 ADD dst, dst, 8*NBYTES 462 .set noreorder
446 ADD len, 8*NBYTES # revert len (see above) 463 ADD len, 8*NBYTES # revert len (see above)
447 464
448 /* 465 /*
449 * len == the number of bytes left to copy < 8*NBYTES 466 * len == the number of bytes left to copy < 8*NBYTES
450 */ 467 */
451cleanup_both_aligned: 468.Lcleanup_both_aligned:
452#define rem t7 469#define rem t7
453 beqz len, done 470 beqz len, .Ldone
454 sltu t0, len, 4*NBYTES 471 sltu t0, len, 4*NBYTES
455 bnez t0, less_than_4units 472 bnez t0, .Lless_than_4units
456 and rem, len, (NBYTES-1) # rem = len % NBYTES 473 and rem, len, (NBYTES-1) # rem = len % NBYTES
457 /* 474 /*
458 * len >= 4*NBYTES 475 * len >= 4*NBYTES
459 */ 476 */
460EXC( LOAD t0, UNIT(0)(src), l_exc) 477EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
461EXC( LOAD t1, UNIT(1)(src), l_exc_copy) 478EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
462EXC( LOAD t2, UNIT(2)(src), l_exc_copy) 479EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
463EXC( LOAD t3, UNIT(3)(src), l_exc_copy) 480EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
464 SUB len, len, 4*NBYTES 481 SUB len, len, 4*NBYTES
465 ADD src, src, 4*NBYTES 482 ADD src, src, 4*NBYTES
466EXC( STORE t0, UNIT(0)(dst), s_exc) 483EXC( STORE t0, UNIT(0)(dst), .Ls_exc)
467 ADDC(sum, t0) 484 ADDC(sum, t0)
468EXC( STORE t1, UNIT(1)(dst), s_exc) 485EXC( STORE t1, UNIT(1)(dst), .Ls_exc)
469 ADDC(sum, t1) 486 ADDC(sum, t1)
470EXC( STORE t2, UNIT(2)(dst), s_exc) 487EXC( STORE t2, UNIT(2)(dst), .Ls_exc)
471 ADDC(sum, t2) 488 ADDC(sum, t2)
472EXC( STORE t3, UNIT(3)(dst), s_exc) 489EXC( STORE t3, UNIT(3)(dst), .Ls_exc)
473 ADDC(sum, t3) 490 ADDC(sum, t3)
474 beqz len, done 491 .set reorder /* DADDI_WAR */
475 ADD dst, dst, 4*NBYTES 492 ADD dst, dst, 4*NBYTES
476less_than_4units: 493 beqz len, .Ldone
494 .set noreorder
495.Lless_than_4units:
477 /* 496 /*
478 * rem = len % NBYTES 497 * rem = len % NBYTES
479 */ 498 */
480 beq rem, len, copy_bytes 499 beq rem, len, .Lcopy_bytes
481 nop 500 nop
4821: 5011:
483EXC( LOAD t0, 0(src), l_exc) 502EXC( LOAD t0, 0(src), .Ll_exc)
484 ADD src, src, NBYTES 503 ADD src, src, NBYTES
485 SUB len, len, NBYTES 504 SUB len, len, NBYTES
486EXC( STORE t0, 0(dst), s_exc) 505EXC( STORE t0, 0(dst), .Ls_exc)
487 ADDC(sum, t0) 506 ADDC(sum, t0)
507 .set reorder /* DADDI_WAR */
508 ADD dst, dst, NBYTES
488 bne rem, len, 1b 509 bne rem, len, 1b
489 ADD dst, dst, NBYTES 510 .set noreorder
490 511
491 /* 512 /*
492 * src and dst are aligned, need to copy rem bytes (rem < NBYTES) 513 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
@@ -500,20 +521,20 @@ EXC( STORE t0, 0(dst), s_exc)
500 * more instruction-level parallelism. 521 * more instruction-level parallelism.
501 */ 522 */
502#define bits t2 523#define bits t2
503 beqz len, done 524 beqz len, .Ldone
504 ADD t1, dst, len # t1 is just past last byte of dst 525 ADD t1, dst, len # t1 is just past last byte of dst
505 li bits, 8*NBYTES 526 li bits, 8*NBYTES
506 SLL rem, len, 3 # rem = number of bits to keep 527 SLL rem, len, 3 # rem = number of bits to keep
507EXC( LOAD t0, 0(src), l_exc) 528EXC( LOAD t0, 0(src), .Ll_exc)
508 SUB bits, bits, rem # bits = number of bits to discard 529 SUB bits, bits, rem # bits = number of bits to discard
509 SHIFT_DISCARD t0, t0, bits 530 SHIFT_DISCARD t0, t0, bits
510EXC( STREST t0, -1(t1), s_exc) 531EXC( STREST t0, -1(t1), .Ls_exc)
511 SHIFT_DISCARD_REVERT t0, t0, bits 532 SHIFT_DISCARD_REVERT t0, t0, bits
512 .set reorder 533 .set reorder
513 ADDC(sum, t0) 534 ADDC(sum, t0)
514 b done 535 b .Ldone
515 .set noreorder 536 .set noreorder
516dst_unaligned: 537.Ldst_unaligned:
517 /* 538 /*
518 * dst is unaligned 539 * dst is unaligned
519 * t0 = src & ADDRMASK 540 * t0 = src & ADDRMASK
@@ -524,25 +545,25 @@ dst_unaligned:
524 * Set match = (src and dst have same alignment) 545 * Set match = (src and dst have same alignment)
525 */ 546 */
526#define match rem 547#define match rem
527EXC( LDFIRST t3, FIRST(0)(src), l_exc) 548EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
528 ADD t2, zero, NBYTES 549 ADD t2, zero, NBYTES
529EXC( LDREST t3, REST(0)(src), l_exc_copy) 550EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
530 SUB t2, t2, t1 # t2 = number of bytes copied 551 SUB t2, t2, t1 # t2 = number of bytes copied
531 xor match, t0, t1 552 xor match, t0, t1
532EXC( STFIRST t3, FIRST(0)(dst), s_exc) 553EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc)
533 SLL t4, t1, 3 # t4 = number of bits to discard 554 SLL t4, t1, 3 # t4 = number of bits to discard
534 SHIFT_DISCARD t3, t3, t4 555 SHIFT_DISCARD t3, t3, t4
535 /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */ 556 /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */
536 ADDC(sum, t3) 557 ADDC(sum, t3)
537 beq len, t2, done 558 beq len, t2, .Ldone
538 SUB len, len, t2 559 SUB len, len, t2
539 ADD dst, dst, t2 560 ADD dst, dst, t2
540 beqz match, both_aligned 561 beqz match, .Lboth_aligned
541 ADD src, src, t2 562 ADD src, src, t2
542 563
543src_unaligned_dst_aligned: 564.Lsrc_unaligned_dst_aligned:
544 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter 565 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
545 beqz t0, cleanup_src_unaligned 566 beqz t0, .Lcleanup_src_unaligned
546 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 567 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
5471: 5681:
548/* 569/*
@@ -551,49 +572,53 @@ src_unaligned_dst_aligned:
551 * It's OK to load FIRST(N+1) before REST(N) because the two addresses 572 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
552 * are to the same unit (unless src is aligned, but it's not). 573 * are to the same unit (unless src is aligned, but it's not).
553 */ 574 */
554EXC( LDFIRST t0, FIRST(0)(src), l_exc) 575EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
555EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) 576EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
556 SUB len, len, 4*NBYTES 577 SUB len, len, 4*NBYTES
557EXC( LDREST t0, REST(0)(src), l_exc_copy) 578EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
558EXC( LDREST t1, REST(1)(src), l_exc_copy) 579EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
559EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) 580EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
560EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) 581EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
561EXC( LDREST t2, REST(2)(src), l_exc_copy) 582EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
562EXC( LDREST t3, REST(3)(src), l_exc_copy) 583EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
563 ADD src, src, 4*NBYTES 584 ADD src, src, 4*NBYTES
564#ifdef CONFIG_CPU_SB1 585#ifdef CONFIG_CPU_SB1
565 nop # improves slotting 586 nop # improves slotting
566#endif 587#endif
567EXC( STORE t0, UNIT(0)(dst), s_exc) 588EXC( STORE t0, UNIT(0)(dst), .Ls_exc)
568 ADDC(sum, t0) 589 ADDC(sum, t0)
569EXC( STORE t1, UNIT(1)(dst), s_exc) 590EXC( STORE t1, UNIT(1)(dst), .Ls_exc)
570 ADDC(sum, t1) 591 ADDC(sum, t1)
571EXC( STORE t2, UNIT(2)(dst), s_exc) 592EXC( STORE t2, UNIT(2)(dst), .Ls_exc)
572 ADDC(sum, t2) 593 ADDC(sum, t2)
573EXC( STORE t3, UNIT(3)(dst), s_exc) 594EXC( STORE t3, UNIT(3)(dst), .Ls_exc)
574 ADDC(sum, t3) 595 ADDC(sum, t3)
596 .set reorder /* DADDI_WAR */
597 ADD dst, dst, 4*NBYTES
575 bne len, rem, 1b 598 bne len, rem, 1b
576 ADD dst, dst, 4*NBYTES 599 .set noreorder
577 600
578cleanup_src_unaligned: 601.Lcleanup_src_unaligned:
579 beqz len, done 602 beqz len, .Ldone
580 and rem, len, NBYTES-1 # rem = len % NBYTES 603 and rem, len, NBYTES-1 # rem = len % NBYTES
581 beq rem, len, copy_bytes 604 beq rem, len, .Lcopy_bytes
582 nop 605 nop
5831: 6061:
584EXC( LDFIRST t0, FIRST(0)(src), l_exc) 607EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
585EXC( LDREST t0, REST(0)(src), l_exc_copy) 608EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
586 ADD src, src, NBYTES 609 ADD src, src, NBYTES
587 SUB len, len, NBYTES 610 SUB len, len, NBYTES
588EXC( STORE t0, 0(dst), s_exc) 611EXC( STORE t0, 0(dst), .Ls_exc)
589 ADDC(sum, t0) 612 ADDC(sum, t0)
613 .set reorder /* DADDI_WAR */
614 ADD dst, dst, NBYTES
590 bne len, rem, 1b 615 bne len, rem, 1b
591 ADD dst, dst, NBYTES 616 .set noreorder
592 617
593copy_bytes_checklen: 618.Lcopy_bytes_checklen:
594 beqz len, done 619 beqz len, .Ldone
595 nop 620 nop
596copy_bytes: 621.Lcopy_bytes:
597 /* 0 < len < NBYTES */ 622 /* 0 < len < NBYTES */
598#ifdef CONFIG_CPU_LITTLE_ENDIAN 623#ifdef CONFIG_CPU_LITTLE_ENDIAN
599#define SHIFT_START 0 624#define SHIFT_START 0
@@ -604,14 +629,14 @@ copy_bytes:
604#endif 629#endif
605 move t2, zero # partial word 630 move t2, zero # partial word
606 li t3, SHIFT_START # shift 631 li t3, SHIFT_START # shift
607/* use l_exc_copy here to return correct sum on fault */ 632/* use .Ll_exc_copy here to return correct sum on fault */
608#define COPY_BYTE(N) \ 633#define COPY_BYTE(N) \
609EXC( lbu t0, N(src), l_exc_copy); \ 634EXC( lbu t0, N(src), .Ll_exc_copy); \
610 SUB len, len, 1; \ 635 SUB len, len, 1; \
611EXC( sb t0, N(dst), s_exc); \ 636EXC( sb t0, N(dst), .Ls_exc); \
612 SLLV t0, t0, t3; \ 637 SLLV t0, t0, t3; \
613 addu t3, SHIFT_INC; \ 638 addu t3, SHIFT_INC; \
614 beqz len, copy_bytes_done; \ 639 beqz len, .Lcopy_bytes_done; \
615 or t2, t0 640 or t2, t0
616 641
617 COPY_BYTE(0) 642 COPY_BYTE(0)
@@ -622,15 +647,17 @@ EXC( sb t0, N(dst), s_exc); \
622 COPY_BYTE(4) 647 COPY_BYTE(4)
623 COPY_BYTE(5) 648 COPY_BYTE(5)
624#endif 649#endif
625EXC( lbu t0, NBYTES-2(src), l_exc_copy) 650EXC( lbu t0, NBYTES-2(src), .Ll_exc_copy)
626 SUB len, len, 1 651 SUB len, len, 1
627EXC( sb t0, NBYTES-2(dst), s_exc) 652EXC( sb t0, NBYTES-2(dst), .Ls_exc)
628 SLLV t0, t0, t3 653 SLLV t0, t0, t3
629 or t2, t0 654 or t2, t0
630copy_bytes_done: 655.Lcopy_bytes_done:
631 ADDC(sum, t2) 656 ADDC(sum, t2)
632done: 657.Ldone:
633 /* fold checksum */ 658 /* fold checksum */
659 .set push
660 .set noat
634#ifdef USE_DOUBLE 661#ifdef USE_DOUBLE
635 dsll32 v1, sum, 0 662 dsll32 v1, sum, 0
636 daddu sum, v1 663 daddu sum, v1
@@ -651,13 +678,14 @@ done:
651 srl sum, sum, 8 678 srl sum, sum, 8
652 or sum, v1 679 or sum, v1
653 andi sum, 0xffff 680 andi sum, 0xffff
681 .set pop
6541: 6821:
655 .set reorder 683 .set reorder
656 ADDC(sum, psum) 684 ADDC(sum, psum)
657 jr ra 685 jr ra
658 .set noreorder 686 .set noreorder
659 687
660l_exc_copy: 688.Ll_exc_copy:
661 /* 689 /*
662 * Copy bytes from src until faulting load address (or until a 690 * Copy bytes from src until faulting load address (or until a
663 * lb faults) 691 * lb faults)
@@ -672,15 +700,17 @@ l_exc_copy:
672 li t2, SHIFT_START 700 li t2, SHIFT_START
673 LOAD t0, THREAD_BUADDR(t0) 701 LOAD t0, THREAD_BUADDR(t0)
6741: 7021:
675EXC( lbu t1, 0(src), l_exc) 703EXC( lbu t1, 0(src), .Ll_exc)
676 ADD src, src, 1 704 ADD src, src, 1
677 sb t1, 0(dst) # can't fault -- we're copy_from_user 705 sb t1, 0(dst) # can't fault -- we're copy_from_user
678 SLLV t1, t1, t2 706 SLLV t1, t1, t2
679 addu t2, SHIFT_INC 707 addu t2, SHIFT_INC
680 ADDC(sum, t1) 708 ADDC(sum, t1)
709 .set reorder /* DADDI_WAR */
710 ADD dst, dst, 1
681 bne src, t0, 1b 711 bne src, t0, 1b
682 ADD dst, dst, 1 712 .set noreorder
683l_exc: 713.Ll_exc:
684 LOAD t0, TI_TASK($28) 714 LOAD t0, TI_TASK($28)
685 nop 715 nop
686 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address 716 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
@@ -697,19 +727,30 @@ l_exc:
697 * Clear len bytes starting at dst. Can't call __bzero because it 727 * Clear len bytes starting at dst. Can't call __bzero because it
698 * might modify len. An inefficient loop for these rare times... 728 * might modify len. An inefficient loop for these rare times...
699 */ 729 */
700 beqz len, done 730 .set reorder /* DADDI_WAR */
701 SUB src, len, 1 731 SUB src, len, 1
732 beqz len, .Ldone
733 .set noreorder
7021: sb zero, 0(dst) 7341: sb zero, 0(dst)
703 ADD dst, dst, 1 735 ADD dst, dst, 1
736 .set push
737 .set noat
738#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
704 bnez src, 1b 739 bnez src, 1b
705 SUB src, src, 1 740 SUB src, src, 1
741#else
742 li v1, 1
743 bnez src, 1b
744 SUB src, src, v1
745#endif
706 li v1, -EFAULT 746 li v1, -EFAULT
707 b done 747 b .Ldone
708 sw v1, (errptr) 748 sw v1, (errptr)
709 749
710s_exc: 750.Ls_exc:
711 li v0, -1 /* invalid checksum */ 751 li v0, -1 /* invalid checksum */
712 li v1, -EFAULT 752 li v1, -EFAULT
713 jr ra 753 jr ra
714 sw v1, (errptr) 754 sw v1, (errptr)
755 .set pop
715 END(__csum_partial_copy_user) 756 END(__csum_partial_copy_user)
diff --git a/arch/mips/lib/memcpy-inatomic.S b/arch/mips/lib/memcpy-inatomic.S
index 3a534b2baa0f..736d0fb56a94 100644
--- a/arch/mips/lib/memcpy-inatomic.S
+++ b/arch/mips/lib/memcpy-inatomic.S
@@ -9,6 +9,7 @@
9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. 9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
10 * Copyright (C) 2002 Broadcom, Inc. 10 * Copyright (C) 2002 Broadcom, Inc.
11 * memcpy/copy_user author: Mark Vandevoorde 11 * memcpy/copy_user author: Mark Vandevoorde
12 * Copyright (C) 2007 Maciej W. Rozycki
12 * 13 *
13 * Mnemonic names for arguments to memcpy/__copy_user 14 * Mnemonic names for arguments to memcpy/__copy_user
14 */ 15 */
@@ -175,7 +176,11 @@
175 176
176 .text 177 .text
177 .set noreorder 178 .set noreorder
179#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
178 .set noat 180 .set noat
181#else
182 .set at=v1
183#endif
179 184
180/* 185/*
181 * A combined memcpy/__copy_user 186 * A combined memcpy/__copy_user
@@ -204,36 +209,36 @@ LEAF(__copy_user_inatomic)
204 and t1, dst, ADDRMASK 209 and t1, dst, ADDRMASK
205 PREF( 0, 1*32(src) ) 210 PREF( 0, 1*32(src) )
206 PREF( 1, 1*32(dst) ) 211 PREF( 1, 1*32(dst) )
207 bnez t2, copy_bytes_checklen 212 bnez t2, .Lcopy_bytes_checklen
208 and t0, src, ADDRMASK 213 and t0, src, ADDRMASK
209 PREF( 0, 2*32(src) ) 214 PREF( 0, 2*32(src) )
210 PREF( 1, 2*32(dst) ) 215 PREF( 1, 2*32(dst) )
211 bnez t1, dst_unaligned 216 bnez t1, .Ldst_unaligned
212 nop 217 nop
213 bnez t0, src_unaligned_dst_aligned 218 bnez t0, .Lsrc_unaligned_dst_aligned
214 /* 219 /*
215 * use delay slot for fall-through 220 * use delay slot for fall-through
216 * src and dst are aligned; need to compute rem 221 * src and dst are aligned; need to compute rem
217 */ 222 */
218both_aligned: 223.Lboth_aligned:
219 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter 224 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
220 beqz t0, cleanup_both_aligned # len < 8*NBYTES 225 beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
221 and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) 226 and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
222 PREF( 0, 3*32(src) ) 227 PREF( 0, 3*32(src) )
223 PREF( 1, 3*32(dst) ) 228 PREF( 1, 3*32(dst) )
224 .align 4 229 .align 4
2251: 2301:
226EXC( LOAD t0, UNIT(0)(src), l_exc) 231EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
227EXC( LOAD t1, UNIT(1)(src), l_exc_copy) 232EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
228EXC( LOAD t2, UNIT(2)(src), l_exc_copy) 233EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
229EXC( LOAD t3, UNIT(3)(src), l_exc_copy) 234EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
230 SUB len, len, 8*NBYTES 235 SUB len, len, 8*NBYTES
231EXC( LOAD t4, UNIT(4)(src), l_exc_copy) 236EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
232EXC( LOAD t7, UNIT(5)(src), l_exc_copy) 237EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy)
233 STORE t0, UNIT(0)(dst) 238 STORE t0, UNIT(0)(dst)
234 STORE t1, UNIT(1)(dst) 239 STORE t1, UNIT(1)(dst)
235EXC( LOAD t0, UNIT(6)(src), l_exc_copy) 240EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy)
236EXC( LOAD t1, UNIT(7)(src), l_exc_copy) 241EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy)
237 ADD src, src, 8*NBYTES 242 ADD src, src, 8*NBYTES
238 ADD dst, dst, 8*NBYTES 243 ADD dst, dst, 8*NBYTES
239 STORE t2, UNIT(-6)(dst) 244 STORE t2, UNIT(-6)(dst)
@@ -250,39 +255,43 @@ EXC( LOAD t1, UNIT(7)(src), l_exc_copy)
250 /* 255 /*
251 * len == rem == the number of bytes left to copy < 8*NBYTES 256 * len == rem == the number of bytes left to copy < 8*NBYTES
252 */ 257 */
253cleanup_both_aligned: 258.Lcleanup_both_aligned:
254 beqz len, done 259 beqz len, .Ldone
255 sltu t0, len, 4*NBYTES 260 sltu t0, len, 4*NBYTES
256 bnez t0, less_than_4units 261 bnez t0, .Lless_than_4units
257 and rem, len, (NBYTES-1) # rem = len % NBYTES 262 and rem, len, (NBYTES-1) # rem = len % NBYTES
258 /* 263 /*
259 * len >= 4*NBYTES 264 * len >= 4*NBYTES
260 */ 265 */
261EXC( LOAD t0, UNIT(0)(src), l_exc) 266EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
262EXC( LOAD t1, UNIT(1)(src), l_exc_copy) 267EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
263EXC( LOAD t2, UNIT(2)(src), l_exc_copy) 268EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
264EXC( LOAD t3, UNIT(3)(src), l_exc_copy) 269EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
265 SUB len, len, 4*NBYTES 270 SUB len, len, 4*NBYTES
266 ADD src, src, 4*NBYTES 271 ADD src, src, 4*NBYTES
267 STORE t0, UNIT(0)(dst) 272 STORE t0, UNIT(0)(dst)
268 STORE t1, UNIT(1)(dst) 273 STORE t1, UNIT(1)(dst)
269 STORE t2, UNIT(2)(dst) 274 STORE t2, UNIT(2)(dst)
270 STORE t3, UNIT(3)(dst) 275 STORE t3, UNIT(3)(dst)
271 beqz len, done 276 .set reorder /* DADDI_WAR */
272 ADD dst, dst, 4*NBYTES 277 ADD dst, dst, 4*NBYTES
273less_than_4units: 278 beqz len, .Ldone
279 .set noreorder
280.Lless_than_4units:
274 /* 281 /*
275 * rem = len % NBYTES 282 * rem = len % NBYTES
276 */ 283 */
277 beq rem, len, copy_bytes 284 beq rem, len, .Lcopy_bytes
278 nop 285 nop
2791: 2861:
280EXC( LOAD t0, 0(src), l_exc) 287EXC( LOAD t0, 0(src), .Ll_exc)
281 ADD src, src, NBYTES 288 ADD src, src, NBYTES
282 SUB len, len, NBYTES 289 SUB len, len, NBYTES
283 STORE t0, 0(dst) 290 STORE t0, 0(dst)
291 .set reorder /* DADDI_WAR */
292 ADD dst, dst, NBYTES
284 bne rem, len, 1b 293 bne rem, len, 1b
285 ADD dst, dst, NBYTES 294 .set noreorder
286 295
287 /* 296 /*
288 * src and dst are aligned, need to copy rem bytes (rem < NBYTES) 297 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
@@ -296,17 +305,17 @@ EXC( LOAD t0, 0(src), l_exc)
296 * more instruction-level parallelism. 305 * more instruction-level parallelism.
297 */ 306 */
298#define bits t2 307#define bits t2
299 beqz len, done 308 beqz len, .Ldone
300 ADD t1, dst, len # t1 is just past last byte of dst 309 ADD t1, dst, len # t1 is just past last byte of dst
301 li bits, 8*NBYTES 310 li bits, 8*NBYTES
302 SLL rem, len, 3 # rem = number of bits to keep 311 SLL rem, len, 3 # rem = number of bits to keep
303EXC( LOAD t0, 0(src), l_exc) 312EXC( LOAD t0, 0(src), .Ll_exc)
304 SUB bits, bits, rem # bits = number of bits to discard 313 SUB bits, bits, rem # bits = number of bits to discard
305 SHIFT_DISCARD t0, t0, bits 314 SHIFT_DISCARD t0, t0, bits
306 STREST t0, -1(t1) 315 STREST t0, -1(t1)
307 jr ra 316 jr ra
308 move len, zero 317 move len, zero
309dst_unaligned: 318.Ldst_unaligned:
310 /* 319 /*
311 * dst is unaligned 320 * dst is unaligned
312 * t0 = src & ADDRMASK 321 * t0 = src & ADDRMASK
@@ -317,22 +326,22 @@ dst_unaligned:
317 * Set match = (src and dst have same alignment) 326 * Set match = (src and dst have same alignment)
318 */ 327 */
319#define match rem 328#define match rem
320EXC( LDFIRST t3, FIRST(0)(src), l_exc) 329EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
321 ADD t2, zero, NBYTES 330 ADD t2, zero, NBYTES
322EXC( LDREST t3, REST(0)(src), l_exc_copy) 331EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
323 SUB t2, t2, t1 # t2 = number of bytes copied 332 SUB t2, t2, t1 # t2 = number of bytes copied
324 xor match, t0, t1 333 xor match, t0, t1
325 STFIRST t3, FIRST(0)(dst) 334 STFIRST t3, FIRST(0)(dst)
326 beq len, t2, done 335 beq len, t2, .Ldone
327 SUB len, len, t2 336 SUB len, len, t2
328 ADD dst, dst, t2 337 ADD dst, dst, t2
329 beqz match, both_aligned 338 beqz match, .Lboth_aligned
330 ADD src, src, t2 339 ADD src, src, t2
331 340
332src_unaligned_dst_aligned: 341.Lsrc_unaligned_dst_aligned:
333 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter 342 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
334 PREF( 0, 3*32(src) ) 343 PREF( 0, 3*32(src) )
335 beqz t0, cleanup_src_unaligned 344 beqz t0, .Lcleanup_src_unaligned
336 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 345 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
337 PREF( 1, 3*32(dst) ) 346 PREF( 1, 3*32(dst) )
3381: 3471:
@@ -342,15 +351,15 @@ src_unaligned_dst_aligned:
342 * It's OK to load FIRST(N+1) before REST(N) because the two addresses 351 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
343 * are to the same unit (unless src is aligned, but it's not). 352 * are to the same unit (unless src is aligned, but it's not).
344 */ 353 */
345EXC( LDFIRST t0, FIRST(0)(src), l_exc) 354EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
346EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) 355EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
347 SUB len, len, 4*NBYTES 356 SUB len, len, 4*NBYTES
348EXC( LDREST t0, REST(0)(src), l_exc_copy) 357EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
349EXC( LDREST t1, REST(1)(src), l_exc_copy) 358EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
350EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) 359EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
351EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) 360EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
352EXC( LDREST t2, REST(2)(src), l_exc_copy) 361EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
353EXC( LDREST t3, REST(3)(src), l_exc_copy) 362EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
354 PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) 363 PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
355 ADD src, src, 4*NBYTES 364 ADD src, src, 4*NBYTES
356#ifdef CONFIG_CPU_SB1 365#ifdef CONFIG_CPU_SB1
@@ -361,32 +370,36 @@ EXC( LDREST t3, REST(3)(src), l_exc_copy)
361 STORE t2, UNIT(2)(dst) 370 STORE t2, UNIT(2)(dst)
362 STORE t3, UNIT(3)(dst) 371 STORE t3, UNIT(3)(dst)
363 PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) 372 PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
373 .set reorder /* DADDI_WAR */
374 ADD dst, dst, 4*NBYTES
364 bne len, rem, 1b 375 bne len, rem, 1b
365 ADD dst, dst, 4*NBYTES 376 .set noreorder
366 377
367cleanup_src_unaligned: 378.Lcleanup_src_unaligned:
368 beqz len, done 379 beqz len, .Ldone
369 and rem, len, NBYTES-1 # rem = len % NBYTES 380 and rem, len, NBYTES-1 # rem = len % NBYTES
370 beq rem, len, copy_bytes 381 beq rem, len, .Lcopy_bytes
371 nop 382 nop
3721: 3831:
373EXC( LDFIRST t0, FIRST(0)(src), l_exc) 384EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
374EXC( LDREST t0, REST(0)(src), l_exc_copy) 385EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
375 ADD src, src, NBYTES 386 ADD src, src, NBYTES
376 SUB len, len, NBYTES 387 SUB len, len, NBYTES
377 STORE t0, 0(dst) 388 STORE t0, 0(dst)
389 .set reorder /* DADDI_WAR */
390 ADD dst, dst, NBYTES
378 bne len, rem, 1b 391 bne len, rem, 1b
379 ADD dst, dst, NBYTES 392 .set noreorder
380 393
381copy_bytes_checklen: 394.Lcopy_bytes_checklen:
382 beqz len, done 395 beqz len, .Ldone
383 nop 396 nop
384copy_bytes: 397.Lcopy_bytes:
385 /* 0 < len < NBYTES */ 398 /* 0 < len < NBYTES */
386#define COPY_BYTE(N) \ 399#define COPY_BYTE(N) \
387EXC( lb t0, N(src), l_exc); \ 400EXC( lb t0, N(src), .Ll_exc); \
388 SUB len, len, 1; \ 401 SUB len, len, 1; \
389 beqz len, done; \ 402 beqz len, .Ldone; \
390 sb t0, N(dst) 403 sb t0, N(dst)
391 404
392 COPY_BYTE(0) 405 COPY_BYTE(0)
@@ -397,16 +410,16 @@ EXC( lb t0, N(src), l_exc); \
397 COPY_BYTE(4) 410 COPY_BYTE(4)
398 COPY_BYTE(5) 411 COPY_BYTE(5)
399#endif 412#endif
400EXC( lb t0, NBYTES-2(src), l_exc) 413EXC( lb t0, NBYTES-2(src), .Ll_exc)
401 SUB len, len, 1 414 SUB len, len, 1
402 jr ra 415 jr ra
403 sb t0, NBYTES-2(dst) 416 sb t0, NBYTES-2(dst)
404done: 417.Ldone:
405 jr ra 418 jr ra
406 nop 419 nop
407 END(__copy_user_inatomic) 420 END(__copy_user_inatomic)
408 421
409l_exc_copy: 422.Ll_exc_copy:
410 /* 423 /*
411 * Copy bytes from src until faulting load address (or until a 424 * Copy bytes from src until faulting load address (or until a
412 * lb faults) 425 * lb faults)
@@ -421,12 +434,14 @@ l_exc_copy:
421 nop 434 nop
422 LOAD t0, THREAD_BUADDR(t0) 435 LOAD t0, THREAD_BUADDR(t0)
4231: 4361:
424EXC( lb t1, 0(src), l_exc) 437EXC( lb t1, 0(src), .Ll_exc)
425 ADD src, src, 1 438 ADD src, src, 1
426 sb t1, 0(dst) # can't fault -- we're copy_from_user 439 sb t1, 0(dst) # can't fault -- we're copy_from_user
440 .set reorder /* DADDI_WAR */
441 ADD dst, dst, 1
427 bne src, t0, 1b 442 bne src, t0, 1b
428 ADD dst, dst, 1 443 .set noreorder
429l_exc: 444.Ll_exc:
430 LOAD t0, TI_TASK($28) 445 LOAD t0, TI_TASK($28)
431 nop 446 nop
432 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address 447 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index a526c62cb76a..c06cccf60bec 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -9,6 +9,7 @@
9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. 9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
10 * Copyright (C) 2002 Broadcom, Inc. 10 * Copyright (C) 2002 Broadcom, Inc.
11 * memcpy/copy_user author: Mark Vandevoorde 11 * memcpy/copy_user author: Mark Vandevoorde
12 * Copyright (C) 2007 Maciej W. Rozycki
12 * 13 *
13 * Mnemonic names for arguments to memcpy/__copy_user 14 * Mnemonic names for arguments to memcpy/__copy_user
14 */ 15 */
@@ -175,7 +176,11 @@
175 176
176 .text 177 .text
177 .set noreorder 178 .set noreorder
179#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
178 .set noat 180 .set noat
181#else
182 .set at=v1
183#endif
179 184
180/* 185/*
181 * A combined memcpy/__copy_user 186 * A combined memcpy/__copy_user
@@ -186,7 +191,7 @@
186 .align 5 191 .align 5
187LEAF(memcpy) /* a0=dst a1=src a2=len */ 192LEAF(memcpy) /* a0=dst a1=src a2=len */
188 move v0, dst /* return value */ 193 move v0, dst /* return value */
189__memcpy: 194.L__memcpy:
190FEXPORT(__copy_user) 195FEXPORT(__copy_user)
191 /* 196 /*
192 * Note: dst & src may be unaligned, len may be 0 197 * Note: dst & src may be unaligned, len may be 0
@@ -194,6 +199,7 @@ FEXPORT(__copy_user)
194 */ 199 */
195#define rem t8 200#define rem t8
196 201
202 R10KCBARRIER(0(ra))
197 /* 203 /*
198 * The "issue break"s below are very approximate. 204 * The "issue break"s below are very approximate.
199 * Issue delays for dcache fills will perturb the schedule, as will 205 * Issue delays for dcache fills will perturb the schedule, as will
@@ -207,44 +213,45 @@ FEXPORT(__copy_user)
207 and t1, dst, ADDRMASK 213 and t1, dst, ADDRMASK
208 PREF( 0, 1*32(src) ) 214 PREF( 0, 1*32(src) )
209 PREF( 1, 1*32(dst) ) 215 PREF( 1, 1*32(dst) )
210 bnez t2, copy_bytes_checklen 216 bnez t2, .Lcopy_bytes_checklen
211 and t0, src, ADDRMASK 217 and t0, src, ADDRMASK
212 PREF( 0, 2*32(src) ) 218 PREF( 0, 2*32(src) )
213 PREF( 1, 2*32(dst) ) 219 PREF( 1, 2*32(dst) )
214 bnez t1, dst_unaligned 220 bnez t1, .Ldst_unaligned
215 nop 221 nop
216 bnez t0, src_unaligned_dst_aligned 222 bnez t0, .Lsrc_unaligned_dst_aligned
217 /* 223 /*
218 * use delay slot for fall-through 224 * use delay slot for fall-through
219 * src and dst are aligned; need to compute rem 225 * src and dst are aligned; need to compute rem
220 */ 226 */
221both_aligned: 227.Lboth_aligned:
222 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter 228 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
223 beqz t0, cleanup_both_aligned # len < 8*NBYTES 229 beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
224 and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) 230 and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
225 PREF( 0, 3*32(src) ) 231 PREF( 0, 3*32(src) )
226 PREF( 1, 3*32(dst) ) 232 PREF( 1, 3*32(dst) )
227 .align 4 233 .align 4
2281: 2341:
229EXC( LOAD t0, UNIT(0)(src), l_exc) 235 R10KCBARRIER(0(ra))
230EXC( LOAD t1, UNIT(1)(src), l_exc_copy) 236EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
231EXC( LOAD t2, UNIT(2)(src), l_exc_copy) 237EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
232EXC( LOAD t3, UNIT(3)(src), l_exc_copy) 238EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
239EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
233 SUB len, len, 8*NBYTES 240 SUB len, len, 8*NBYTES
234EXC( LOAD t4, UNIT(4)(src), l_exc_copy) 241EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
235EXC( LOAD t7, UNIT(5)(src), l_exc_copy) 242EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy)
236EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) 243EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p8u)
237EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) 244EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p7u)
238EXC( LOAD t0, UNIT(6)(src), l_exc_copy) 245EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy)
239EXC( LOAD t1, UNIT(7)(src), l_exc_copy) 246EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy)
240 ADD src, src, 8*NBYTES 247 ADD src, src, 8*NBYTES
241 ADD dst, dst, 8*NBYTES 248 ADD dst, dst, 8*NBYTES
242EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) 249EXC( STORE t2, UNIT(-6)(dst), .Ls_exc_p6u)
243EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) 250EXC( STORE t3, UNIT(-5)(dst), .Ls_exc_p5u)
244EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u) 251EXC( STORE t4, UNIT(-4)(dst), .Ls_exc_p4u)
245EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u) 252EXC( STORE t7, UNIT(-3)(dst), .Ls_exc_p3u)
246EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u) 253EXC( STORE t0, UNIT(-2)(dst), .Ls_exc_p2u)
247EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u) 254EXC( STORE t1, UNIT(-1)(dst), .Ls_exc_p1u)
248 PREF( 0, 8*32(src) ) 255 PREF( 0, 8*32(src) )
249 PREF( 1, 8*32(dst) ) 256 PREF( 1, 8*32(dst) )
250 bne len, rem, 1b 257 bne len, rem, 1b
@@ -253,39 +260,45 @@ EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u)
253 /* 260 /*
254 * len == rem == the number of bytes left to copy < 8*NBYTES 261 * len == rem == the number of bytes left to copy < 8*NBYTES
255 */ 262 */
256cleanup_both_aligned: 263.Lcleanup_both_aligned:
257 beqz len, done 264 beqz len, .Ldone
258 sltu t0, len, 4*NBYTES 265 sltu t0, len, 4*NBYTES
259 bnez t0, less_than_4units 266 bnez t0, .Lless_than_4units
260 and rem, len, (NBYTES-1) # rem = len % NBYTES 267 and rem, len, (NBYTES-1) # rem = len % NBYTES
261 /* 268 /*
262 * len >= 4*NBYTES 269 * len >= 4*NBYTES
263 */ 270 */
264EXC( LOAD t0, UNIT(0)(src), l_exc) 271EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
265EXC( LOAD t1, UNIT(1)(src), l_exc_copy) 272EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
266EXC( LOAD t2, UNIT(2)(src), l_exc_copy) 273EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
267EXC( LOAD t3, UNIT(3)(src), l_exc_copy) 274EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
268 SUB len, len, 4*NBYTES 275 SUB len, len, 4*NBYTES
269 ADD src, src, 4*NBYTES 276 ADD src, src, 4*NBYTES
270EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) 277 R10KCBARRIER(0(ra))
271EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) 278EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u)
272EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) 279EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u)
273EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) 280EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u)
274 beqz len, done 281EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u)
275 ADD dst, dst, 4*NBYTES 282 .set reorder /* DADDI_WAR */
276less_than_4units: 283 ADD dst, dst, 4*NBYTES
284 beqz len, .Ldone
285 .set noreorder
286.Lless_than_4units:
277 /* 287 /*
278 * rem = len % NBYTES 288 * rem = len % NBYTES
279 */ 289 */
280 beq rem, len, copy_bytes 290 beq rem, len, .Lcopy_bytes
281 nop 291 nop
2821: 2921:
283EXC( LOAD t0, 0(src), l_exc) 293 R10KCBARRIER(0(ra))
294EXC( LOAD t0, 0(src), .Ll_exc)
284 ADD src, src, NBYTES 295 ADD src, src, NBYTES
285 SUB len, len, NBYTES 296 SUB len, len, NBYTES
286EXC( STORE t0, 0(dst), s_exc_p1u) 297EXC( STORE t0, 0(dst), .Ls_exc_p1u)
298 .set reorder /* DADDI_WAR */
299 ADD dst, dst, NBYTES
287 bne rem, len, 1b 300 bne rem, len, 1b
288 ADD dst, dst, NBYTES 301 .set noreorder
289 302
290 /* 303 /*
291 * src and dst are aligned, need to copy rem bytes (rem < NBYTES) 304 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
@@ -299,17 +312,17 @@ EXC( STORE t0, 0(dst), s_exc_p1u)
299 * more instruction-level parallelism. 312 * more instruction-level parallelism.
300 */ 313 */
301#define bits t2 314#define bits t2
302 beqz len, done 315 beqz len, .Ldone
303 ADD t1, dst, len # t1 is just past last byte of dst 316 ADD t1, dst, len # t1 is just past last byte of dst
304 li bits, 8*NBYTES 317 li bits, 8*NBYTES
305 SLL rem, len, 3 # rem = number of bits to keep 318 SLL rem, len, 3 # rem = number of bits to keep
306EXC( LOAD t0, 0(src), l_exc) 319EXC( LOAD t0, 0(src), .Ll_exc)
307 SUB bits, bits, rem # bits = number of bits to discard 320 SUB bits, bits, rem # bits = number of bits to discard
308 SHIFT_DISCARD t0, t0, bits 321 SHIFT_DISCARD t0, t0, bits
309EXC( STREST t0, -1(t1), s_exc) 322EXC( STREST t0, -1(t1), .Ls_exc)
310 jr ra 323 jr ra
311 move len, zero 324 move len, zero
312dst_unaligned: 325.Ldst_unaligned:
313 /* 326 /*
314 * dst is unaligned 327 * dst is unaligned
315 * t0 = src & ADDRMASK 328 * t0 = src & ADDRMASK
@@ -320,22 +333,23 @@ dst_unaligned:
320 * Set match = (src and dst have same alignment) 333 * Set match = (src and dst have same alignment)
321 */ 334 */
322#define match rem 335#define match rem
323EXC( LDFIRST t3, FIRST(0)(src), l_exc) 336EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
324 ADD t2, zero, NBYTES 337 ADD t2, zero, NBYTES
325EXC( LDREST t3, REST(0)(src), l_exc_copy) 338EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
326 SUB t2, t2, t1 # t2 = number of bytes copied 339 SUB t2, t2, t1 # t2 = number of bytes copied
327 xor match, t0, t1 340 xor match, t0, t1
328EXC( STFIRST t3, FIRST(0)(dst), s_exc) 341 R10KCBARRIER(0(ra))
329 beq len, t2, done 342EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc)
343 beq len, t2, .Ldone
330 SUB len, len, t2 344 SUB len, len, t2
331 ADD dst, dst, t2 345 ADD dst, dst, t2
332 beqz match, both_aligned 346 beqz match, .Lboth_aligned
333 ADD src, src, t2 347 ADD src, src, t2
334 348
335src_unaligned_dst_aligned: 349.Lsrc_unaligned_dst_aligned:
336 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter 350 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
337 PREF( 0, 3*32(src) ) 351 PREF( 0, 3*32(src) )
338 beqz t0, cleanup_src_unaligned 352 beqz t0, .Lcleanup_src_unaligned
339 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 353 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
340 PREF( 1, 3*32(dst) ) 354 PREF( 1, 3*32(dst) )
3411: 3551:
@@ -345,52 +359,59 @@ src_unaligned_dst_aligned:
345 * It's OK to load FIRST(N+1) before REST(N) because the two addresses 359 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
346 * are to the same unit (unless src is aligned, but it's not). 360 * are to the same unit (unless src is aligned, but it's not).
347 */ 361 */
348EXC( LDFIRST t0, FIRST(0)(src), l_exc) 362 R10KCBARRIER(0(ra))
349EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) 363EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
364EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
350 SUB len, len, 4*NBYTES 365 SUB len, len, 4*NBYTES
351EXC( LDREST t0, REST(0)(src), l_exc_copy) 366EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
352EXC( LDREST t1, REST(1)(src), l_exc_copy) 367EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
353EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) 368EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
354EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) 369EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
355EXC( LDREST t2, REST(2)(src), l_exc_copy) 370EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
356EXC( LDREST t3, REST(3)(src), l_exc_copy) 371EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
357 PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) 372 PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
358 ADD src, src, 4*NBYTES 373 ADD src, src, 4*NBYTES
359#ifdef CONFIG_CPU_SB1 374#ifdef CONFIG_CPU_SB1
360 nop # improves slotting 375 nop # improves slotting
361#endif 376#endif
362EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) 377EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u)
363EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) 378EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u)
364EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) 379EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u)
365EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) 380EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u)
366 PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) 381 PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
382 .set reorder /* DADDI_WAR */
383 ADD dst, dst, 4*NBYTES
367 bne len, rem, 1b 384 bne len, rem, 1b
368 ADD dst, dst, 4*NBYTES 385 .set noreorder
369 386
370cleanup_src_unaligned: 387.Lcleanup_src_unaligned:
371 beqz len, done 388 beqz len, .Ldone
372 and rem, len, NBYTES-1 # rem = len % NBYTES 389 and rem, len, NBYTES-1 # rem = len % NBYTES
373 beq rem, len, copy_bytes 390 beq rem, len, .Lcopy_bytes
374 nop 391 nop
3751: 3921:
376EXC( LDFIRST t0, FIRST(0)(src), l_exc) 393 R10KCBARRIER(0(ra))
377EXC( LDREST t0, REST(0)(src), l_exc_copy) 394EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
395EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
378 ADD src, src, NBYTES 396 ADD src, src, NBYTES
379 SUB len, len, NBYTES 397 SUB len, len, NBYTES
380EXC( STORE t0, 0(dst), s_exc_p1u) 398EXC( STORE t0, 0(dst), .Ls_exc_p1u)
399 .set reorder /* DADDI_WAR */
400 ADD dst, dst, NBYTES
381 bne len, rem, 1b 401 bne len, rem, 1b
382 ADD dst, dst, NBYTES 402 .set noreorder
383 403
384copy_bytes_checklen: 404.Lcopy_bytes_checklen:
385 beqz len, done 405 beqz len, .Ldone
386 nop 406 nop
387copy_bytes: 407.Lcopy_bytes:
388 /* 0 < len < NBYTES */ 408 /* 0 < len < NBYTES */
409 R10KCBARRIER(0(ra))
389#define COPY_BYTE(N) \ 410#define COPY_BYTE(N) \
390EXC( lb t0, N(src), l_exc); \ 411EXC( lb t0, N(src), .Ll_exc); \
391 SUB len, len, 1; \ 412 SUB len, len, 1; \
392 beqz len, done; \ 413 beqz len, .Ldone; \
393EXC( sb t0, N(dst), s_exc_p1) 414EXC( sb t0, N(dst), .Ls_exc_p1)
394 415
395 COPY_BYTE(0) 416 COPY_BYTE(0)
396 COPY_BYTE(1) 417 COPY_BYTE(1)
@@ -400,16 +421,16 @@ EXC( sb t0, N(dst), s_exc_p1)
400 COPY_BYTE(4) 421 COPY_BYTE(4)
401 COPY_BYTE(5) 422 COPY_BYTE(5)
402#endif 423#endif
403EXC( lb t0, NBYTES-2(src), l_exc) 424EXC( lb t0, NBYTES-2(src), .Ll_exc)
404 SUB len, len, 1 425 SUB len, len, 1
405 jr ra 426 jr ra
406EXC( sb t0, NBYTES-2(dst), s_exc_p1) 427EXC( sb t0, NBYTES-2(dst), .Ls_exc_p1)
407done: 428.Ldone:
408 jr ra 429 jr ra
409 nop 430 nop
410 END(memcpy) 431 END(memcpy)
411 432
412l_exc_copy: 433.Ll_exc_copy:
413 /* 434 /*
414 * Copy bytes from src until faulting load address (or until a 435 * Copy bytes from src until faulting load address (or until a
415 * lb faults) 436 * lb faults)
@@ -424,12 +445,14 @@ l_exc_copy:
424 nop 445 nop
425 LOAD t0, THREAD_BUADDR(t0) 446 LOAD t0, THREAD_BUADDR(t0)
4261: 4471:
427EXC( lb t1, 0(src), l_exc) 448EXC( lb t1, 0(src), .Ll_exc)
428 ADD src, src, 1 449 ADD src, src, 1
429 sb t1, 0(dst) # can't fault -- we're copy_from_user 450 sb t1, 0(dst) # can't fault -- we're copy_from_user
451 .set reorder /* DADDI_WAR */
452 ADD dst, dst, 1
430 bne src, t0, 1b 453 bne src, t0, 1b
431 ADD dst, dst, 1 454 .set noreorder
432l_exc: 455.Ll_exc:
433 LOAD t0, TI_TASK($28) 456 LOAD t0, TI_TASK($28)
434 nop 457 nop
435 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address 458 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
@@ -446,20 +469,33 @@ l_exc:
446 * Clear len bytes starting at dst. Can't call __bzero because it 469 * Clear len bytes starting at dst. Can't call __bzero because it
447 * might modify len. An inefficient loop for these rare times... 470 * might modify len. An inefficient loop for these rare times...
448 */ 471 */
449 beqz len, done 472 .set reorder /* DADDI_WAR */
450 SUB src, len, 1 473 SUB src, len, 1
474 beqz len, .Ldone
475 .set noreorder
4511: sb zero, 0(dst) 4761: sb zero, 0(dst)
452 ADD dst, dst, 1 477 ADD dst, dst, 1
478#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
453 bnez src, 1b 479 bnez src, 1b
454 SUB src, src, 1 480 SUB src, src, 1
481#else
482 .set push
483 .set noat
484 li v1, 1
485 bnez src, 1b
486 SUB src, src, v1
487 .set pop
488#endif
455 jr ra 489 jr ra
456 nop 490 nop
457 491
458 492
459#define SEXC(n) \ 493#define SEXC(n) \
460s_exc_p ## n ## u: \ 494 .set reorder; /* DADDI_WAR */ \
461 jr ra; \ 495.Ls_exc_p ## n ## u: \
462 ADD len, len, n*NBYTES 496 ADD len, len, n*NBYTES; \
497 jr ra; \
498 .set noreorder
463 499
464SEXC(8) 500SEXC(8)
465SEXC(7) 501SEXC(7)
@@ -470,10 +506,12 @@ SEXC(3)
470SEXC(2) 506SEXC(2)
471SEXC(1) 507SEXC(1)
472 508
473s_exc_p1: 509.Ls_exc_p1:
510 .set reorder /* DADDI_WAR */
511 ADD len, len, 1
474 jr ra 512 jr ra
475 ADD len, len, 1 513 .set noreorder
476s_exc: 514.Ls_exc:
477 jr ra 515 jr ra
478 nop 516 nop
479 517
@@ -484,38 +522,44 @@ LEAF(memmove)
484 sltu t0, a1, t0 # dst + len <= src -> memcpy 522 sltu t0, a1, t0 # dst + len <= src -> memcpy
485 sltu t1, a0, t1 # dst >= src + len -> memcpy 523 sltu t1, a0, t1 # dst >= src + len -> memcpy
486 and t0, t1 524 and t0, t1
487 beqz t0, __memcpy 525 beqz t0, .L__memcpy
488 move v0, a0 /* return value */ 526 move v0, a0 /* return value */
489 beqz a2, r_out 527 beqz a2, .Lr_out
490 END(memmove) 528 END(memmove)
491 529
492 /* fall through to __rmemcpy */ 530 /* fall through to __rmemcpy */
493LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ 531LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
494 sltu t0, a1, a0 532 sltu t0, a1, a0
495 beqz t0, r_end_bytes_up # src >= dst 533 beqz t0, .Lr_end_bytes_up # src >= dst
496 nop 534 nop
497 ADD a0, a2 # dst = dst + len 535 ADD a0, a2 # dst = dst + len
498 ADD a1, a2 # src = src + len 536 ADD a1, a2 # src = src + len
499 537
500r_end_bytes: 538.Lr_end_bytes:
539 R10KCBARRIER(0(ra))
501 lb t0, -1(a1) 540 lb t0, -1(a1)
502 SUB a2, a2, 0x1 541 SUB a2, a2, 0x1
503 sb t0, -1(a0) 542 sb t0, -1(a0)
504 SUB a1, a1, 0x1 543 SUB a1, a1, 0x1
505 bnez a2, r_end_bytes 544 .set reorder /* DADDI_WAR */
506 SUB a0, a0, 0x1 545 SUB a0, a0, 0x1
546 bnez a2, .Lr_end_bytes
547 .set noreorder
507 548
508r_out: 549.Lr_out:
509 jr ra 550 jr ra
510 move a2, zero 551 move a2, zero
511 552
512r_end_bytes_up: 553.Lr_end_bytes_up:
554 R10KCBARRIER(0(ra))
513 lb t0, (a1) 555 lb t0, (a1)
514 SUB a2, a2, 0x1 556 SUB a2, a2, 0x1
515 sb t0, (a0) 557 sb t0, (a0)
516 ADD a1, a1, 0x1 558 ADD a1, a1, 0x1
517 bnez a2, r_end_bytes_up 559 .set reorder /* DADDI_WAR */
518 ADD a0, a0, 0x1 560 ADD a0, a0, 0x1
561 bnez a2, .Lr_end_bytes_up
562 .set noreorder
519 563
520 jr ra 564 jr ra
521 move a2, zero 565 move a2, zero
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 3f8b8b3d0b23..77dc3b20110a 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle 6 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2007 Maciej W. Rozycki
8 */ 9 */
9#include <asm/asm.h> 10#include <asm/asm.h>
10#include <asm/asm-offsets.h> 11#include <asm/asm-offsets.h>
@@ -71,34 +72,45 @@ LEAF(memset)
71 72
72FEXPORT(__bzero) 73FEXPORT(__bzero)
73 sltiu t0, a2, LONGSIZE /* very small region? */ 74 sltiu t0, a2, LONGSIZE /* very small region? */
74 bnez t0, small_memset 75 bnez t0, .Lsmall_memset
75 andi t0, a0, LONGMASK /* aligned? */ 76 andi t0, a0, LONGMASK /* aligned? */
76 77
78#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
77 beqz t0, 1f 79 beqz t0, 1f
78 PTR_SUBU t0, LONGSIZE /* alignment in bytes */ 80 PTR_SUBU t0, LONGSIZE /* alignment in bytes */
81#else
82 .set noat
83 li AT, LONGSIZE
84 beqz t0, 1f
85 PTR_SUBU t0, AT /* alignment in bytes */
86 .set at
87#endif
79 88
89 R10KCBARRIER(0(ra))
80#ifdef __MIPSEB__ 90#ifdef __MIPSEB__
81 EX(LONG_S_L, a1, (a0), first_fixup) /* make word/dword aligned */ 91 EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
82#endif 92#endif
83#ifdef __MIPSEL__ 93#ifdef __MIPSEL__
84 EX(LONG_S_R, a1, (a0), first_fixup) /* make word/dword aligned */ 94 EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
85#endif 95#endif
86 PTR_SUBU a0, t0 /* long align ptr */ 96 PTR_SUBU a0, t0 /* long align ptr */
87 PTR_ADDU a2, t0 /* correct size */ 97 PTR_ADDU a2, t0 /* correct size */
88 98
891: ori t1, a2, 0x3f /* # of full blocks */ 991: ori t1, a2, 0x3f /* # of full blocks */
90 xori t1, 0x3f 100 xori t1, 0x3f
91 beqz t1, memset_partial /* no block to fill */ 101 beqz t1, .Lmemset_partial /* no block to fill */
92 andi t0, a2, 0x40-LONGSIZE 102 andi t0, a2, 0x40-LONGSIZE
93 103
94 PTR_ADDU t1, a0 /* end address */ 104 PTR_ADDU t1, a0 /* end address */
95 .set reorder 105 .set reorder
961: PTR_ADDIU a0, 64 1061: PTR_ADDIU a0, 64
97 f_fill64 a0, -64, a1, fwd_fixup 107 R10KCBARRIER(0(ra))
108 f_fill64 a0, -64, a1, .Lfwd_fixup
98 bne t1, a0, 1b 109 bne t1, a0, 1b
99 .set noreorder 110 .set noreorder
100 111
101memset_partial: 112.Lmemset_partial:
113 R10KCBARRIER(0(ra))
102 PTR_LA t1, 2f /* where to start */ 114 PTR_LA t1, 2f /* where to start */
103#if LONGSIZE == 4 115#if LONGSIZE == 4
104 PTR_SUBU t1, t0 116 PTR_SUBU t1, t0
@@ -106,7 +118,7 @@ memset_partial:
106 .set noat 118 .set noat
107 LONG_SRL AT, t0, 1 119 LONG_SRL AT, t0, 1
108 PTR_SUBU t1, AT 120 PTR_SUBU t1, AT
109 .set noat 121 .set at
110#endif 122#endif
111 jr t1 123 jr t1
112 PTR_ADDU a0, t0 /* dest ptr */ 124 PTR_ADDU a0, t0 /* dest ptr */
@@ -114,26 +126,28 @@ memset_partial:
114 .set push 126 .set push
115 .set noreorder 127 .set noreorder
116 .set nomacro 128 .set nomacro
117 f_fill64 a0, -64, a1, partial_fixup /* ... but first do longs ... */ 129 f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */
1182: .set pop 1302: .set pop
119 andi a2, LONGMASK /* At most one long to go */ 131 andi a2, LONGMASK /* At most one long to go */
120 132
121 beqz a2, 1f 133 beqz a2, 1f
122 PTR_ADDU a0, a2 /* What's left */ 134 PTR_ADDU a0, a2 /* What's left */
135 R10KCBARRIER(0(ra))
123#ifdef __MIPSEB__ 136#ifdef __MIPSEB__
124 EX(LONG_S_R, a1, -1(a0), last_fixup) 137 EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
125#endif 138#endif
126#ifdef __MIPSEL__ 139#ifdef __MIPSEL__
127 EX(LONG_S_L, a1, -1(a0), last_fixup) 140 EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
128#endif 141#endif
1291: jr ra 1421: jr ra
130 move a2, zero 143 move a2, zero
131 144
132small_memset: 145.Lsmall_memset:
133 beqz a2, 2f 146 beqz a2, 2f
134 PTR_ADDU t1, a0, a2 147 PTR_ADDU t1, a0, a2
135 148
1361: PTR_ADDIU a0, 1 /* fill bytewise */ 1491: PTR_ADDIU a0, 1 /* fill bytewise */
150 R10KCBARRIER(0(ra))
137 bne t1, a0, 1b 151 bne t1, a0, 1b
138 sb a1, -1(a0) 152 sb a1, -1(a0)
139 153
@@ -141,11 +155,11 @@ small_memset:
141 move a2, zero 155 move a2, zero
142 END(memset) 156 END(memset)
143 157
144first_fixup: 158.Lfirst_fixup:
145 jr ra 159 jr ra
146 nop 160 nop
147 161
148fwd_fixup: 162.Lfwd_fixup:
149 PTR_L t0, TI_TASK($28) 163 PTR_L t0, TI_TASK($28)
150 LONG_L t0, THREAD_BUADDR(t0) 164 LONG_L t0, THREAD_BUADDR(t0)
151 andi a2, 0x3f 165 andi a2, 0x3f
@@ -153,7 +167,7 @@ fwd_fixup:
153 jr ra 167 jr ra
154 LONG_SUBU a2, t0 168 LONG_SUBU a2, t0
155 169
156partial_fixup: 170.Lpartial_fixup:
157 PTR_L t0, TI_TASK($28) 171 PTR_L t0, TI_TASK($28)
158 LONG_L t0, THREAD_BUADDR(t0) 172 LONG_L t0, THREAD_BUADDR(t0)
159 andi a2, LONGMASK 173 andi a2, LONGMASK
@@ -161,6 +175,6 @@ partial_fixup:
161 jr ra 175 jr ra
162 LONG_SUBU a2, t0 176 LONG_SUBU a2, t0
163 177
164last_fixup: 178.Llast_fixup:
165 jr ra 179 jr ra
166 andi v1, a2, LONGMASK 180 andi v1, a2, LONGMASK
diff --git a/arch/mips/lib/strlen_user.S b/arch/mips/lib/strlen_user.S
index eca558d83a37..fdbb970f670d 100644
--- a/arch/mips/lib/strlen_user.S
+++ b/arch/mips/lib/strlen_user.S
@@ -24,16 +24,16 @@
24LEAF(__strlen_user_asm) 24LEAF(__strlen_user_asm)
25 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? 25 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
26 and v0, a0 26 and v0, a0
27 bnez v0, fault 27 bnez v0, .Lfault
28 28
29FEXPORT(__strlen_user_nocheck_asm) 29FEXPORT(__strlen_user_nocheck_asm)
30 move v0, a0 30 move v0, a0
311: EX(lb, t0, (v0), fault) 311: EX(lb, t0, (v0), .Lfault)
32 PTR_ADDIU v0, 1 32 PTR_ADDIU v0, 1
33 bnez t0, 1b 33 bnez t0, 1b
34 PTR_SUBU v0, a0 34 PTR_SUBU v0, a0
35 jr ra 35 jr ra
36 END(__strlen_user_asm) 36 END(__strlen_user_asm)
37 37
38fault: move v0, zero 38.Lfault: move v0, zero
39 jr ra 39 jr ra
diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S
index d16c76fbfac7..7201b2ff08c8 100644
--- a/arch/mips/lib/strncpy_user.S
+++ b/arch/mips/lib/strncpy_user.S
@@ -30,29 +30,30 @@
30LEAF(__strncpy_from_user_asm) 30LEAF(__strncpy_from_user_asm)
31 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? 31 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
32 and v0, a1 32 and v0, a1
33 bnez v0, fault 33 bnez v0, .Lfault
34 34
35FEXPORT(__strncpy_from_user_nocheck_asm) 35FEXPORT(__strncpy_from_user_nocheck_asm)
36 move v0, zero 36 move v0, zero
37 move v1, a1 37 move v1, a1
38 .set noreorder 38 .set noreorder
391: EX(lbu, t0, (v1), fault) 391: EX(lbu, t0, (v1), .Lfault)
40 PTR_ADDIU v1, 1 40 PTR_ADDIU v1, 1
41 R10KCBARRIER(0(ra))
41 beqz t0, 2f 42 beqz t0, 2f
42 sb t0, (a0) 43 sb t0, (a0)
43 PTR_ADDIU v0, 1 44 PTR_ADDIU v0, 1
44 bne v0, a2, 1b
45 PTR_ADDIU a0, 1
46 .set reorder 45 .set reorder
46 PTR_ADDIU a0, 1
47 bne v0, a2, 1b
472: PTR_ADDU t0, a1, v0 482: PTR_ADDU t0, a1, v0
48 xor t0, a1 49 xor t0, a1
49 bltz t0, fault 50 bltz t0, .Lfault
50 jr ra # return n 51 jr ra # return n
51 END(__strncpy_from_user_asm) 52 END(__strncpy_from_user_asm)
52 53
53fault: li v0, -EFAULT 54.Lfault: li v0, -EFAULT
54 jr ra 55 jr ra
55 56
56 .section __ex_table,"a" 57 .section __ex_table,"a"
57 PTR 1b, fault 58 PTR 1b, .Lfault
58 .previous 59 .previous
diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index c0ea15194a0e..c768e3000616 100644
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -28,18 +28,19 @@
28LEAF(__strnlen_user_asm) 28LEAF(__strnlen_user_asm)
29 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? 29 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
30 and v0, a0 30 and v0, a0
31 bnez v0, fault 31 bnez v0, .Lfault
32 32
33FEXPORT(__strnlen_user_nocheck_asm) 33FEXPORT(__strnlen_user_nocheck_asm)
34 move v0, a0 34 move v0, a0
35 PTR_ADDU a1, a0 # stop pointer 35 PTR_ADDU a1, a0 # stop pointer
361: beq v0, a1, 1f # limit reached? 361: beq v0, a1, 1f # limit reached?
37 EX(lb, t0, (v0), fault) 37 EX(lb, t0, (v0), .Lfault)
38 PTR_ADDU v0, 1 38 PTR_ADDU v0, 1
39 bnez t0, 1b 39 bnez t0, 1b
401: PTR_SUBU v0, a0 401: PTR_SUBU v0, a0
41 jr ra 41 jr ra
42 END(__strnlen_user_asm) 42 END(__strnlen_user_asm)
43 43
44fault: move v0, zero 44.Lfault:
45 move v0, zero
45 jr ra 46 jr ra
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 58d14f4d9349..27b012d4341c 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -46,9 +46,9 @@ unsigned long __init run_uncached(void *func)
46 if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) 46 if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
47 usp = CKSEG1ADDR(sp); 47 usp = CKSEG1ADDR(sp);
48#ifdef CONFIG_64BIT 48#ifdef CONFIG_64BIT
49 else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) && 49 else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0) &&
50 (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0)) 50 (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0))
51 usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, 51 usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
52 XKPHYS_TO_PHYS((long long)sp)); 52 XKPHYS_TO_PHYS((long long)sp));
53#endif 53#endif
54 else { 54 else {
@@ -58,9 +58,9 @@ unsigned long __init run_uncached(void *func)
58 if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2) 58 if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
59 ufunc = CKSEG1ADDR(lfunc); 59 ufunc = CKSEG1ADDR(lfunc);
60#ifdef CONFIG_64BIT 60#ifdef CONFIG_64BIT
61 else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) && 61 else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0, 0) &&
62 (long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0)) 62 (long long)lfunc < (long long)PHYS_TO_XKPHYS(8, 0))
63 ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, 63 ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
64 XKPHYS_TO_PHYS((long long)lfunc)); 64 XKPHYS_TO_PHYS((long long)lfunc));
65#endif 65#endif
66 else { 66 else {
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index e405d112a067..5c500802271e 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -34,12 +34,6 @@
34#include <asm/time.h> 34#include <asm/time.h>
35#include <asm/traps.h> 35#include <asm/traps.h>
36 36
37extern void mips_reboot_setup(void);
38
39#ifdef CONFIG_KGDB
40extern void kgdb_config(void);
41#endif
42
43static void __init serial_init(void); 37static void __init serial_init(void);
44 38
45const char *get_system_type(void) 39const char *get_system_type(void)
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 30f1f54cb68b..1695dca5506b 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -250,6 +250,8 @@ void __init mips_ejtag_setup(void)
250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 250 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
251} 251}
252 252
253extern struct plat_smp_ops msmtc_smp_ops;
254
253void __init prom_init(void) 255void __init prom_init(void)
254{ 256{
255 prom_argc = fw_arg0; 257 prom_argc = fw_arg0;
@@ -416,4 +418,10 @@ void __init prom_init(void)
416#ifdef CONFIG_SERIAL_8250_CONSOLE 418#ifdef CONFIG_SERIAL_8250_CONSOLE
417 console_config(); 419 console_config();
418#endif 420#endif
421#ifdef CONFIG_MIPS_MT_SMP
422 register_smp_ops(&vsmp_smp_ops);
423#endif
424#ifdef CONFIG_MIPS_MT_SMTC
425 register_smp_ops(&msmtc_smp_ops);
426#endif
419} 427}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index f010261b75d8..dbe60eb55e29 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -26,13 +26,13 @@
26#include <linux/sched.h> 26#include <linux/sched.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/io.h>
29#include <linux/kernel_stat.h> 30#include <linux/kernel_stat.h>
30#include <linux/kernel.h> 31#include <linux/kernel.h>
31#include <linux/random.h> 32#include <linux/random.h>
32 33
33#include <asm/i8259.h> 34#include <asm/i8259.h>
34#include <asm/irq_cpu.h> 35#include <asm/irq_cpu.h>
35#include <asm/io.h>
36#include <asm/irq_regs.h> 36#include <asm/irq_regs.h>
37#include <asm/mips-boards/malta.h> 37#include <asm/mips-boards/malta.h>
38#include <asm/mips-boards/maltaint.h> 38#include <asm/mips-boards/maltaint.h>
@@ -47,7 +47,7 @@ static DEFINE_SPINLOCK(mips_irq_lock);
47static inline int mips_pcibios_iack(void) 47static inline int mips_pcibios_iack(void)
48{ 48{
49 int irq; 49 int irq;
50 u32 dummy; 50 u32 dummy;
51 51
52 /* 52 /*
53 * Determine highest priority pending interrupt by performing 53 * Determine highest priority pending interrupt by performing
@@ -58,7 +58,7 @@ static inline int mips_pcibios_iack(void)
58 case MIPS_REVISION_SCON_ROCIT: 58 case MIPS_REVISION_SCON_ROCIT:
59 case MIPS_REVISION_SCON_SOCITSC: 59 case MIPS_REVISION_SCON_SOCITSC:
60 case MIPS_REVISION_SCON_SOCITSCP: 60 case MIPS_REVISION_SCON_SOCITSCP:
61 MSC_READ(MSC01_PCI_IACK, irq); 61 MSC_READ(MSC01_PCI_IACK, irq);
62 irq &= 0xff; 62 irq &= 0xff;
63 break; 63 break;
64 case MIPS_REVISION_SCON_GT64120: 64 case MIPS_REVISION_SCON_GT64120:
@@ -83,7 +83,7 @@ static inline int mips_pcibios_iack(void)
83 BONITO_PCIMAP_CFG = 0; 83 BONITO_PCIMAP_CFG = 0;
84 break; 84 break;
85 default: 85 default:
86 printk("Unknown system controller.\n"); 86 printk(KERN_WARNING "Unknown system controller.\n");
87 return -1; 87 return -1;
88 } 88 }
89 return irq; 89 return irq;
@@ -114,7 +114,8 @@ static void malta_hw0_irqdispatch(void)
114 114
115 irq = get_int(); 115 irq = get_int();
116 if (irq < 0) { 116 if (irq < 0) {
117 return; /* interrupt has already been cleared */ 117 /* interrupt has already been cleared */
118 return;
118 } 119 }
119 120
120 do_IRQ(MALTA_INT_BASE + irq); 121 do_IRQ(MALTA_INT_BASE + irq);
@@ -123,15 +124,15 @@ static void malta_hw0_irqdispatch(void)
123static void corehi_irqdispatch(void) 124static void corehi_irqdispatch(void)
124{ 125{
125 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 126 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
126 unsigned int pcimstat, intisr, inten, intpol; 127 unsigned int pcimstat, intisr, inten, intpol;
127 unsigned int intrcause, datalo, datahi; 128 unsigned int intrcause, datalo, datahi;
128 struct pt_regs *regs = get_irq_regs(); 129 struct pt_regs *regs = get_irq_regs();
129 130
130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 131 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
131 printk("epc : %08lx\nStatus: %08lx\n" 132 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
132 "Cause : %08lx\nbadVaddr : %08lx\n", 133 "Cause : %08lx\nbadVaddr : %08lx\n",
133 regs->cp0_epc, regs->cp0_status, 134 regs->cp0_epc, regs->cp0_status,
134 regs->cp0_cause, regs->cp0_badvaddr); 135 regs->cp0_cause, regs->cp0_badvaddr);
135 136
136 /* Read all the registers and then print them as there is a 137 /* Read all the registers and then print them as there is a
137 problem with interspersed printk's upsetting the Bonito controller. 138 problem with interspersed printk's upsetting the Bonito controller.
@@ -139,41 +140,41 @@ static void corehi_irqdispatch(void)
139 */ 140 */
140 141
141 switch (mips_revision_sconid) { 142 switch (mips_revision_sconid) {
142 case MIPS_REVISION_SCON_SOCIT: 143 case MIPS_REVISION_SCON_SOCIT:
143 case MIPS_REVISION_SCON_ROCIT: 144 case MIPS_REVISION_SCON_ROCIT:
144 case MIPS_REVISION_SCON_SOCITSC: 145 case MIPS_REVISION_SCON_SOCITSC:
145 case MIPS_REVISION_SCON_SOCITSCP: 146 case MIPS_REVISION_SCON_SOCITSCP:
146 ll_msc_irq(); 147 ll_msc_irq();
147 break; 148 break;
148 case MIPS_REVISION_SCON_GT64120: 149 case MIPS_REVISION_SCON_GT64120:
149 intrcause = GT_READ(GT_INTRCAUSE_OFS); 150 intrcause = GT_READ(GT_INTRCAUSE_OFS);
150 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 151 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
151 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 152 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
152 printk("GT_INTRCAUSE = %08x\n", intrcause); 153 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
153 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); 154 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
154 break; 155 datahi, datalo);
155 case MIPS_REVISION_SCON_BONITO: 156 break;
156 pcibadaddr = BONITO_PCIBADADDR; 157 case MIPS_REVISION_SCON_BONITO:
157 pcimstat = BONITO_PCIMSTAT; 158 pcibadaddr = BONITO_PCIBADADDR;
158 intisr = BONITO_INTISR; 159 pcimstat = BONITO_PCIMSTAT;
159 inten = BONITO_INTEN; 160 intisr = BONITO_INTISR;
160 intpol = BONITO_INTPOL; 161 inten = BONITO_INTEN;
161 intedge = BONITO_INTEDGE; 162 intpol = BONITO_INTPOL;
162 intsteer = BONITO_INTSTEER; 163 intedge = BONITO_INTEDGE;
163 pcicmd = BONITO_PCICMD; 164 intsteer = BONITO_INTSTEER;
164 printk("BONITO_INTISR = %08x\n", intisr); 165 pcicmd = BONITO_PCICMD;
165 printk("BONITO_INTEN = %08x\n", inten); 166 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
166 printk("BONITO_INTPOL = %08x\n", intpol); 167 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
167 printk("BONITO_INTEDGE = %08x\n", intedge); 168 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
168 printk("BONITO_INTSTEER = %08x\n", intsteer); 169 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
169 printk("BONITO_PCICMD = %08x\n", pcicmd); 170 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
170 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); 171 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
171 printk("BONITO_PCIMSTAT = %08x\n", pcimstat); 172 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
172 break; 173 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
173 } 174 break;
174 175 }
175 /* We die here*/ 176
176 die("CoreHi interrupt", regs); 177 die("CoreHi interrupt", regs);
177} 178}
178 179
179static inline int clz(unsigned long x) 180static inline int clz(unsigned long x)
@@ -214,9 +215,9 @@ static inline unsigned int irq_ffs(unsigned int pending)
214 215
215 t0 = pending & 0x8000; 216 t0 = pending & 0x8000;
216 t0 = t0 < 1; 217 t0 = t0 < 1;
217 //t0 = t0 << 2; 218 /* t0 = t0 << 2; */
218 a0 = a0 - t0; 219 a0 = a0 - t0;
219 //pending = pending << t0; 220 /* pending = pending << t0; */
220 221
221 return a0; 222 return a0;
222#endif 223#endif
@@ -299,21 +300,29 @@ void __init arch_init_irq(void)
299 if (!cpu_has_veic) 300 if (!cpu_has_veic)
300 mips_cpu_irq_init(); 301 mips_cpu_irq_init();
301 302
302 switch(mips_revision_sconid) { 303 switch (mips_revision_sconid) {
303 case MIPS_REVISION_SCON_SOCIT: 304 case MIPS_REVISION_SCON_SOCIT:
304 case MIPS_REVISION_SCON_ROCIT: 305 case MIPS_REVISION_SCON_ROCIT:
305 if (cpu_has_veic) 306 if (cpu_has_veic)
306 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 307 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
308 MSC01E_INT_BASE, msc_eicirqmap,
309 msc_nr_eicirqs);
307 else 310 else
308 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 311 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
312 MSC01C_INT_BASE, msc_irqmap,
313 msc_nr_irqs);
309 break; 314 break;
310 315
311 case MIPS_REVISION_SCON_SOCITSC: 316 case MIPS_REVISION_SCON_SOCITSC:
312 case MIPS_REVISION_SCON_SOCITSCP: 317 case MIPS_REVISION_SCON_SOCITSCP:
313 if (cpu_has_veic) 318 if (cpu_has_veic)
314 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 319 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
320 MSC01E_INT_BASE, msc_eicirqmap,
321 msc_nr_eicirqs);
315 else 322 else
316 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 323 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
324 MSC01C_INT_BASE, msc_irqmap,
325 msc_nr_irqs);
317 } 326 }
318 327
319 if (cpu_has_veic) { 328 if (cpu_has_veic) {
@@ -321,8 +330,7 @@ void __init arch_init_irq(void)
321 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); 330 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
322 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 331 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
323 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 332 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
324 } 333 } else if (cpu_has_vint) {
325 else if (cpu_has_vint) {
326 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 334 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); 335 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 336#ifdef CONFIG_MIPS_MT_SMTC
@@ -344,11 +352,12 @@ void __init arch_init_irq(void)
344 } 352 }
345#else /* Not SMTC */ 353#else /* Not SMTC */
346 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 354 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
347 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 355 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
356 &corehi_irqaction);
348#endif /* CONFIG_MIPS_MT_SMTC */ 357#endif /* CONFIG_MIPS_MT_SMTC */
349 } 358 } else {
350 else {
351 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 359 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
352 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 360 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
361 &corehi_irqaction);
353 } 362 }
354} 363}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index bc43a5c2224d..2cd8f5734b36 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) Dmitri Vorobiev
4 * 5 *
5 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -15,39 +16,57 @@
15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 */ 18 */
19#include <linux/cpu.h>
18#include <linux/init.h> 20#include <linux/init.h>
19#include <linux/sched.h> 21#include <linux/sched.h>
20#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/irq.h>
21#include <linux/pci.h> 24#include <linux/pci.h>
22#include <linux/screen_info.h> 25#include <linux/screen_info.h>
26#include <linux/time.h>
23 27
24#include <asm/cpu.h>
25#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
26#include <asm/irq.h>
27#include <asm/mips-boards/generic.h> 29#include <asm/mips-boards/generic.h>
28#include <asm/mips-boards/prom.h> 30#include <asm/mips-boards/prom.h>
29#include <asm/mips-boards/malta.h> 31#include <asm/mips-boards/malta.h>
30#include <asm/mips-boards/maltaint.h> 32#include <asm/mips-boards/maltaint.h>
31#include <asm/dma.h> 33#include <asm/dma.h>
32#include <asm/time.h>
33#include <asm/traps.h> 34#include <asm/traps.h>
34#ifdef CONFIG_VT 35#ifdef CONFIG_VT
35#include <linux/console.h> 36#include <linux/console.h>
36#endif 37#endif
37 38
38extern void mips_reboot_setup(void);
39extern unsigned long mips_rtc_get_time(void);
40
41#ifdef CONFIG_KGDB
42extern void kgdb_config(void);
43#endif
44
45struct resource standard_io_resources[] = { 39struct resource standard_io_resources[] = {
46 { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY }, 40 {
47 { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY }, 41 .name = "dma1",
48 { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY }, 42 .start = 0x00,
49 { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY }, 43 .end = 0x1f,
50 { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY }, 44 .flags = IORESOURCE_BUSY
45 },
46 {
47 .name = "timer",
48 .start = 0x40,
49 .end = 0x5f,
50 .flags = IORESOURCE_BUSY
51 },
52 {
53 .name = "keyboard",
54 .start = 0x60,
55 .end = 0x6f,
56 .flags = IORESOURCE_BUSY
57 },
58 {
59 .name = "dma page reg",
60 .start = 0x80,
61 .end = 0x8f,
62 .flags = IORESOURCE_BUSY
63 },
64 {
65 .name = "dma2",
66 .start = 0xc0,
67 .end = 0xdf,
68 .flags = IORESOURCE_BUSY
69 },
51}; 70};
52 71
53const char *get_system_type(void) 72const char *get_system_type(void)
@@ -62,7 +81,7 @@ const char display_string[] = " LINUX ON MALTA ";
62#endif /* CONFIG_MIPS_MT_SMTC */ 81#endif /* CONFIG_MIPS_MT_SMTC */
63 82
64#ifdef CONFIG_BLK_DEV_FD 83#ifdef CONFIG_BLK_DEV_FD
65void __init fd_activate(void) 84static void __init fd_activate(void)
66{ 85{
67 /* 86 /*
68 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O 87 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
@@ -83,6 +102,85 @@ void __init fd_activate(void)
83} 102}
84#endif 103#endif
85 104
105#ifdef CONFIG_BLK_DEV_IDE
106static void __init pci_clock_check(void)
107{
108 unsigned int __iomem *jmpr_p =
109 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
110 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
111 static const int pciclocks[] __initdata = {
112 33, 20, 25, 30, 12, 16, 37, 10
113 };
114 int pciclock = pciclocks[jmpr];
115 char *argptr = prom_getcmdline();
116
117 if (pciclock != 33 && !strstr(argptr, "idebus=")) {
118 printk(KERN_WARNING "WARNING: PCI clock is %dMHz, "
119 "setting idebus\n", pciclock);
120 argptr += strlen(argptr);
121 sprintf(argptr, " idebus=%d", pciclock);
122 if (pciclock < 20 || pciclock > 66)
123 printk(KERN_WARNING "WARNING: IDE timing "
124 "calculations will be incorrect\n");
125 }
126}
127#endif
128
129#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
130static void __init screen_info_setup(void)
131{
132 screen_info = (struct screen_info) {
133 .orig_x = 0,
134 .orig_y = 25,
135 .ext_mem_k = 0,
136 .orig_video_page = 0,
137 .orig_video_mode = 0,
138 .orig_video_cols = 80,
139 .unused2 = 0,
140 .orig_video_ega_bx = 0,
141 .unused3 = 0,
142 .orig_video_lines = 25,
143 .orig_video_isVGA = VIDEO_TYPE_VGAC,
144 .orig_video_points = 16
145 };
146}
147#endif
148
149static void __init bonito_quirks_setup(void)
150{
151 char *argptr;
152
153 argptr = prom_getcmdline();
154 if (strstr(argptr, "debug")) {
155 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
156 printk(KERN_INFO "Enabled Bonito debug mode\n");
157 } else
158 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
159
160#ifdef CONFIG_DMA_COHERENT
161 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
162 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
163 printk(KERN_INFO "Enabled Bonito CPU coherency\n");
164
165 argptr = prom_getcmdline();
166 if (strstr(argptr, "iobcuncached")) {
167 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
168 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
169 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
170 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
171 printk(KERN_INFO "Disabled Bonito IOBC coherency\n");
172 } else {
173 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
174 BONITO_PCIMEMBASECFG |=
175 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
176 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
177 printk(KERN_INFO "Enabled Bonito IOBC coherency\n");
178 }
179 } else
180 panic("Hardware DMA cache coherency not supported");
181#endif
182}
183
86void __init plat_mem_setup(void) 184void __init plat_mem_setup(void)
87{ 185{
88 unsigned int i; 186 unsigned int i;
@@ -102,86 +200,24 @@ void __init plat_mem_setup(void)
102 kgdb_config(); 200 kgdb_config();
103#endif 201#endif
104 202
105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
106 char *argptr;
107
108 argptr = prom_getcmdline();
109 if (strstr(argptr, "debug")) {
110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
111 printk("Enabled Bonito debug mode\n");
112 }
113 else
114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
115
116#ifdef CONFIG_DMA_COHERENT
117 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
118 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
119 printk("Enabled Bonito CPU coherency\n");
120
121 argptr = prom_getcmdline();
122 if (strstr(argptr, "iobcuncached")) {
123 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
124 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
125 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
126 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
127 printk("Disabled Bonito IOBC coherency\n");
128 }
129 else {
130 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
131 BONITO_PCIMEMBASECFG |=
132 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
133 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
134 printk("Enabled Bonito IOBC coherency\n");
135 }
136 }
137 else
138 panic("Hardware DMA cache coherency not supported");
139
140#endif
141 }
142#ifdef CONFIG_DMA_COHERENT 203#ifdef CONFIG_DMA_COHERENT
143 else { 204 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
144 panic("Hardware DMA cache coherency not supported"); 205 panic("Hardware DMA cache coherency not supported");
145 }
146#endif 206#endif
147 207
208 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
209 bonito_quirks_setup();
210
148#ifdef CONFIG_BLK_DEV_IDE 211#ifdef CONFIG_BLK_DEV_IDE
149 /* Check PCI clock */ 212 pci_clock_check();
150 {
151 unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
152 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
153 static const int pciclocks[] __initdata = {
154 33, 20, 25, 30, 12, 16, 37, 10
155 };
156 int pciclock = pciclocks[jmpr];
157 char *argptr = prom_getcmdline();
158
159 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
161 argptr += strlen(argptr);
162 sprintf(argptr, " idebus=%d", pciclock);
163 if (pciclock < 20 || pciclock > 66)
164 printk("WARNING: IDE timing calculations will be incorrect\n");
165 }
166 }
167#endif 213#endif
214
168#ifdef CONFIG_BLK_DEV_FD 215#ifdef CONFIG_BLK_DEV_FD
169 fd_activate(); 216 fd_activate();
170#endif 217#endif
171#ifdef CONFIG_VT 218
172#if defined(CONFIG_VGA_CONSOLE) 219#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
173 screen_info = (struct screen_info) { 220 screen_info_setup();
174 0, 25, /* orig-x, orig-y */
175 0, /* unused */
176 0, /* orig-video-page */
177 0, /* orig-video-mode */
178 80, /* orig-video-cols */
179 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
180 25, /* orig-video-lines */
181 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
182 16 /* orig-video-points */
183 };
184#endif
185#endif 221#endif
186 mips_reboot_setup(); 222 mips_reboot_setup();
187} 223}
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index 5c980f4a48fe..5ea705e49454 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -15,28 +15,26 @@
15 * Cause the specified action to be performed on a targeted "CPU" 15 * Cause the specified action to be performed on a targeted "CPU"
16 */ 16 */
17 17
18void core_send_ipi(int cpu, unsigned int action) 18static void msmtc_send_ipi_single(int cpu, unsigned int action)
19{ 19{
20 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ 20 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
21 smtc_send_ipi(cpu, LINUX_SMP_IPI, action); 21 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
22} 22}
23 23
24/* 24static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action)
25 * Platform "CPU" startup hook
26 */
27
28void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
29{ 25{
30 smtc_boot_secondary(cpu, idle); 26 unsigned int i;
27
28 for_each_cpu_mask(i, mask)
29 msmtc_send_ipi_single(i, action);
31} 30}
32 31
33/* 32/*
34 * Post-config but pre-boot cleanup entry point 33 * Post-config but pre-boot cleanup entry point
35 */ 34 */
36 35static void __cpuinit msmtc_init_secondary(void)
37void __cpuinit prom_init_secondary(void)
38{ 36{
39 void smtc_init_secondary(void); 37 void smtc_init_secondary(void);
40 int myvpe; 38 int myvpe;
41 39
42 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ 40 /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
@@ -50,45 +48,61 @@ void __cpuinit prom_init_secondary(void)
50 set_c0_status(0x100 << cp0_perfcount_irq); 48 set_c0_status(0x100 << cp0_perfcount_irq);
51 } 49 }
52 50
53 smtc_init_secondary(); 51 smtc_init_secondary();
54} 52}
55 53
56/* 54/*
57 * Platform SMP pre-initialization 55 * Platform "CPU" startup hook
58 *
59 * As noted above, we can assume a single CPU for now
60 * but it may be multithreaded.
61 */ 56 */
62 57static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle)
63void __cpuinit plat_smp_setup(void)
64{ 58{
65 if (read_c0_config3() & (1<<2)) 59 smtc_boot_secondary(cpu, idle);
66 mipsmt_build_cpu_map(0);
67} 60}
68 61
69void __init plat_prepare_cpus(unsigned int max_cpus) 62/*
63 * SMP initialization finalization entry point
64 */
65static void __cpuinit msmtc_smp_finish(void)
70{ 66{
71 if (read_c0_config3() & (1<<2)) 67 smtc_smp_finish();
72 mipsmt_prepare_cpus();
73} 68}
74 69
75/* 70/*
76 * SMP initialization finalization entry point 71 * Hook for after all CPUs are online
77 */ 72 */
78 73
79void __cpuinit prom_smp_finish(void) 74static void msmtc_cpus_done(void)
80{ 75{
81 smtc_smp_finish();
82} 76}
83 77
84/* 78/*
85 * Hook for after all CPUs are online 79 * Platform SMP pre-initialization
80 *
81 * As noted above, we can assume a single CPU for now
82 * but it may be multithreaded.
86 */ 83 */
87 84
88void prom_cpus_done(void) 85static void __init msmtc_smp_setup(void)
89{ 86{
87 mipsmt_build_cpu_map(0);
90} 88}
91 89
90static void __init msmtc_prepare_cpus(unsigned int max_cpus)
91{
92 mipsmt_prepare_cpus();
93}
94
95struct plat_smp_ops msmtc_smp_ops = {
96 .send_ipi_single = msmtc_send_ipi_single,
97 .send_ipi_mask = msmtc_send_ipi_mask,
98 .init_secondary = msmtc_init_secondary,
99 .smp_finish = msmtc_smp_finish,
100 .cpus_done = msmtc_cpus_done,
101 .boot_secondary = msmtc_boot_secondary,
102 .smp_setup = msmtc_smp_setup,
103 .prepare_cpus = msmtc_prepare_cpus,
104};
105
92#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 106#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
93/* 107/*
94 * IRQ affinity hook 108 * IRQ affinity hook
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 1fb61b852304..8aa8e5b7b074 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -34,8 +34,6 @@
34#include <asm/mips-boards/seadint.h> 34#include <asm/mips-boards/seadint.h>
35#include <asm/time.h> 35#include <asm/time.h>
36 36
37extern void mips_reboot_setup(void);
38
39static void __init serial_init(void); 37static void __init serial_init(void);
40 38
41const char *get_system_type(void) 39const char *get_system_type(void)
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 75568b584df4..57f43c1c7882 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -21,6 +21,6 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \
21 sim_cmdline.o 21 sim_cmdline.o
22 22
23obj-$(CONFIG_EARLY_PRINTK) += sim_console.o 23obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
24obj-$(CONFIG_SMP) += sim_smp.o 24obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
25 25
26EXTRA_CFLAGS += -Werror 26EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 452c129d02c1..d49fe73426b7 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -60,6 +60,8 @@ void __init plat_mem_setup(void)
60#endif 60#endif
61} 61}
62 62
63extern struct plat_smp_ops ssmtc_smp_ops;
64
63void __init prom_init(void) 65void __init prom_init(void)
64{ 66{
65 set_io_port_base(0xbfd00000); 67 set_io_port_base(0xbfd00000);
@@ -67,8 +69,20 @@ void __init prom_init(void)
67 pr_info("\nLINUX started...\n"); 69 pr_info("\nLINUX started...\n");
68 prom_init_cmdline(); 70 prom_init_cmdline();
69 prom_meminit(); 71 prom_meminit();
70}
71 72
73#ifdef CONFIG_MIPS_MT_SMP
74 if (cpu_has_mipsmt)
75 register_smp_ops(&vsmp_smp_ops);
76 else
77 register_smp_ops(&up_smp_ops);
78#endif
79#ifdef CONFIG_MIPS_MT_SMTC
80 if (cpu_has_mipsmt)
81 register_smp_ops(&ssmtc_smp_ops);
82 else
83 register_smp_ops(&up_smp_ops);
84#endif
85}
72 86
73static void __init serial_init(void) 87static void __init serial_init(void)
74{ 88{
diff --git a/arch/mips/mipssim/sim_smp.c b/arch/mips/mipssim/sim_smtc.c
index ccbbccac23ef..d6e4f656ad14 100644
--- a/arch/mips/mipssim/sim_smp.c
+++ b/arch/mips/mipssim/sim_smtc.c
@@ -16,7 +16,7 @@
16 * 16 *
17 */ 17 */
18/* 18/*
19 * Simulator Platform-specific hooks for SMP operation 19 * Simulator Platform-specific hooks for SMTC operation
20 */ 20 */
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/sched.h> 22#include <linux/sched.h>
@@ -29,65 +29,72 @@
29#include <asm/processor.h> 29#include <asm/processor.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/mmu_context.h> 31#include <asm/mmu_context.h>
32#ifdef CONFIG_MIPS_MT_SMTC
33#include <asm/smtc_ipi.h> 32#include <asm/smtc_ipi.h>
34#endif /* CONFIG_MIPS_MT_SMTC */
35 33
36/* VPE/SMP Prototype implements platform interfaces directly */ 34/* VPE/SMP Prototype implements platform interfaces directly */
37#if !defined(CONFIG_MIPS_MT_SMP)
38 35
39/* 36/*
40 * Cause the specified action to be performed on a targeted "CPU" 37 * Cause the specified action to be performed on a targeted "CPU"
41 */ 38 */
42 39
43void core_send_ipi(int cpu, unsigned int action) 40static void ssmtc_send_ipi_single(int cpu, unsigned int action)
44{ 41{
45#ifdef CONFIG_MIPS_MT_SMTC
46 smtc_send_ipi(cpu, LINUX_SMP_IPI, action); 42 smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
47#endif /* CONFIG_MIPS_MT_SMTC */ 43 /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
48/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ 44}
45
46static inline void ssmtc_send_ipi_mask(cpumask_t mask, unsigned int action)
47{
48 unsigned int i;
49 49
50 for_each_cpu_mask(i, mask)
51 ssmtc_send_ipi_single(i, action);
50} 52}
51 53
52/* 54/*
53 * Platform "CPU" startup hook 55 * Post-config but pre-boot cleanup entry point
54 */ 56 */
55 57static void __cpuinit ssmtc_init_secondary(void)
56void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
57{ 58{
58#ifdef CONFIG_MIPS_MT_SMTC 59 void smtc_init_secondary(void);
59 smtc_boot_secondary(cpu, idle); 60
60#endif /* CONFIG_MIPS_MT_SMTC */ 61 smtc_init_secondary();
61} 62}
62 63
63/* 64/*
64 * Post-config but pre-boot cleanup entry point 65 * SMP initialization finalization entry point
65 */ 66 */
67static void __cpuinit ssmtc_smp_finish(void)
68{
69 smtc_smp_finish();
70}
66 71
67void __cpuinit prom_init_secondary(void) 72/*
73 * Hook for after all CPUs are online
74 */
75static void ssmtc_cpus_done(void)
68{ 76{
69#ifdef CONFIG_MIPS_MT_SMTC 77}
70 void smtc_init_secondary(void);
71 78
72 smtc_init_secondary(); 79/*
73#endif /* CONFIG_MIPS_MT_SMTC */ 80 * Platform "CPU" startup hook
81 */
82static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle)
83{
84 smtc_boot_secondary(cpu, idle);
74} 85}
75 86
76void plat_smp_setup(void) 87static void __init ssmtc_smp_setup(void)
77{ 88{
78#ifdef CONFIG_MIPS_MT_SMTC
79 if (read_c0_config3() & (1 << 2)) 89 if (read_c0_config3() & (1 << 2))
80 mipsmt_build_cpu_map(0); 90 mipsmt_build_cpu_map(0);
81#endif /* CONFIG_MIPS_MT_SMTC */
82} 91}
83 92
84/* 93/*
85 * Platform SMP pre-initialization 94 * Platform SMP pre-initialization
86 */ 95 */
87 96static void ssmtc_prepare_cpus(unsigned int max_cpus)
88void plat_prepare_cpus(unsigned int max_cpus)
89{ 97{
90#ifdef CONFIG_MIPS_MT_SMTC
91 /* 98 /*
92 * As noted above, we can assume a single CPU for now 99 * As noted above, we can assume a single CPU for now
93 * but it may be multithreaded. 100 * but it may be multithreaded.
@@ -96,28 +103,15 @@ void plat_prepare_cpus(unsigned int max_cpus)
96 if (read_c0_config3() & (1 << 2)) { 103 if (read_c0_config3() & (1 << 2)) {
97 mipsmt_prepare_cpus(); 104 mipsmt_prepare_cpus();
98 } 105 }
99#endif /* CONFIG_MIPS_MT_SMTC */
100} 106}
101 107
102/* 108struct plat_smp_ops ssmtc_smp_ops = {
103 * SMP initialization finalization entry point 109 .send_ipi_single = ssmtc_send_ipi_single,
104 */ 110 .send_ipi_mask = ssmtc_send_ipi_mask,
105 111 .init_secondary = ssmtc_init_secondary,
106void __cpuinit prom_smp_finish(void) 112 .smp_finish = ssmtc_smp_finish,
107{ 113 .cpus_done = ssmtc_cpus_done,
108#ifdef CONFIG_MIPS_MT_SMTC 114 .boot_secondary = ssmtc_boot_secondary,
109 smtc_smp_finish(); 115 .smp_setup = ssmtc_smp_setup,
110#endif /* CONFIG_MIPS_MT_SMTC */ 116 .prepare_cpus = ssmtc_prepare_cpus,
111} 117};
112
113/*
114 * Hook for after all CPUs are online
115 */
116
117void prom_cpus_done(void)
118{
119#ifdef CONFIG_MIPS_MT_SMTC
120
121#endif /* CONFIG_MIPS_MT_SMTC */
122}
123#endif /* CONFIG_MIPS32R2_MT_SMP */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9355f1c9325f..02bd180f0e02 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -449,7 +449,7 @@ static inline void local_r4k_flush_cache_page(void *args)
449 * If the page isn't marked valid, the page cannot possibly be 449 * If the page isn't marked valid, the page cannot possibly be
450 * in the cache. 450 * in the cache.
451 */ 451 */
452 if (!(pte_val(*ptep) & _PAGE_PRESENT)) 452 if (!(pte_present(*ptep)))
453 return; 453 return;
454 454
455 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) 455 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
@@ -468,8 +468,6 @@ static inline void local_r4k_flush_cache_page(void *args)
468 468
469 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 469 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
470 r4k_blast_dcache_page(addr); 470 r4k_blast_dcache_page(addr);
471 if (exec && !cpu_icache_snoops_remote_store)
472 r4k_blast_scache_page(addr);
473 } 471 }
474 if (exec) { 472 if (exec) {
475 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { 473 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
@@ -533,13 +531,6 @@ static inline void local_r4k_flush_icache_range(void *args)
533 R4600_HIT_CACHEOP_WAR_IMPL; 531 R4600_HIT_CACHEOP_WAR_IMPL;
534 protected_blast_dcache_range(start, end); 532 protected_blast_dcache_range(start, end);
535 } 533 }
536
537 if (!cpu_icache_snoops_remote_store && scache_size) {
538 if (end - start > scache_size)
539 r4k_blast_scache();
540 else
541 protected_blast_scache_range(start, end);
542 }
543 } 534 }
544 535
545 if (end - start > icache_size) 536 if (end - start > icache_size)
@@ -598,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
598 if (size >= scache_size) 589 if (size >= scache_size)
599 r4k_blast_scache(); 590 r4k_blast_scache();
600 else 591 else
601 blast_scache_range(addr, addr + size); 592 blast_inv_scache_range(addr, addr + size);
602 return; 593 return;
603 } 594 }
604 595
@@ -606,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
606 r4k_blast_dcache(); 597 r4k_blast_dcache();
607 } else { 598 } else {
608 R4600_HIT_CACHEOP_WAR_IMPL; 599 R4600_HIT_CACHEOP_WAR_IMPL;
609 blast_dcache_range(addr, addr + size); 600 blast_inv_dcache_range(addr, addr + size);
610 } 601 }
611 602
612 bc_inv(addr, size); 603 bc_inv(addr, size);
@@ -989,6 +980,8 @@ static void __init probe_pcache(void)
989 case CPU_AU1100: 980 case CPU_AU1100:
990 case CPU_AU1550: 981 case CPU_AU1550:
991 case CPU_AU1200: 982 case CPU_AU1200:
983 case CPU_AU1210:
984 case CPU_AU1250:
992 c->icache.flags |= MIPS_CACHE_IC_F_DC; 985 c->icache.flags |= MIPS_CACHE_IC_F_DC;
993 break; 986 break;
994 } 987 }
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 810535dd091b..ae39dd88b9aa 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
383 BUG_ON(direction == DMA_NONE); 383 BUG_ON(direction == DMA_NONE);
384 384
385 if (!plat_device_is_coherent(dev)) 385 if (!plat_device_is_coherent(dev))
386 dma_cache_wback_inv((unsigned long)vaddr, size); 386 __dma_sync((unsigned long)vaddr, size, direction);
387} 387}
388 388
389EXPORT_SYMBOL(dma_cache_sync); 389EXPORT_SYMBOL(dma_cache_sync);
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index 4f770ac885ce..9185fbf37c0d 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -4,6 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Maciej W. Rozycki
7 */ 8 */
8#include <linux/init.h> 9#include <linux/init.h>
9#include <linux/kernel.h> 10#include <linux/kernel.h>
@@ -12,6 +13,7 @@
12#include <linux/module.h> 13#include <linux/module.h>
13#include <linux/proc_fs.h> 14#include <linux/proc_fs.h>
14 15
16#include <asm/bugs.h>
15#include <asm/cacheops.h> 17#include <asm/cacheops.h>
16#include <asm/inst.h> 18#include <asm/inst.h>
17#include <asm/io.h> 19#include <asm/io.h>
@@ -255,64 +257,58 @@ static inline void build_store_reg(int reg)
255 __build_store_reg(reg); 257 __build_store_reg(reg);
256} 258}
257 259
258static inline void build_addiu_a2_a0(unsigned long offset) 260static inline void build_addiu_rt_rs(unsigned int rt, unsigned int rs,
261 unsigned long offset)
259{ 262{
260 union mips_instruction mi; 263 union mips_instruction mi;
261 264
262 BUG_ON(offset > 0x7fff); 265 BUG_ON(offset > 0x7fff);
263 266
264 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; 267 if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
265 mi.i_format.rs = 4; /* $a0 */ 268 mi.i_format.opcode = addiu_op;
266 mi.i_format.rt = 6; /* $a2 */ 269 mi.i_format.rs = 0; /* $zero */
267 mi.i_format.simmediate = offset; 270 mi.i_format.rt = 25; /* $t9 */
271 mi.i_format.simmediate = offset;
272 emit_instruction(mi);
268 273
274 mi.r_format.opcode = spec_op;
275 mi.r_format.rs = rs;
276 mi.r_format.rt = 25; /* $t9 */
277 mi.r_format.rd = rt;
278 mi.r_format.re = 0;
279 mi.r_format.func = daddu_op;
280 } else {
281 mi.i_format.opcode = cpu_has_64bit_gp_regs ?
282 daddiu_op : addiu_op;
283 mi.i_format.rs = rs;
284 mi.i_format.rt = rt;
285 mi.i_format.simmediate = offset;
286 }
269 emit_instruction(mi); 287 emit_instruction(mi);
270} 288}
271 289
272static inline void build_addiu_a2(unsigned long offset) 290static inline void build_addiu_a2_a0(unsigned long offset)
273{ 291{
274 union mips_instruction mi; 292 build_addiu_rt_rs(6, 4, offset); /* $a2, $a0, offset */
275 293}
276 BUG_ON(offset > 0x7fff);
277
278 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
279 mi.i_format.rs = 6; /* $a2 */
280 mi.i_format.rt = 6; /* $a2 */
281 mi.i_format.simmediate = offset;
282 294
283 emit_instruction(mi); 295static inline void build_addiu_a2(unsigned long offset)
296{
297 build_addiu_rt_rs(6, 6, offset); /* $a2, $a2, offset */
284} 298}
285 299
286static inline void build_addiu_a1(unsigned long offset) 300static inline void build_addiu_a1(unsigned long offset)
287{ 301{
288 union mips_instruction mi; 302 build_addiu_rt_rs(5, 5, offset); /* $a1, $a1, offset */
289
290 BUG_ON(offset > 0x7fff);
291
292 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
293 mi.i_format.rs = 5; /* $a1 */
294 mi.i_format.rt = 5; /* $a1 */
295 mi.i_format.simmediate = offset;
296 303
297 load_offset -= offset; 304 load_offset -= offset;
298
299 emit_instruction(mi);
300} 305}
301 306
302static inline void build_addiu_a0(unsigned long offset) 307static inline void build_addiu_a0(unsigned long offset)
303{ 308{
304 union mips_instruction mi; 309 build_addiu_rt_rs(4, 4, offset); /* $a0, $a0, offset */
305
306 BUG_ON(offset > 0x7fff);
307
308 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
309 mi.i_format.rs = 4; /* $a0 */
310 mi.i_format.rt = 4; /* $a0 */
311 mi.i_format.simmediate = offset;
312 310
313 store_offset -= offset; 311 store_offset -= offset;
314
315 emit_instruction(mi);
316} 312}
317 313
318static inline void build_bne(unsigned int *dest) 314static inline void build_bne(unsigned int *dest)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a61246d3533d..d026302e0ecc 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -6,7 +6,7 @@
6 * Synthesize TLB refill handlers at runtime. 6 * Synthesize TLB refill handlers at runtime.
7 * 7 *
8 * Copyright (C) 2004,2005,2006 by Thiemo Seufer 8 * Copyright (C) 2004,2005,2006 by Thiemo Seufer
9 * Copyright (C) 2005 Maciej W. Rozycki 9 * Copyright (C) 2005, 2007 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * 11 *
12 * ... and the days got worse and worse and now you see 12 * ... and the days got worse and worse and now you see
@@ -19,20 +19,15 @@
19 * (Condolences to Napoleon XIV) 19 * (Condolences to Napoleon XIV)
20 */ 20 */
21 21
22#include <stdarg.h>
23
24#include <linux/mm.h>
25#include <linux/kernel.h> 22#include <linux/kernel.h>
26#include <linux/types.h> 23#include <linux/types.h>
27#include <linux/string.h> 24#include <linux/string.h>
28#include <linux/init.h> 25#include <linux/init.h>
29 26
30#include <asm/pgtable.h> 27#include <asm/bugs.h>
31#include <asm/cacheflush.h>
32#include <asm/mmu_context.h> 28#include <asm/mmu_context.h>
33#include <asm/inst.h> 29#include <asm/inst.h>
34#include <asm/elf.h> 30#include <asm/elf.h>
35#include <asm/smp.h>
36#include <asm/war.h> 31#include <asm/war.h>
37 32
38static inline int r45k_bvahwbug(void) 33static inline int r45k_bvahwbug(void)
@@ -66,7 +61,7 @@ static inline int __maybe_unused r10000_llsc_war(void)
66 * why; it's not an issue caused by the core RTL. 61 * why; it's not an issue caused by the core RTL.
67 * 62 *
68 */ 63 */
69static __init int __attribute__((unused)) m4kc_tlbp_war(void) 64static int __init m4kc_tlbp_war(void)
70{ 65{
71 return (current_cpu_data.processor_id & 0xffff00) == 66 return (current_cpu_data.processor_id & 0xffff00) ==
72 (PRID_COMP_MIPS | PRID_IMP_4KC); 67 (PRID_COMP_MIPS | PRID_IMP_4KC);
@@ -140,7 +135,7 @@ struct insn {
140 | (e) << RE_SH \ 135 | (e) << RE_SH \
141 | (f) << FUNC_SH) 136 | (f) << FUNC_SH)
142 137
143static __initdata struct insn insn_table[] = { 138static struct insn insn_table[] __initdata = {
144 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 139 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
145 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 140 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
146 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, 141 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
@@ -193,7 +188,7 @@ static __initdata struct insn insn_table[] = {
193 188
194#undef M 189#undef M
195 190
196static __init u32 build_rs(u32 arg) 191static u32 __init build_rs(u32 arg)
197{ 192{
198 if (arg & ~RS_MASK) 193 if (arg & ~RS_MASK)
199 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 194 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -201,7 +196,7 @@ static __init u32 build_rs(u32 arg)
201 return (arg & RS_MASK) << RS_SH; 196 return (arg & RS_MASK) << RS_SH;
202} 197}
203 198
204static __init u32 build_rt(u32 arg) 199static u32 __init build_rt(u32 arg)
205{ 200{
206 if (arg & ~RT_MASK) 201 if (arg & ~RT_MASK)
207 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 202 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -209,7 +204,7 @@ static __init u32 build_rt(u32 arg)
209 return (arg & RT_MASK) << RT_SH; 204 return (arg & RT_MASK) << RT_SH;
210} 205}
211 206
212static __init u32 build_rd(u32 arg) 207static u32 __init build_rd(u32 arg)
213{ 208{
214 if (arg & ~RD_MASK) 209 if (arg & ~RD_MASK)
215 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 210 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -217,7 +212,7 @@ static __init u32 build_rd(u32 arg)
217 return (arg & RD_MASK) << RD_SH; 212 return (arg & RD_MASK) << RD_SH;
218} 213}
219 214
220static __init u32 build_re(u32 arg) 215static u32 __init build_re(u32 arg)
221{ 216{
222 if (arg & ~RE_MASK) 217 if (arg & ~RE_MASK)
223 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 218 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -225,7 +220,7 @@ static __init u32 build_re(u32 arg)
225 return (arg & RE_MASK) << RE_SH; 220 return (arg & RE_MASK) << RE_SH;
226} 221}
227 222
228static __init u32 build_simm(s32 arg) 223static u32 __init build_simm(s32 arg)
229{ 224{
230 if (arg > 0x7fff || arg < -0x8000) 225 if (arg > 0x7fff || arg < -0x8000)
231 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 226 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -233,7 +228,7 @@ static __init u32 build_simm(s32 arg)
233 return arg & 0xffff; 228 return arg & 0xffff;
234} 229}
235 230
236static __init u32 build_uimm(u32 arg) 231static u32 __init build_uimm(u32 arg)
237{ 232{
238 if (arg & ~IMM_MASK) 233 if (arg & ~IMM_MASK)
239 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 234 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -241,7 +236,7 @@ static __init u32 build_uimm(u32 arg)
241 return arg & IMM_MASK; 236 return arg & IMM_MASK;
242} 237}
243 238
244static __init u32 build_bimm(s32 arg) 239static u32 __init build_bimm(s32 arg)
245{ 240{
246 if (arg > 0x1ffff || arg < -0x20000) 241 if (arg > 0x1ffff || arg < -0x20000)
247 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 242 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -252,7 +247,7 @@ static __init u32 build_bimm(s32 arg)
252 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 247 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
253} 248}
254 249
255static __init u32 build_jimm(u32 arg) 250static u32 __init build_jimm(u32 arg)
256{ 251{
257 if (arg & ~((JIMM_MASK) << 2)) 252 if (arg & ~((JIMM_MASK) << 2))
258 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 253 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -260,7 +255,7 @@ static __init u32 build_jimm(u32 arg)
260 return (arg >> 2) & JIMM_MASK; 255 return (arg >> 2) & JIMM_MASK;
261} 256}
262 257
263static __init u32 build_func(u32 arg) 258static u32 __init build_func(u32 arg)
264{ 259{
265 if (arg & ~FUNC_MASK) 260 if (arg & ~FUNC_MASK)
266 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 261 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -268,7 +263,7 @@ static __init u32 build_func(u32 arg)
268 return arg & FUNC_MASK; 263 return arg & FUNC_MASK;
269} 264}
270 265
271static __init u32 build_set(u32 arg) 266static u32 __init build_set(u32 arg)
272{ 267{
273 if (arg & ~SET_MASK) 268 if (arg & ~SET_MASK)
274 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 269 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -293,7 +288,7 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...)
293 break; 288 break;
294 } 289 }
295 290
296 if (!ip) 291 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
297 panic("Unsupported TLB synthesizer instruction %d", opc); 292 panic("Unsupported TLB synthesizer instruction %d", opc);
298 293
299 op = ip->match; 294 op = ip->match;
@@ -315,69 +310,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...)
315} 310}
316 311
317#define I_u1u2u3(op) \ 312#define I_u1u2u3(op) \
318 static inline void __init i##op(u32 **buf, unsigned int a, \ 313 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
319 unsigned int b, unsigned int c) \ 314 unsigned int b, unsigned int c) \
320 { \ 315 { \
321 build_insn(buf, insn##op, a, b, c); \ 316 build_insn(buf, insn##op, a, b, c); \
322 } 317 }
323 318
324#define I_u2u1u3(op) \ 319#define I_u2u1u3(op) \
325 static inline void __init i##op(u32 **buf, unsigned int a, \ 320 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
326 unsigned int b, unsigned int c) \ 321 unsigned int b, unsigned int c) \
327 { \ 322 { \
328 build_insn(buf, insn##op, b, a, c); \ 323 build_insn(buf, insn##op, b, a, c); \
329 } 324 }
330 325
331#define I_u3u1u2(op) \ 326#define I_u3u1u2(op) \
332 static inline void __init i##op(u32 **buf, unsigned int a, \ 327 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
333 unsigned int b, unsigned int c) \ 328 unsigned int b, unsigned int c) \
334 { \ 329 { \
335 build_insn(buf, insn##op, b, c, a); \ 330 build_insn(buf, insn##op, b, c, a); \
336 } 331 }
337 332
338#define I_u1u2s3(op) \ 333#define I_u1u2s3(op) \
339 static inline void __init i##op(u32 **buf, unsigned int a, \ 334 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
340 unsigned int b, signed int c) \ 335 unsigned int b, signed int c) \
341 { \ 336 { \
342 build_insn(buf, insn##op, a, b, c); \ 337 build_insn(buf, insn##op, a, b, c); \
343 } 338 }
344 339
345#define I_u2s3u1(op) \ 340#define I_u2s3u1(op) \
346 static inline void __init i##op(u32 **buf, unsigned int a, \ 341 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
347 signed int b, unsigned int c) \ 342 signed int b, unsigned int c) \
348 { \ 343 { \
349 build_insn(buf, insn##op, c, a, b); \ 344 build_insn(buf, insn##op, c, a, b); \
350 } 345 }
351 346
352#define I_u2u1s3(op) \ 347#define I_u2u1s3(op) \
353 static inline void __init i##op(u32 **buf, unsigned int a, \ 348 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
354 unsigned int b, signed int c) \ 349 unsigned int b, signed int c) \
355 { \ 350 { \
356 build_insn(buf, insn##op, b, a, c); \ 351 build_insn(buf, insn##op, b, a, c); \
357 } 352 }
358 353
359#define I_u1u2(op) \ 354#define I_u1u2(op) \
360 static inline void __init i##op(u32 **buf, unsigned int a, \ 355 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
361 unsigned int b) \ 356 unsigned int b) \
362 { \ 357 { \
363 build_insn(buf, insn##op, a, b); \ 358 build_insn(buf, insn##op, a, b); \
364 } 359 }
365 360
366#define I_u1s2(op) \ 361#define I_u1s2(op) \
367 static inline void __init i##op(u32 **buf, unsigned int a, \ 362 static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \
368 signed int b) \ 363 signed int b) \
369 { \ 364 { \
370 build_insn(buf, insn##op, a, b); \ 365 build_insn(buf, insn##op, a, b); \
371 } 366 }
372 367
373#define I_u1(op) \ 368#define I_u1(op) \
374 static inline void __init i##op(u32 **buf, unsigned int a) \ 369 static void __init __maybe_unused i##op(u32 **buf, unsigned int a) \
375 { \ 370 { \
376 build_insn(buf, insn##op, a); \ 371 build_insn(buf, insn##op, a); \
377 } 372 }
378 373
379#define I_0(op) \ 374#define I_0(op) \
380 static inline void __init i##op(u32 **buf) \ 375 static void __init __maybe_unused i##op(u32 **buf) \
381 { \ 376 { \
382 build_insn(buf, insn##op); \ 377 build_insn(buf, insn##op); \
383 } 378 }
@@ -457,7 +452,7 @@ struct label {
457 enum label_id lab; 452 enum label_id lab;
458}; 453};
459 454
460static __init void build_label(struct label **lab, u32 *addr, 455static void __init build_label(struct label **lab, u32 *addr,
461 enum label_id l) 456 enum label_id l)
462{ 457{
463 (*lab)->addr = addr; 458 (*lab)->addr = addr;
@@ -466,7 +461,7 @@ static __init void build_label(struct label **lab, u32 *addr,
466} 461}
467 462
468#define L_LA(lb) \ 463#define L_LA(lb) \
469 static inline void l##lb(struct label **lab, u32 *addr) \ 464 static inline void __init l##lb(struct label **lab, u32 *addr) \
470 { \ 465 { \
471 build_label(lab, addr, label##lb); \ 466 build_label(lab, addr, label##lb); \
472 } 467 }
@@ -525,37 +520,46 @@ L_LA(_r3000_write_probe_fail)
525#define i_ssnop(buf) i_sll(buf, 0, 0, 1) 520#define i_ssnop(buf) i_sll(buf, 0, 0, 1)
526#define i_ehb(buf) i_sll(buf, 0, 0, 3) 521#define i_ehb(buf) i_sll(buf, 0, 0, 3)
527 522
528#ifdef CONFIG_64BIT 523static int __init __maybe_unused in_compat_space_p(long addr)
529static __init int __maybe_unused in_compat_space_p(long addr)
530{ 524{
531 /* Is this address in 32bit compat space? */ 525 /* Is this address in 32bit compat space? */
526#ifdef CONFIG_64BIT
532 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 527 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
528#else
529 return 1;
530#endif
533} 531}
534 532
535static __init int __maybe_unused rel_highest(long val) 533static int __init __maybe_unused rel_highest(long val)
536{ 534{
535#ifdef CONFIG_64BIT
537 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 536 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
537#else
538 return 0;
539#endif
538} 540}
539 541
540static __init int __maybe_unused rel_higher(long val) 542static int __init __maybe_unused rel_higher(long val)
541{ 543{
544#ifdef CONFIG_64BIT
542 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 545 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
543} 546#else
547 return 0;
544#endif 548#endif
549}
545 550
546static __init int rel_hi(long val) 551static int __init rel_hi(long val)
547{ 552{
548 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 553 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
549} 554}
550 555
551static __init int rel_lo(long val) 556static int __init rel_lo(long val)
552{ 557{
553 return ((val & 0xffff) ^ 0x8000) - 0x8000; 558 return ((val & 0xffff) ^ 0x8000) - 0x8000;
554} 559}
555 560
556static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 561static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr)
557{ 562{
558#ifdef CONFIG_64BIT
559 if (!in_compat_space_p(addr)) { 563 if (!in_compat_space_p(addr)) {
560 i_lui(buf, rs, rel_highest(addr)); 564 i_lui(buf, rs, rel_highest(addr));
561 if (rel_higher(addr)) 565 if (rel_higher(addr))
@@ -567,16 +571,18 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
567 } else 571 } else
568 i_dsll32(buf, rs, rs, 0); 572 i_dsll32(buf, rs, rs, 0);
569 } else 573 } else
570#endif
571 i_lui(buf, rs, rel_hi(addr)); 574 i_lui(buf, rs, rel_hi(addr));
572} 575}
573 576
574static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, 577static void __init __maybe_unused i_LA(u32 **buf, unsigned int rs, long addr)
575 long addr)
576{ 578{
577 i_LA_mostly(buf, rs, addr); 579 i_LA_mostly(buf, rs, addr);
578 if (rel_lo(addr)) 580 if (rel_lo(addr)) {
579 i_ADDIU(buf, rs, rs, rel_lo(addr)); 581 if (!in_compat_space_p(addr))
582 i_daddiu(buf, rs, rs, rel_lo(addr));
583 else
584 i_addiu(buf, rs, rs, rel_lo(addr));
585 }
580} 586}
581 587
582/* 588/*
@@ -589,7 +595,7 @@ struct reloc {
589 enum label_id lab; 595 enum label_id lab;
590}; 596};
591 597
592static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 598static void __init r_mips_pc16(struct reloc **rel, u32 *addr,
593 enum label_id l) 599 enum label_id l)
594{ 600{
595 (*rel)->addr = addr; 601 (*rel)->addr = addr;
@@ -614,7 +620,7 @@ static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
614 } 620 }
615} 621}
616 622
617static __init void resolve_relocs(struct reloc *rel, struct label *lab) 623static void __init resolve_relocs(struct reloc *rel, struct label *lab)
618{ 624{
619 struct label *l; 625 struct label *l;
620 626
@@ -624,7 +630,7 @@ static __init void resolve_relocs(struct reloc *rel, struct label *lab)
624 __resolve_relocs(rel, l); 630 __resolve_relocs(rel, l);
625} 631}
626 632
627static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 633static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end,
628 long off) 634 long off)
629{ 635{
630 for (; rel->lab != label_invalid; rel++) 636 for (; rel->lab != label_invalid; rel++)
@@ -632,7 +638,7 @@ static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
632 rel->addr += off; 638 rel->addr += off;
633} 639}
634 640
635static __init void move_labels(struct label *lab, u32 *first, u32 *end, 641static void __init move_labels(struct label *lab, u32 *first, u32 *end,
636 long off) 642 long off)
637{ 643{
638 for (; lab->lab != label_invalid; lab++) 644 for (; lab->lab != label_invalid; lab++)
@@ -640,7 +646,7 @@ static __init void move_labels(struct label *lab, u32 *first, u32 *end,
640 lab->addr += off; 646 lab->addr += off;
641} 647}
642 648
643static __init void copy_handler(struct reloc *rel, struct label *lab, 649static void __init copy_handler(struct reloc *rel, struct label *lab,
644 u32 *first, u32 *end, u32 *target) 650 u32 *first, u32 *end, u32 *target)
645{ 651{
646 long off = (long)(target - first); 652 long off = (long)(target - first);
@@ -651,7 +657,7 @@ static __init void copy_handler(struct reloc *rel, struct label *lab,
651 move_labels(lab, first, end, off); 657 move_labels(lab, first, end, off);
652} 658}
653 659
654static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, 660static int __init __maybe_unused insn_has_bdelay(struct reloc *rel,
655 u32 *addr) 661 u32 *addr)
656{ 662{
657 for (; rel->lab != label_invalid; rel++) { 663 for (; rel->lab != label_invalid; rel++) {
@@ -714,6 +720,22 @@ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
714 i_bgez(p, reg, 0); 720 i_bgez(p, reg, 0);
715} 721}
716 722
723/*
724 * For debug purposes.
725 */
726static inline void dump_handler(const u32 *handler, int count)
727{
728 int i;
729
730 pr_debug("\t.set push\n");
731 pr_debug("\t.set noreorder\n");
732
733 for (i = 0; i < count; i++)
734 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
735
736 pr_debug("\t.set pop\n");
737}
738
717/* The only general purpose registers allowed in TLB handlers. */ 739/* The only general purpose registers allowed in TLB handlers. */
718#define K0 26 740#define K0 26
719#define K1 27 741#define K1 27
@@ -743,11 +765,11 @@ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
743 * We deliberately chose a buffer size of 128, so we won't scribble 765 * We deliberately chose a buffer size of 128, so we won't scribble
744 * over anything important on overflow before we panic. 766 * over anything important on overflow before we panic.
745 */ 767 */
746static __initdata u32 tlb_handler[128]; 768static u32 tlb_handler[128] __initdata;
747 769
748/* simply assume worst case size for labels and relocs */ 770/* simply assume worst case size for labels and relocs */
749static __initdata struct label labels[128]; 771static struct label labels[128] __initdata;
750static __initdata struct reloc relocs[128]; 772static struct reloc relocs[128] __initdata;
751 773
752/* 774/*
753 * The R3000 TLB handler is simple. 775 * The R3000 TLB handler is simple.
@@ -756,7 +778,6 @@ static void __init build_r3000_tlb_refill_handler(void)
756{ 778{
757 long pgdc = (long)pgd_current; 779 long pgdc = (long)pgd_current;
758 u32 *p; 780 u32 *p;
759 int i;
760 781
761 memset(tlb_handler, 0, sizeof(tlb_handler)); 782 memset(tlb_handler, 0, sizeof(tlb_handler));
762 p = tlb_handler; 783 p = tlb_handler;
@@ -785,13 +806,9 @@ static void __init build_r3000_tlb_refill_handler(void)
785 pr_info("Synthesized TLB refill handler (%u instructions).\n", 806 pr_info("Synthesized TLB refill handler (%u instructions).\n",
786 (unsigned int)(p - tlb_handler)); 807 (unsigned int)(p - tlb_handler));
787 808
788 pr_debug("\t.set push\n");
789 pr_debug("\t.set noreorder\n");
790 for (i = 0; i < (p - tlb_handler); i++)
791 pr_debug("\t.word 0x%08x\n", tlb_handler[i]);
792 pr_debug("\t.set pop\n");
793
794 memcpy((void *)ebase, tlb_handler, 0x80); 809 memcpy((void *)ebase, tlb_handler, 0x80);
810
811 dump_handler((u32 *)ebase, 32);
795} 812}
796 813
797/* 814/*
@@ -801,7 +818,7 @@ static void __init build_r3000_tlb_refill_handler(void)
801 * other one.To keep things simple, we first assume linear space, 818 * other one.To keep things simple, we first assume linear space,
802 * then we relocate it to the final handler layout as needed. 819 * then we relocate it to the final handler layout as needed.
803 */ 820 */
804static __initdata u32 final_handler[64]; 821static u32 final_handler[64] __initdata;
805 822
806/* 823/*
807 * Hazards 824 * Hazards
@@ -825,7 +842,7 @@ static __initdata u32 final_handler[64];
825 * 842 *
826 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 843 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
827 */ 844 */
828static __init void __maybe_unused build_tlb_probe_entry(u32 **p) 845static void __init __maybe_unused build_tlb_probe_entry(u32 **p)
829{ 846{
830 switch (current_cpu_type()) { 847 switch (current_cpu_type()) {
831 /* Found by experiment: R4600 v2.0 needs this, too. */ 848 /* Found by experiment: R4600 v2.0 needs this, too. */
@@ -849,7 +866,7 @@ static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
849 */ 866 */
850enum tlb_write_entry { tlb_random, tlb_indexed }; 867enum tlb_write_entry { tlb_random, tlb_indexed };
851 868
852static __init void build_tlb_write_entry(u32 **p, struct label **l, 869static void __init build_tlb_write_entry(u32 **p, struct label **l,
853 struct reloc **r, 870 struct reloc **r,
854 enum tlb_write_entry wmode) 871 enum tlb_write_entry wmode)
855{ 872{
@@ -860,6 +877,12 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
860 case tlb_indexed: tlbw = i_tlbwi; break; 877 case tlb_indexed: tlbw = i_tlbwi; break;
861 } 878 }
862 879
880 if (cpu_has_mips_r2) {
881 i_ehb(p);
882 tlbw(p);
883 return;
884 }
885
863 switch (current_cpu_type()) { 886 switch (current_cpu_type()) {
864 case CPU_R4000PC: 887 case CPU_R4000PC:
865 case CPU_R4000SC: 888 case CPU_R4000SC:
@@ -894,6 +917,8 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
894 case CPU_AU1500: 917 case CPU_AU1500:
895 case CPU_AU1550: 918 case CPU_AU1550:
896 case CPU_AU1200: 919 case CPU_AU1200:
920 case CPU_AU1210:
921 case CPU_AU1250:
897 case CPU_PR4450: 922 case CPU_PR4450:
898 i_nop(p); 923 i_nop(p);
899 tlbw(p); 924 tlbw(p);
@@ -935,14 +960,6 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
935 tlbw(p); 960 tlbw(p);
936 break; 961 break;
937 962
938 case CPU_4KEC:
939 case CPU_24K:
940 case CPU_34K:
941 case CPU_74K:
942 i_ehb(p);
943 tlbw(p);
944 break;
945
946 case CPU_RM9000: 963 case CPU_RM9000:
947 /* 964 /*
948 * When the JTLB is updated by tlbwi or tlbwr, a subsequent 965 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
@@ -993,7 +1010,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
993 * TMP and PTR are scratch. 1010 * TMP and PTR are scratch.
994 * TMP will be clobbered, PTR will hold the pmd entry. 1011 * TMP will be clobbered, PTR will hold the pmd entry.
995 */ 1012 */
996static __init void 1013static void __init
997build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 1014build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
998 unsigned int tmp, unsigned int ptr) 1015 unsigned int tmp, unsigned int ptr)
999{ 1016{
@@ -1054,7 +1071,7 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
1054 * BVADDR is the faulting address, PTR is scratch. 1071 * BVADDR is the faulting address, PTR is scratch.
1055 * PTR will hold the pgd for vmalloc. 1072 * PTR will hold the pgd for vmalloc.
1056 */ 1073 */
1057static __init void 1074static void __init
1058build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 1075build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1059 unsigned int bvaddr, unsigned int ptr) 1076 unsigned int bvaddr, unsigned int ptr)
1060{ 1077{
@@ -1087,7 +1104,10 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1087 } else { 1104 } else {
1088 i_LA_mostly(p, ptr, modd); 1105 i_LA_mostly(p, ptr, modd);
1089 il_b(p, r, label_vmalloc_done); 1106 il_b(p, r, label_vmalloc_done);
1090 i_daddiu(p, ptr, ptr, rel_lo(modd)); 1107 if (in_compat_space_p(modd))
1108 i_addiu(p, ptr, ptr, rel_lo(modd));
1109 else
1110 i_daddiu(p, ptr, ptr, rel_lo(modd));
1091 } 1111 }
1092 1112
1093 l_vmalloc(l, *p); 1113 l_vmalloc(l, *p);
@@ -1108,7 +1128,10 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1108 } else { 1128 } else {
1109 i_LA_mostly(p, ptr, swpd); 1129 i_LA_mostly(p, ptr, swpd);
1110 il_b(p, r, label_vmalloc_done); 1130 il_b(p, r, label_vmalloc_done);
1111 i_daddiu(p, ptr, ptr, rel_lo(swpd)); 1131 if (in_compat_space_p(swpd))
1132 i_addiu(p, ptr, ptr, rel_lo(swpd));
1133 else
1134 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1112 } 1135 }
1113} 1136}
1114 1137
@@ -1118,7 +1141,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1118 * TMP and PTR are scratch. 1141 * TMP and PTR are scratch.
1119 * TMP will be clobbered, PTR will hold the pgd entry. 1142 * TMP will be clobbered, PTR will hold the pgd entry.
1120 */ 1143 */
1121static __init void __maybe_unused 1144static void __init __maybe_unused
1122build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1145build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1123{ 1146{
1124 long pgdc = (long)pgd_current; 1147 long pgdc = (long)pgd_current;
@@ -1153,7 +1176,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1153 1176
1154#endif /* !CONFIG_64BIT */ 1177#endif /* !CONFIG_64BIT */
1155 1178
1156static __init void build_adjust_context(u32 **p, unsigned int ctx) 1179static void __init build_adjust_context(u32 **p, unsigned int ctx)
1157{ 1180{
1158 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 1181 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1159 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1182 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
@@ -1179,7 +1202,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx)
1179 i_andi(p, ctx, ctx, mask); 1202 i_andi(p, ctx, ctx, mask);
1180} 1203}
1181 1204
1182static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1205static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1183{ 1206{
1184 /* 1207 /*
1185 * Bug workaround for the Nevada. It seems as if under certain 1208 * Bug workaround for the Nevada. It seems as if under certain
@@ -1204,7 +1227,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1204 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1227 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1205} 1228}
1206 1229
1207static __init void build_update_entries(u32 **p, unsigned int tmp, 1230static void __init build_update_entries(u32 **p, unsigned int tmp,
1208 unsigned int ptep) 1231 unsigned int ptep)
1209{ 1232{
1210 /* 1233 /*
@@ -1254,7 +1277,6 @@ static void __init build_r4000_tlb_refill_handler(void)
1254 struct reloc *r = relocs; 1277 struct reloc *r = relocs;
1255 u32 *f; 1278 u32 *f;
1256 unsigned int final_len; 1279 unsigned int final_len;
1257 int i;
1258 1280
1259 memset(tlb_handler, 0, sizeof(tlb_handler)); 1281 memset(tlb_handler, 0, sizeof(tlb_handler));
1260 memset(labels, 0, sizeof(labels)); 1282 memset(labels, 0, sizeof(labels));
@@ -1356,20 +1378,9 @@ static void __init build_r4000_tlb_refill_handler(void)
1356 pr_info("Synthesized TLB refill handler (%u instructions).\n", 1378 pr_info("Synthesized TLB refill handler (%u instructions).\n",
1357 final_len); 1379 final_len);
1358 1380
1359 f = final_handler;
1360#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2)
1361 if (final_len > 32)
1362 final_len = 64;
1363 else
1364 f = final_handler + 32;
1365#endif /* CONFIG_64BIT */
1366 pr_debug("\t.set push\n");
1367 pr_debug("\t.set noreorder\n");
1368 for (i = 0; i < final_len; i++)
1369 pr_debug("\t.word 0x%08x\n", f[i]);
1370 pr_debug("\t.set pop\n");
1371
1372 memcpy((void *)ebase, final_handler, 0x100); 1381 memcpy((void *)ebase, final_handler, 0x100);
1382
1383 dump_handler((u32 *)ebase, 64);
1373} 1384}
1374 1385
1375/* 1386/*
@@ -1381,18 +1392,15 @@ static void __init build_r4000_tlb_refill_handler(void)
1381extern void tlb_do_page_fault_0(void); 1392extern void tlb_do_page_fault_0(void);
1382extern void tlb_do_page_fault_1(void); 1393extern void tlb_do_page_fault_1(void);
1383 1394
1384#define __tlb_handler_align \
1385 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1386
1387/* 1395/*
1388 * 128 instructions for the fastpath handler is generous and should 1396 * 128 instructions for the fastpath handler is generous and should
1389 * never be exceeded. 1397 * never be exceeded.
1390 */ 1398 */
1391#define FASTPATH_SIZE 128 1399#define FASTPATH_SIZE 128
1392 1400
1393u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; 1401u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1394u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; 1402u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1395u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; 1403u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1396 1404
1397static void __init 1405static void __init
1398iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) 1406iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
@@ -1600,7 +1608,6 @@ static void __init build_r3000_tlb_load_handler(void)
1600 u32 *p = handle_tlbl; 1608 u32 *p = handle_tlbl;
1601 struct label *l = labels; 1609 struct label *l = labels;
1602 struct reloc *r = relocs; 1610 struct reloc *r = relocs;
1603 int i;
1604 1611
1605 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1612 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1606 memset(labels, 0, sizeof(labels)); 1613 memset(labels, 0, sizeof(labels));
@@ -1623,11 +1630,7 @@ static void __init build_r3000_tlb_load_handler(void)
1623 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", 1630 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n",
1624 (unsigned int)(p - handle_tlbl)); 1631 (unsigned int)(p - handle_tlbl));
1625 1632
1626 pr_debug("\t.set push\n"); 1633 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1627 pr_debug("\t.set noreorder\n");
1628 for (i = 0; i < (p - handle_tlbl); i++)
1629 pr_debug("\t.word 0x%08x\n", handle_tlbl[i]);
1630 pr_debug("\t.set pop\n");
1631} 1634}
1632 1635
1633static void __init build_r3000_tlb_store_handler(void) 1636static void __init build_r3000_tlb_store_handler(void)
@@ -1635,7 +1638,6 @@ static void __init build_r3000_tlb_store_handler(void)
1635 u32 *p = handle_tlbs; 1638 u32 *p = handle_tlbs;
1636 struct label *l = labels; 1639 struct label *l = labels;
1637 struct reloc *r = relocs; 1640 struct reloc *r = relocs;
1638 int i;
1639 1641
1640 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1642 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1641 memset(labels, 0, sizeof(labels)); 1643 memset(labels, 0, sizeof(labels));
@@ -1658,11 +1660,7 @@ static void __init build_r3000_tlb_store_handler(void)
1658 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", 1660 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n",
1659 (unsigned int)(p - handle_tlbs)); 1661 (unsigned int)(p - handle_tlbs));
1660 1662
1661 pr_debug("\t.set push\n"); 1663 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1662 pr_debug("\t.set noreorder\n");
1663 for (i = 0; i < (p - handle_tlbs); i++)
1664 pr_debug("\t.word 0x%08x\n", handle_tlbs[i]);
1665 pr_debug("\t.set pop\n");
1666} 1664}
1667 1665
1668static void __init build_r3000_tlb_modify_handler(void) 1666static void __init build_r3000_tlb_modify_handler(void)
@@ -1670,7 +1668,6 @@ static void __init build_r3000_tlb_modify_handler(void)
1670 u32 *p = handle_tlbm; 1668 u32 *p = handle_tlbm;
1671 struct label *l = labels; 1669 struct label *l = labels;
1672 struct reloc *r = relocs; 1670 struct reloc *r = relocs;
1673 int i;
1674 1671
1675 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1672 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1676 memset(labels, 0, sizeof(labels)); 1673 memset(labels, 0, sizeof(labels));
@@ -1693,11 +1690,7 @@ static void __init build_r3000_tlb_modify_handler(void)
1693 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", 1690 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n",
1694 (unsigned int)(p - handle_tlbm)); 1691 (unsigned int)(p - handle_tlbm));
1695 1692
1696 pr_debug("\t.set push\n"); 1693 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1697 pr_debug("\t.set noreorder\n");
1698 for (i = 0; i < (p - handle_tlbm); i++)
1699 pr_debug("\t.word 0x%08x\n", handle_tlbm[i]);
1700 pr_debug("\t.set pop\n");
1701} 1694}
1702 1695
1703/* 1696/*
@@ -1750,7 +1743,6 @@ static void __init build_r4000_tlb_load_handler(void)
1750 u32 *p = handle_tlbl; 1743 u32 *p = handle_tlbl;
1751 struct label *l = labels; 1744 struct label *l = labels;
1752 struct reloc *r = relocs; 1745 struct reloc *r = relocs;
1753 int i;
1754 1746
1755 memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1747 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1756 memset(labels, 0, sizeof(labels)); 1748 memset(labels, 0, sizeof(labels));
@@ -1783,11 +1775,7 @@ static void __init build_r4000_tlb_load_handler(void)
1783 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", 1775 pr_info("Synthesized TLB load handler fastpath (%u instructions).\n",
1784 (unsigned int)(p - handle_tlbl)); 1776 (unsigned int)(p - handle_tlbl));
1785 1777
1786 pr_debug("\t.set push\n"); 1778 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1787 pr_debug("\t.set noreorder\n");
1788 for (i = 0; i < (p - handle_tlbl); i++)
1789 pr_debug("\t.word 0x%08x\n", handle_tlbl[i]);
1790 pr_debug("\t.set pop\n");
1791} 1779}
1792 1780
1793static void __init build_r4000_tlb_store_handler(void) 1781static void __init build_r4000_tlb_store_handler(void)
@@ -1795,7 +1783,6 @@ static void __init build_r4000_tlb_store_handler(void)
1795 u32 *p = handle_tlbs; 1783 u32 *p = handle_tlbs;
1796 struct label *l = labels; 1784 struct label *l = labels;
1797 struct reloc *r = relocs; 1785 struct reloc *r = relocs;
1798 int i;
1799 1786
1800 memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1787 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1801 memset(labels, 0, sizeof(labels)); 1788 memset(labels, 0, sizeof(labels));
@@ -1819,11 +1806,7 @@ static void __init build_r4000_tlb_store_handler(void)
1819 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", 1806 pr_info("Synthesized TLB store handler fastpath (%u instructions).\n",
1820 (unsigned int)(p - handle_tlbs)); 1807 (unsigned int)(p - handle_tlbs));
1821 1808
1822 pr_debug("\t.set push\n"); 1809 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1823 pr_debug("\t.set noreorder\n");
1824 for (i = 0; i < (p - handle_tlbs); i++)
1825 pr_debug("\t.word 0x%08x\n", handle_tlbs[i]);
1826 pr_debug("\t.set pop\n");
1827} 1810}
1828 1811
1829static void __init build_r4000_tlb_modify_handler(void) 1812static void __init build_r4000_tlb_modify_handler(void)
@@ -1831,7 +1814,6 @@ static void __init build_r4000_tlb_modify_handler(void)
1831 u32 *p = handle_tlbm; 1814 u32 *p = handle_tlbm;
1832 struct label *l = labels; 1815 struct label *l = labels;
1833 struct reloc *r = relocs; 1816 struct reloc *r = relocs;
1834 int i;
1835 1817
1836 memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1818 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1837 memset(labels, 0, sizeof(labels)); 1819 memset(labels, 0, sizeof(labels));
@@ -1856,11 +1838,7 @@ static void __init build_r4000_tlb_modify_handler(void)
1856 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", 1838 pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n",
1857 (unsigned int)(p - handle_tlbm)); 1839 (unsigned int)(p - handle_tlbm));
1858 1840
1859 pr_debug("\t.set push\n"); 1841 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1860 pr_debug("\t.set noreorder\n");
1861 for (i = 0; i < (p - handle_tlbm); i++)
1862 pr_debug("\t.word 0x%08x\n", handle_tlbm[i]);
1863 pr_debug("\t.set pop\n");
1864} 1842}
1865 1843
1866void __init build_tlb_refill_handler(void) 1844void __init build_tlb_refill_handler(void)
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index bdfa07aecd97..ccbea229a0e6 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -19,7 +19,7 @@
19#define M_PERFCTL_SUPERVISOR (1UL << 2) 19#define M_PERFCTL_SUPERVISOR (1UL << 2)
20#define M_PERFCTL_USER (1UL << 3) 20#define M_PERFCTL_USER (1UL << 3)
21#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) 21#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
22#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5) 22#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
23#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 23#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
24#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 24#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
25#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 25#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 47f316c86ab1..30ed36125bcd 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -178,8 +178,8 @@ struct pci_ops bcm1480_pci_ops = {
178 178
179static struct resource bcm1480_mem_resource = { 179static struct resource bcm1480_mem_resource = {
180 .name = "BCM1480 PCI MEM", 180 .name = "BCM1480 PCI MEM",
181 .start = 0x30000000UL, 181 .start = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES,
182 .end = 0x3fffffffUL, 182 .end = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL,
183 .flags = IORESOURCE_MEM, 183 .flags = IORESOURCE_MEM,
184}; 184};
185 185
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index a63e3bd6b0ac..005e7fecab08 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -173,8 +173,8 @@ struct pci_ops bcm1480ht_pci_ops = {
173 173
174static struct resource bcm1480ht_mem_resource = { 174static struct resource bcm1480ht_mem_resource = {
175 .name = "BCM1480 HT MEM", 175 .name = "BCM1480 HT MEM",
176 .start = 0x40000000UL, 176 .start = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES,
177 .end = 0x5fffffffUL, 177 .end = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES + 0x1fffffffUL,
178 .flags = IORESOURCE_MEM, 178 .flags = IORESOURCE_MEM,
179}; 179};
180 180
diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c
index 2ce298f4d19a..92d764c97701 100644
--- a/arch/mips/philips/pnx8550/common/setup.c
+++ b/arch/mips/philips/pnx8550/common/setup.c
@@ -74,7 +74,7 @@ struct resource standard_io_resources[] = {
74 }, 74 },
75}; 75};
76 76
77#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) 77#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
78 78
79extern struct resource pci_io_resource; 79extern struct resource pci_io_resource;
80extern struct resource pci_mem_resource; 80extern struct resource pci_mem_resource;
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 6d494e0de3d9..62f495b57f93 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -47,11 +47,6 @@ static struct clocksource pnx_clocksource = {
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48}; 48};
49 49
50static void timer_ack(void)
51{
52 write_c0_compare(cpj);
53}
54
55static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) 50static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
56{ 51{
57 struct clock_event_device *c = dev_id; 52 struct clock_event_device *c = dev_id;
@@ -94,30 +89,22 @@ static struct clock_event_device pnx8xxx_clockevent = {
94 .set_next_event = pnx8xxx_set_next_event, 89 .set_next_event = pnx8xxx_set_next_event,
95}; 90};
96 91
97/* 92static inline void timer_ack(void)
98 * plat_time_init() - it does the following things: 93{
99 * 94 write_c0_compare(cpj);
100 * 1) plat_time_init() - 95}
101 * a) (optional) set up RTC routines,
102 * b) (optional) calibrate and set the mips_hpt_frequency
103 * (only needed if you intended to use cpu counter as timer interrupt
104 * source)
105 */
106 96
107__init void plat_time_init(void) 97__init void plat_time_init(void)
108{ 98{
109 unsigned int configPR; 99 unsigned int configPR;
110 unsigned int n; 100 unsigned int n;
111 unsigned int m; 101 unsigned int m;
112 unsigned int p; 102 unsigned int p;
113 unsigned int pow2p; 103 unsigned int pow2p;
114 104
115 clockevents_register_device(&pnx8xxx_clockevent); 105 clockevents_register_device(&pnx8xxx_clockevent);
116 clocksource_register(&pnx_clocksource); 106 clocksource_register(&pnx_clocksource);
117 107
118 setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
119 setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
120
121 /* Timer 1 start */ 108 /* Timer 1 start */
122 configPR = read_c0_config7(); 109 configPR = read_c0_config7();
123 configPR &= ~0x00000008; 110 configPR &= ~0x00000008;
@@ -158,6 +145,6 @@ __init void plat_time_init(void)
158 write_c0_count2(0); 145 write_c0_count2(0);
159 write_c0_compare2(0xffffffff); 146 write_c0_compare2(0xffffffff);
160 147
148 setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
149 setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
161} 150}
162
163
diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c
index cfd90fa3d799..90b4d35f3ece 100644
--- a/arch/mips/philips/pnx8550/jbs/init.c
+++ b/arch/mips/philips/pnx8550/jbs/init.c
@@ -45,11 +45,8 @@ const char *get_system_type(void)
45 45
46void __init prom_init(void) 46void __init prom_init(void)
47{ 47{
48
49 unsigned long memsize; 48 unsigned long memsize;
50 49
51 mips_machtype = MACH_PHILIPS_JBS;
52
53 //memsize = 0x02800000; /* Trimedia uses memory above */ 50 //memsize = 0x02800000; /* Trimedia uses memory above */
54 memsize = 0x08000000; /* Trimedia uses memory above */ 51 memsize = 0x08000000; /* Trimedia uses memory above */
55 add_memory_region(0, memsize, BOOT_MEM_RAM); 52 add_memory_region(0, memsize, BOOT_MEM_RAM);
diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c
index fdb33ed089b9..832dd60b0a7a 100644
--- a/arch/mips/philips/pnx8550/stb810/prom_init.c
+++ b/arch/mips/philips/pnx8550/stb810/prom_init.c
@@ -41,8 +41,6 @@ void __init prom_init(void)
41 41
42 prom_init_cmdline(); 42 prom_init_cmdline();
43 43
44 mips_machtype = MACH_PHILIPS_STB810;
45
46 memsize = 0x08000000; /* Trimedia uses memory above */ 44 memsize = 0x08000000; /* Trimedia uses memory above */
47 add_memory_region(0, memsize, BOOT_MEM_RAM); 45 add_memory_region(0, memsize, BOOT_MEM_RAM);
48} 46}
diff --git a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h b/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h
deleted file mode 100644
index 31c5523276fa..000000000000
--- a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * arch/mips/pmc-sierra/yosemite/i2c-yosemite.h
3 *
4 * Copyright (C) 2003 PMC-Sierra Inc.
5 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#ifndef __I2C_YOSEMITE_H
29#define __I2C_YOSEMITE_H
30
31/* Read and Write operations to the chip */
32
33#define TITAN_I2C_BASE 0xbb000000 /* XXX Needs to change */
34
35#define TITAN_I2C_WRITE(offset, data) \
36 *(volatile unsigned long *)(TITAN_I2C_BASE + offset) = data
37
38#define TITAN_I2C_READ(offset) *(volatile unsigned long *)(TITAN_I2C_BASE + offset)
39
40
41/* Local constansts*/
42#define TITAN_I2C_MAX_FILTER 15
43#define TITAN_I2C_MAX_CLK 1023
44#define TITAN_I2C_MAX_ARBF 15
45#define TITAN_I2C_MAX_NAK 15
46#define TITAN_I2C_MAX_MASTERCODE 7
47#define TITAN_I2C_MAX_WORDS_PER_RW 4
48#define TITAN_I2C_MAX_POLL 100
49
50/* Registers used for I2C work */
51#define TITAN_I2C_SCMB_CONTROL 0x0180 /* SCMB Control */
52#define TITAN_I2C_SCMB_CLOCK_A 0x0184 /* SCMB Clock A */
53#define TITAN_I2C_SCMB_CLOCK_B 0x0188 /* SCMB Clock B */
54#define TITAN_I2C_CONFIG 0x01A0 /* I2C Config */
55#define TITAN_I2C_COMMAND 0x01A4 /* I2C Command */
56#define TITAN_I2C_SLAVE_ADDRESS 0x01A8 /* I2C Slave Address */
57#define TITAN_I2C_DATA 0x01AC /* I2C Data [15:0] */
58#define TITAN_I2C_INTERRUPTS 0x01BC /* I2C Interrupts */
59
60/* Error */
61#define TITAN_I2C_ERR_ARB_LOST (-9220)
62#define TITAN_I2C_ERR_NO_RESP (-9221)
63#define TITAN_I2C_ERR_DATA_COLLISION (-9222)
64#define TITAN_I2C_ERR_TIMEOUT (-9223)
65#define TITAN_I2C_ERR_OK 0
66
67/* I2C Command Type */
68typedef enum {
69 TITAN_I2C_CMD_WRITE = 0,
70 TITAN_I2C_CMD_READ = 1,
71 TITAN_I2C_CMD_READ_WRITE = 2
72} titan_i2c_cmd_type;
73
74/* I2C structures */
75typedef struct {
76 int filtera; /* Register 0x0184, bits 15 - 12 */
77 int clka; /* Register 0x0184, bits 9 - 0 */
78 int filterb; /* Register 0x0188, bits 15 - 12 */
79 int clkb; /* Register 0x0188, bits 9 - 0 */
80} titan_i2c_config;
81
82/* I2C command type */
83typedef struct {
84 titan_i2c_cmd_type type; /* Type of command */
85 int num_arb; /* Register 0x01a0, bits 15 - 12 */
86 int num_nak; /* Register 0x01a0, bits 11 - 8 */
87 int addr_size; /* Register 0x01a0, bit 7 */
88 int mst_code; /* Register 0x01a0, bits 6 - 4 */
89 int arb_en; /* Register 0x01a0, bit 1 */
90 int speed; /* Register 0x01a0, bit 0 */
91 int slave_addr; /* Register 0x01a8 */
92 int write_size; /* Register 0x01a4, bits 10 - 8 */
93 unsigned int *data; /* Register 0x01ac */
94} titan_i2c_command;
95
96#endif /* __I2C_YOSEMITE_H */
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
index 9b9936de6589..35dc435846a6 100644
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ b/arch/mips/pmc-sierra/yosemite/prom.c
@@ -19,6 +19,7 @@
19#include <asm/pgtable.h> 19#include <asm/pgtable.h>
20#include <asm/processor.h> 20#include <asm/processor.h>
21#include <asm/reboot.h> 21#include <asm/reboot.h>
22#include <asm/smp-ops.h>
22#include <asm/system.h> 23#include <asm/system.h>
23#include <asm/bootinfo.h> 24#include <asm/bootinfo.h>
24#include <asm/pmon.h> 25#include <asm/pmon.h>
@@ -78,6 +79,8 @@ static void prom_halt(void)
78 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); 79 __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
79} 80}
80 81
82extern struct plat_smp_ops yos_smp_ops;
83
81/* 84/*
82 * Init routine which accepts the variables from PMON 85 * Init routine which accepts the variables from PMON
83 */ 86 */
@@ -126,9 +129,9 @@ void __init prom_init(void)
126 env++; 129 env++;
127 } 130 }
128 131
129 mips_machtype = MACH_TITAN_YOSEMITE;
130
131 prom_grab_secondary(); 132 prom_grab_secondary();
133
134 register_smp_ops(&yos_smp_ops);
132} 135}
133 136
134void __init prom_free_prom_memory(void) 137void __init prom_free_prom_memory(void)
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index b0f12cd2968a..653f3ec61cab 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -42,70 +42,6 @@ void __init prom_grab_secondary(void)
42 launchstack + LAUNCHSTACK_SIZE, 0); 42 launchstack + LAUNCHSTACK_SIZE, 0);
43} 43}
44 44
45/*
46 * Detect available CPUs, populate phys_cpu_present_map before smp_init
47 *
48 * We don't want to start the secondary CPU yet nor do we have a nice probing
49 * feature in PMON so we just assume presence of the secondary core.
50 */
51void __init plat_smp_setup(void)
52{
53 int i;
54
55 cpus_clear(phys_cpu_present_map);
56
57 for (i = 0; i < 2; i++) {
58 cpu_set(i, phys_cpu_present_map);
59 __cpu_number_map[i] = i;
60 __cpu_logical_map[i] = i;
61 }
62}
63
64void __init plat_prepare_cpus(unsigned int max_cpus)
65{
66 /*
67 * Be paranoid. Enable the IPI only if we're really about to go SMP.
68 */
69 if (cpus_weight(cpu_possible_map))
70 set_c0_status(STATUSF_IP5);
71}
72
73/*
74 * Firmware CPU startup hook
75 * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
76 * It launches the next * available CPU and copies some information on the
77 * stack so the first thing we do is throw away that stuff and load useful
78 * values into the registers ...
79 */
80void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
81{
82 unsigned long gp = (unsigned long) task_thread_info(idle);
83 unsigned long sp = __KSTK_TOS(idle);
84
85 secondary_sp = sp;
86 secondary_gp = gp;
87
88 spin_unlock(&launch_lock);
89}
90
91/* Hook for after all CPUs are online */
92void prom_cpus_done(void)
93{
94}
95
96/*
97 * After we've done initial boot, this function is called to allow the
98 * board code to clean up state, if needed
99 */
100void __cpuinit prom_init_secondary(void)
101{
102 set_c0_status(ST0_CO | ST0_IE | ST0_IM);
103}
104
105void __cpuinit prom_smp_finish(void)
106{
107}
108
109void titan_mailbox_irq(void) 45void titan_mailbox_irq(void)
110{ 46{
111 int cpu = smp_processor_id(); 47 int cpu = smp_processor_id();
@@ -133,7 +69,7 @@ void titan_mailbox_irq(void)
133/* 69/*
134 * Send inter-processor interrupt 70 * Send inter-processor interrupt
135 */ 71 */
136void core_send_ipi(int cpu, unsigned int action) 72static void yos_send_ipi_single(int cpu, unsigned int action)
137{ 73{
138 /* 74 /*
139 * Generate an INTMSG so that it can be sent over to the 75 * Generate an INTMSG so that it can be sent over to the
@@ -159,3 +95,86 @@ void core_send_ipi(int cpu, unsigned int action)
159 break; 95 break;
160 } 96 }
161} 97}
98
99static void yos_send_ipi_mask(cpumask_t mask, unsigned int action)
100{
101 unsigned int i;
102
103 for_each_cpu_mask(i, mask)
104 yos_send_ipi_single(i, action);
105}
106
107/*
108 * After we've done initial boot, this function is called to allow the
109 * board code to clean up state, if needed
110 */
111static void __cpuinit yos_init_secondary(void)
112{
113 set_c0_status(ST0_CO | ST0_IE | ST0_IM);
114}
115
116static void __cpuinit yos_smp_finish(void)
117{
118}
119
120/* Hook for after all CPUs are online */
121static void yos_cpus_done(void)
122{
123}
124
125/*
126 * Firmware CPU startup hook
127 * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
128 * It launches the next * available CPU and copies some information on the
129 * stack so the first thing we do is throw away that stuff and load useful
130 * values into the registers ...
131 */
132static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
133{
134 unsigned long gp = (unsigned long) task_thread_info(idle);
135 unsigned long sp = __KSTK_TOS(idle);
136
137 secondary_sp = sp;
138 secondary_gp = gp;
139
140 spin_unlock(&launch_lock);
141}
142
143/*
144 * Detect available CPUs, populate phys_cpu_present_map before smp_init
145 *
146 * We don't want to start the secondary CPU yet nor do we have a nice probing
147 * feature in PMON so we just assume presence of the secondary core.
148 */
149static void __init yos_smp_setup(void)
150{
151 int i;
152
153 cpus_clear(phys_cpu_present_map);
154
155 for (i = 0; i < 2; i++) {
156 cpu_set(i, phys_cpu_present_map);
157 __cpu_number_map[i] = i;
158 __cpu_logical_map[i] = i;
159 }
160}
161
162static void __init yos_prepare_cpus(unsigned int max_cpus)
163{
164 /*
165 * Be paranoid. Enable the IPI only if we're really about to go SMP.
166 */
167 if (cpus_weight(cpu_possible_map))
168 set_c0_status(STATUSF_IP5);
169}
170
171struct plat_smp_ops yos_smp_ops = {
172 .send_ipi_single = yos_send_ipi_single,
173 .send_ipi_mask = yos_send_ipi_mask,
174 .init_secondary = yos_init_secondary,
175 .smp_finish = yos_smp_finish,
176 .cpus_done = yos_cpus_done,
177 .boot_secondary = yos_boot_secondary,
178 .smp_setup = yos_smp_setup,
179 .prepare_cpus = yos_prepare_cpus,
180};
diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile
deleted file mode 100644
index 2ba4ef34b4a7..000000000000
--- a/arch/mips/qemu/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
1#
2# Makefile for Qemu specific kernel interface routines under Linux.
3#
4
5obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o
6
7obj-$(CONFIG_EARLY_PRINTK) += q-console.o
8obj-$(CONFIG_SMP) += q-smp.o
9
10EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/qemu/q-console.c b/arch/mips/qemu/q-console.c
deleted file mode 100644
index 81101ae5017a..000000000000
--- a/arch/mips/qemu/q-console.c
+++ /dev/null
@@ -1,26 +0,0 @@
1#include <linux/console.h>
2#include <linux/init.h>
3#include <linux/serial_reg.h>
4#include <asm/io.h>
5
6#define PORT(offset) (0x3f8 + (offset))
7
8static inline unsigned int serial_in(int offset)
9{
10 return inb(PORT(offset));
11}
12
13static inline void serial_out(int offset, int value)
14{
15 outb(value, PORT(offset));
16}
17
18int prom_putchar(char c)
19{
20 while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
21 ;
22
23 serial_out(UART_TX, c);
24
25 return 1;
26}
diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c
deleted file mode 100644
index 3ed43f416cd1..000000000000
--- a/arch/mips/qemu/q-firmware.c
+++ /dev/null
@@ -1,24 +0,0 @@
1#include <linux/init.h>
2#include <linux/string.h>
3#include <asm/addrspace.h>
4#include <asm/bootinfo.h>
5#include <asm/io.h>
6
7#define QEMU_PORT_BASE 0xb4000000
8
9void __init prom_init(void)
10{
11 int *cmdline;
12
13 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260);
14 if (*cmdline == 0x12345678) {
15 if (*(char *)(cmdline + 1))
16 strcpy(arcs_cmdline, (char *)(cmdline + 1));
17 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM);
18 } else {
19 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
20 }
21
22
23 set_io_port_base(QEMU_PORT_BASE);
24}
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
deleted file mode 100644
index 7df36dbe65c7..000000000000
--- a/arch/mips/qemu/q-irq.c
+++ /dev/null
@@ -1,37 +0,0 @@
1#include <linux/init.h>
2#include <linux/interrupt.h>
3#include <linux/linkage.h>
4
5#include <asm/i8259.h>
6#include <asm/irq_cpu.h>
7#include <asm/mipsregs.h>
8#include <asm/qemu.h>
9#include <asm/system.h>
10#include <asm/time.h>
11
12asmlinkage void plat_irq_dispatch(void)
13{
14 unsigned int pending = read_c0_status() & read_c0_cause();
15
16 if (pending & 0x8000) {
17 do_IRQ(Q_COUNT_COMPARE_IRQ);
18 return;
19 }
20 if (pending & 0x0400) {
21 int irq = i8259_irq();
22
23 if (likely(irq >= 0))
24 do_IRQ(irq);
25
26 return;
27 }
28}
29
30void __init arch_init_irq(void)
31{
32 mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */
33
34 mips_cpu_irq_init();
35 init_i8259_irqs();
36 set_c0_status(0x400);
37}
diff --git a/arch/mips/qemu/q-mem.c b/arch/mips/qemu/q-mem.c
deleted file mode 100644
index dae39b59de15..000000000000
--- a/arch/mips/qemu/q-mem.c
+++ /dev/null
@@ -1,5 +0,0 @@
1#include <linux/init.h>
2
3void __init prom_free_prom_memory(void)
4{
5}
diff --git a/arch/mips/qemu/q-reset.c b/arch/mips/qemu/q-reset.c
deleted file mode 100644
index dbbe44ad7e89..000000000000
--- a/arch/mips/qemu/q-reset.c
+++ /dev/null
@@ -1,33 +0,0 @@
1
2#include <asm/io.h>
3#include <asm/reboot.h>
4#include <asm/cacheflush.h>
5#include <asm/qemu.h>
6
7static void qemu_machine_restart(char *command)
8{
9 volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG;
10
11 set_c0_status(ST0_BEV | ST0_ERL);
12 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
13 flush_cache_all();
14 write_c0_wired(0);
15 *reg = 42;
16 while (1)
17 cpu_wait();
18}
19
20static void qemu_machine_halt(void)
21{
22 volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG;
23
24 *reg = 42;
25 while (1)
26 cpu_wait();
27}
28
29void qemu_reboot_setup(void)
30{
31 _machine_restart = qemu_machine_restart;
32 _machine_halt = qemu_machine_halt;
33}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
deleted file mode 100644
index 969cedc8d8b9..000000000000
--- a/arch/mips/qemu/q-setup.c
+++ /dev/null
@@ -1,22 +0,0 @@
1#include <linux/init.h>
2
3#include <asm/i8253.h>
4#include <asm/io.h>
5#include <asm/time.h>
6
7extern void qemu_reboot_setup(void);
8
9const char *get_system_type(void)
10{
11 return "Qemu";
12}
13
14void __init plat_time_init(void)
15{
16 setup_pit_timer();
17}
18
19void __init plat_mem_setup(void)
20{
21 qemu_reboot_setup();
22}
diff --git a/arch/mips/qemu/q-smp.c b/arch/mips/qemu/q-smp.c
deleted file mode 100644
index 4b0178d0df0b..000000000000
--- a/arch/mips/qemu/q-smp.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
7 *
8 * Symmetric Uniprocessor (TM) Support
9 */
10#include <linux/kernel.h>
11#include <linux/sched.h>
12
13/*
14 * Send inter-processor interrupt
15 */
16void core_send_ipi(int cpu, unsigned int action)
17{
18 panic(KERN_ERR "%s called", __FUNCTION__);
19}
20
21/*
22 * After we've done initial boot, this function is called to allow the
23 * board code to clean up state, if needed
24 */
25void __cpuinit prom_init_secondary(void)
26{
27}
28
29void __cpuinit prom_smp_finish(void)
30{
31}
32
33/* Hook for after all CPUs are online */
34void prom_cpus_done(void)
35{
36}
37
38void __init prom_prepare_cpus(unsigned int max_cpus)
39{
40 cpus_clear(phys_cpu_present_map);
41}
42
43/*
44 * Firmware CPU startup hook
45 */
46void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
47{
48}
49
50void __init plat_smp_setup(void)
51{
52}
53void __init plat_prepare_cpus(unsigned int max_cpus)
54{
55}
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index e3acb51b70b5..ef1564e40c8d 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -3,9 +3,11 @@
3# under Linux. 3# under Linux.
4# 4#
5 5
6obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-berr.o \ 6obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \
7 ip22-time.o ip22-nvram.o ip22-platform.o ip22-reset.o ip22-setup.o 7 ip22-platform.o ip22-reset.o ip22-setup.o
8 8
9obj-$(CONFIG_SGI_IP22) += ip22-berr.o
10obj-$(CONFIG_SGI_IP28) += ip28-berr.o
9obj-$(CONFIG_EISA) += ip22-eisa.o 11obj-$(CONFIG_EISA) += ip22-eisa.o
10 12
11EXTRA_CFLAGS += -Werror 13# EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
index 01a805dcc67c..3f35d6367bec 100644
--- a/arch/mips/sgi-ip22/ip22-mc.c
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -4,6 +4,7 @@
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
5 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes 5 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
6 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) 6 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
7 * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28
7 */ 8 */
8 9
9#include <linux/init.h> 10#include <linux/init.h>
@@ -137,9 +138,12 @@ void __init sgimc_init(void)
137 /* Step 2: Enable all parity checking in cpu control register 138 /* Step 2: Enable all parity checking in cpu control register
138 * zero. 139 * zero.
139 */ 140 */
141 /* don't touch parity settings for IP28 */
142#ifndef CONFIG_SGI_IP28
140 tmp = sgimc->cpuctrl0; 143 tmp = sgimc->cpuctrl0;
141 tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | 144 tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
142 SGIMC_CCTRL0_R4KNOCHKPARR); 145 SGIMC_CCTRL0_R4KNOCHKPARR);
146#endif
143 sgimc->cpuctrl0 = tmp; 147 sgimc->cpuctrl0 = tmp;
144 148
145 /* Step 3: Setup the MC write buffer depth, this is controlled 149 /* Step 3: Setup the MC write buffer depth, this is controlled
diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c
new file mode 100644
index 000000000000..30e12e2ec4b5
--- /dev/null
+++ b/arch/mips/sgi-ip22/ip28-berr.c
@@ -0,0 +1,502 @@
1/*
2 * ip28-berr.c: Bus error handling.
3 *
4 * Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org)
5 * Copyright (C) 2005 Peter Fuerst (pf@net.alphadv.de) - IP28
6 */
7
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/seq_file.h>
12
13#include <asm/addrspace.h>
14#include <asm/system.h>
15#include <asm/traps.h>
16#include <asm/branch.h>
17#include <asm/irq_regs.h>
18#include <asm/sgi/mc.h>
19#include <asm/sgi/hpc3.h>
20#include <asm/sgi/ioc.h>
21#include <asm/sgi/ip22.h>
22#include <asm/r4kcache.h>
23#include <asm/uaccess.h>
24#include <asm/bootinfo.h>
25
26static unsigned int count_be_is_fixup;
27static unsigned int count_be_handler;
28static unsigned int count_be_interrupt;
29static int debug_be_interrupt;
30
31static unsigned int cpu_err_stat; /* Status reg for CPU */
32static unsigned int gio_err_stat; /* Status reg for GIO */
33static unsigned int cpu_err_addr; /* Error address reg for CPU */
34static unsigned int gio_err_addr; /* Error address reg for GIO */
35static unsigned int extio_stat;
36static unsigned int hpc3_berr_stat; /* Bus error interrupt status */
37
38struct hpc3_stat {
39 unsigned long addr;
40 unsigned int ctrl;
41 unsigned int cbp;
42 unsigned int ndptr;
43};
44
45static struct {
46 struct hpc3_stat pbdma[8];
47 struct hpc3_stat scsi[2];
48 struct hpc3_stat ethrx, ethtx;
49} hpc3;
50
51static struct {
52 unsigned long err_addr;
53 struct {
54 u32 lo;
55 u32 hi;
56 } tags[1][2], tagd[4][2], tagi[4][2]; /* Way 0/1 */
57} cache_tags;
58
59static inline void save_cache_tags(unsigned busaddr)
60{
61 unsigned long addr = CAC_BASE | busaddr;
62 int i;
63 cache_tags.err_addr = addr;
64
65 /*
66 * Starting with a bus-address, save secondary cache (indexed by
67 * PA[23..18:7..6]) tags first.
68 */
69 addr &= ~1L;
70#define tag cache_tags.tags[0]
71 cache_op(Index_Load_Tag_S, addr);
72 tag[0].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */
73 tag[0].hi = read_c0_taghi(); /* PA[39:36] */
74 cache_op(Index_Load_Tag_S, addr | 1L);
75 tag[1].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */
76 tag[1].hi = read_c0_taghi(); /* PA[39:36] */
77#undef tag
78
79 /*
80 * Save all primary data cache (indexed by VA[13:5]) tags which
81 * might fit to this bus-address, knowing that VA[11:0] == PA[11:0].
82 * Saving all tags and evaluating them later is easier and safer
83 * than relying on VA[13:12] from the secondary cache tags to pick
84 * matching primary tags here already.
85 */
86 addr &= (0xffL << 56) | ((1 << 12) - 1);
87#define tag cache_tags.tagd[i]
88 for (i = 0; i < 4; ++i, addr += (1 << 12)) {
89 cache_op(Index_Load_Tag_D, addr);
90 tag[0].lo = read_c0_taglo(); /* PA[35:12] */
91 tag[0].hi = read_c0_taghi(); /* PA[39:36] */
92 cache_op(Index_Load_Tag_D, addr | 1L);
93 tag[1].lo = read_c0_taglo(); /* PA[35:12] */
94 tag[1].hi = read_c0_taghi(); /* PA[39:36] */
95 }
96#undef tag
97
98 /*
99 * Save primary instruction cache (indexed by VA[13:6]) tags
100 * the same way.
101 */
102 addr &= (0xffL << 56) | ((1 << 12) - 1);
103#define tag cache_tags.tagi[i]
104 for (i = 0; i < 4; ++i, addr += (1 << 12)) {
105 cache_op(Index_Load_Tag_I, addr);
106 tag[0].lo = read_c0_taglo(); /* PA[35:12] */
107 tag[0].hi = read_c0_taghi(); /* PA[39:36] */
108 cache_op(Index_Load_Tag_I, addr | 1L);
109 tag[1].lo = read_c0_taglo(); /* PA[35:12] */
110 tag[1].hi = read_c0_taghi(); /* PA[39:36] */
111 }
112#undef tag
113}
114
115#define GIO_ERRMASK 0xff00
116#define CPU_ERRMASK 0x3f00
117
118static void save_and_clear_buserr(void)
119{
120 int i;
121
122 /* save status registers */
123 cpu_err_addr = sgimc->cerr;
124 cpu_err_stat = sgimc->cstat;
125 gio_err_addr = sgimc->gerr;
126 gio_err_stat = sgimc->gstat;
127 extio_stat = sgioc->extio;
128 hpc3_berr_stat = hpc3c0->bestat;
129
130 hpc3.scsi[0].addr = (unsigned long)&hpc3c0->scsi_chan0;
131 hpc3.scsi[0].ctrl = hpc3c0->scsi_chan0.ctrl; /* HPC3_SCTRL_ACTIVE ? */
132 hpc3.scsi[0].cbp = hpc3c0->scsi_chan0.cbptr;
133 hpc3.scsi[0].ndptr = hpc3c0->scsi_chan0.ndptr;
134
135 hpc3.scsi[1].addr = (unsigned long)&hpc3c0->scsi_chan1;
136 hpc3.scsi[1].ctrl = hpc3c0->scsi_chan1.ctrl; /* HPC3_SCTRL_ACTIVE ? */
137 hpc3.scsi[1].cbp = hpc3c0->scsi_chan1.cbptr;
138 hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr;
139
140 hpc3.ethrx.addr = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
141 hpc3.ethrx.ctrl = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
142 hpc3.ethrx.cbp = hpc3c0->ethregs.rx_cbptr;
143 hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr;
144
145 hpc3.ethtx.addr = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
146 hpc3.ethtx.ctrl = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
147 hpc3.ethtx.cbp = hpc3c0->ethregs.tx_cbptr;
148 hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr;
149
150 for (i = 0; i < 8; ++i) {
151 /* HPC3_PDMACTRL_ISACT ? */
152 hpc3.pbdma[i].addr = (unsigned long)&hpc3c0->pbdma[i];
153 hpc3.pbdma[i].ctrl = hpc3c0->pbdma[i].pbdma_ctrl;
154 hpc3.pbdma[i].cbp = hpc3c0->pbdma[i].pbdma_bptr;
155 hpc3.pbdma[i].ndptr = hpc3c0->pbdma[i].pbdma_dptr;
156 }
157 i = 0;
158 if (gio_err_stat & CPU_ERRMASK)
159 i = gio_err_addr;
160 if (cpu_err_stat & CPU_ERRMASK)
161 i = cpu_err_addr;
162 save_cache_tags(i);
163
164 sgimc->cstat = sgimc->gstat = 0;
165}
166
167static void print_cache_tags(void)
168{
169 u32 scb, scw;
170 int i;
171
172 printk(KERN_ERR "Cache tags @ %08x:\n", (unsigned)cache_tags.err_addr);
173
174 /* PA[31:12] shifted to PTag0 (PA[35:12]) format */
175 scw = (cache_tags.err_addr >> 4) & 0x0fffff00;
176
177 scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 5) - 1);
178 for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */
179 if ((cache_tags.tagd[i][0].lo & 0x0fffff00) != scw &&
180 (cache_tags.tagd[i][1].lo & 0x0fffff00) != scw)
181 continue;
182 printk(KERN_ERR
183 "D: 0: %08x %08x, 1: %08x %08x (VA[13:5] %04x)\n",
184 cache_tags.tagd[i][0].hi, cache_tags.tagd[i][0].lo,
185 cache_tags.tagd[i][1].hi, cache_tags.tagd[i][1].lo,
186 scb | (1 << 12)*i);
187 }
188 scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 6) - 1);
189 for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */
190 if ((cache_tags.tagi[i][0].lo & 0x0fffff00) != scw &&
191 (cache_tags.tagi[i][1].lo & 0x0fffff00) != scw)
192 continue;
193 printk(KERN_ERR
194 "I: 0: %08x %08x, 1: %08x %08x (VA[13:6] %04x)\n",
195 cache_tags.tagi[i][0].hi, cache_tags.tagi[i][0].lo,
196 cache_tags.tagi[i][1].hi, cache_tags.tagi[i][1].lo,
197 scb | (1 << 12)*i);
198 }
199 i = read_c0_config();
200 scb = i & (1 << 13) ? 7:6; /* scblksize = 2^[7..6] */
201 scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */
202
203 i = ((1 << scw) - 1) & ~((1 << scb) - 1);
204 printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x (PA[%u:%u] %05x)\n",
205 cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo,
206 cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo,
207 scw-1, scb, i & (unsigned)cache_tags.err_addr);
208}
209
210static inline const char *cause_excode_text(int cause)
211{
212 static const char *txt[32] =
213 { "Interrupt",
214 "TLB modification",
215 "TLB (load or instruction fetch)",
216 "TLB (store)",
217 "Address error (load or instruction fetch)",
218 "Address error (store)",
219 "Bus error (instruction fetch)",
220 "Bus error (data: load or store)",
221 "Syscall",
222 "Breakpoint",
223 "Reserved instruction",
224 "Coprocessor unusable",
225 "Arithmetic Overflow",
226 "Trap",
227 "14",
228 "Floating-Point",
229 "16", "17", "18", "19", "20", "21", "22",
230 "Watch Hi/Lo",
231 "24", "25", "26", "27", "28", "29", "30", "31",
232 };
233 return txt[(cause & 0x7c) >> 2];
234}
235
236static void print_buserr(const struct pt_regs *regs)
237{
238 const int field = 2 * sizeof(unsigned long);
239 int error = 0;
240
241 if (extio_stat & EXTIO_MC_BUSERR) {
242 printk(KERN_ERR "MC Bus Error\n");
243 error |= 1;
244 }
245 if (extio_stat & EXTIO_HPC3_BUSERR) {
246 printk(KERN_ERR "HPC3 Bus Error 0x%x:<id=0x%x,%s,lane=0x%x>\n",
247 hpc3_berr_stat,
248 (hpc3_berr_stat & HPC3_BESTAT_PIDMASK) >>
249 HPC3_BESTAT_PIDSHIFT,
250 (hpc3_berr_stat & HPC3_BESTAT_CTYPE) ? "PIO" : "DMA",
251 hpc3_berr_stat & HPC3_BESTAT_BLMASK);
252 error |= 2;
253 }
254 if (extio_stat & EXTIO_EISA_BUSERR) {
255 printk(KERN_ERR "EISA Bus Error\n");
256 error |= 4;
257 }
258 if (cpu_err_stat & CPU_ERRMASK) {
259 printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n",
260 cpu_err_stat,
261 cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "",
262 cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "",
263 cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "",
264 cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "",
265 cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "",
266 cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "",
267 cpu_err_addr);
268 error |= 8;
269 }
270 if (gio_err_stat & GIO_ERRMASK) {
271 printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n",
272 gio_err_stat,
273 gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "",
274 gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "",
275 gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "",
276 gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "",
277 gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "",
278 gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "",
279 gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "",
280 gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "",
281 gio_err_addr);
282 error |= 16;
283 }
284 if (!error)
285 printk(KERN_ERR "MC: Hmm, didn't find any error condition.\n");
286 else {
287 printk(KERN_ERR "CP0: config %08x, "
288 "MC: cpuctrl0/1: %08x/%05x, giopar: %04x\n"
289 "MC: cpu/gio_memacc: %08x/%05x, memcfg0/1: %08x/%08x\n",
290 read_c0_config(),
291 sgimc->cpuctrl0, sgimc->cpuctrl0, sgimc->giopar,
292 sgimc->cmacc, sgimc->gmacc,
293 sgimc->mconfig0, sgimc->mconfig1);
294 print_cache_tags();
295 }
296 printk(KERN_ALERT "%s, epc == %0*lx, ra == %0*lx\n",
297 cause_excode_text(regs->cp0_cause),
298 field, regs->cp0_epc, field, regs->regs[31]);
299}
300
301/*
302 * Check, whether MC's (virtual) DMA address caused the bus error.
303 * See "Virtual DMA Specification", Draft 1.5, Feb 13 1992, SGI
304 */
305
306static int addr_is_ram(unsigned long addr, unsigned sz)
307{
308 int i;
309
310 for (i = 0; i < boot_mem_map.nr_map; i++) {
311 unsigned long a = boot_mem_map.map[i].addr;
312 if (a <= addr && addr+sz <= a+boot_mem_map.map[i].size)
313 return 1;
314 }
315 return 0;
316}
317
318static int check_microtlb(u32 hi, u32 lo, unsigned long vaddr)
319{
320 /* This is likely rather similar to correct code ;-) */
321
322 vaddr &= 0x7fffffff; /* Doc. states that top bit is ignored */
323
324 /* If tlb-entry is valid and VPN-high (bits [30:21] ?) matches... */
325 if ((lo & 2) && (vaddr >> 21) == ((hi<<1) >> 22)) {
326 u32 ctl = sgimc->dma_ctrl;
327 if (ctl & 1) {
328 unsigned int pgsz = (ctl & 2) ? 14:12; /* 16k:4k */
329 /* PTEIndex is VPN-low (bits [22:14]/[20:12] ?) */
330 unsigned long pte = (lo >> 6) << 12; /* PTEBase */
331 pte += 8*((vaddr >> pgsz) & 0x1ff);
332 if (addr_is_ram(pte, 8)) {
333 /*
334 * Note: Since DMA hardware does look up
335 * translation on its own, this PTE *must*
336 * match the TLB/EntryLo-register format !
337 */
338 unsigned long a = *(unsigned long *)
339 PHYS_TO_XKSEG_UNCACHED(pte);
340 a = (a & 0x3f) << 6; /* PFN */
341 a += vaddr & ((1 << pgsz) - 1);
342 return (cpu_err_addr == a);
343 }
344 }
345 }
346 return 0;
347}
348
349static int check_vdma_memaddr(void)
350{
351 if (cpu_err_stat & CPU_ERRMASK) {
352 u32 a = sgimc->maddronly;
353
354 if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */
355 return (cpu_err_addr == a);
356
357 if (check_microtlb(sgimc->dtlb_hi0, sgimc->dtlb_lo0, a) ||
358 check_microtlb(sgimc->dtlb_hi1, sgimc->dtlb_lo1, a) ||
359 check_microtlb(sgimc->dtlb_hi2, sgimc->dtlb_lo2, a) ||
360 check_microtlb(sgimc->dtlb_hi3, sgimc->dtlb_lo3, a))
361 return 1;
362 }
363 return 0;
364}
365
366static int check_vdma_gioaddr(void)
367{
368 if (gio_err_stat & GIO_ERRMASK) {
369 u32 a = sgimc->gio_dma_trans;
370 a = (sgimc->gmaddronly & ~a) | (sgimc->gio_dma_sbits & a);
371 return (gio_err_addr == a);
372 }
373 return 0;
374}
375
376/*
377 * MC sends an interrupt whenever bus or parity errors occur. In addition,
378 * if the error happened during a CPU read, it also asserts the bus error
379 * pin on the R4K. Code in bus error handler save the MC bus error registers
380 * and then clear the interrupt when this happens.
381 */
382
383static int ip28_be_interrupt(const struct pt_regs *regs)
384{
385 int i;
386
387 save_and_clear_buserr();
388 /*
389 * Try to find out, whether we got here by a mispredicted speculative
390 * load/store operation. If so, it's not fatal, we can go on.
391 */
392 /* Any cause other than "Interrupt" (ExcCode 0) is fatal. */
393 if (regs->cp0_cause & CAUSEF_EXCCODE)
394 goto mips_be_fatal;
395
396 /* Any cause other than "Bus error interrupt" (IP6) is weird. */
397 if ((regs->cp0_cause & CAUSEF_IP6) != CAUSEF_IP6)
398 goto mips_be_fatal;
399
400 if (extio_stat & (EXTIO_HPC3_BUSERR | EXTIO_EISA_BUSERR))
401 goto mips_be_fatal;
402
403 /* Any state other than "Memory bus error" is fatal. */
404 if (cpu_err_stat & CPU_ERRMASK & ~SGIMC_CSTAT_ADDR)
405 goto mips_be_fatal;
406
407 /* GIO errors other than timeouts are fatal */
408 if (gio_err_stat & GIO_ERRMASK & ~SGIMC_GSTAT_TIME)
409 goto mips_be_fatal;
410
411 /*
412 * Now we have an asynchronous bus error, speculatively or DMA caused.
413 * Need to search all DMA descriptors for the error address.
414 */
415 for (i = 0; i < sizeof(hpc3)/sizeof(struct hpc3_stat); ++i) {
416 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
417 if ((cpu_err_stat & CPU_ERRMASK) &&
418 (cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp))
419 break;
420 if ((gio_err_stat & GIO_ERRMASK) &&
421 (gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp))
422 break;
423 }
424 if (i < sizeof(hpc3)/sizeof(struct hpc3_stat)) {
425 struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i;
426 printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:"
427 " ctl %08x, ndp %08x, cbp %08x\n",
428 CPHYSADDR(hp->addr), hp->ctrl, hp->ndptr, hp->cbp);
429 goto mips_be_fatal;
430 }
431 /* Check MC's virtual DMA stuff. */
432 if (check_vdma_memaddr()) {
433 printk(KERN_ERR "at GIO DMA: mem address 0x%08x.\n",
434 sgimc->maddronly);
435 goto mips_be_fatal;
436 }
437 if (check_vdma_gioaddr()) {
438 printk(KERN_ERR "at GIO DMA: gio address 0x%08x.\n",
439 sgimc->gmaddronly);
440 goto mips_be_fatal;
441 }
442 /* A speculative bus error... */
443 if (debug_be_interrupt) {
444 print_buserr(regs);
445 printk(KERN_ERR "discarded!\n");
446 }
447 return MIPS_BE_DISCARD;
448
449mips_be_fatal:
450 print_buserr(regs);
451 return MIPS_BE_FATAL;
452}
453
454void ip22_be_interrupt(int irq)
455{
456 const struct pt_regs *regs = get_irq_regs();
457
458 count_be_interrupt++;
459
460 if (ip28_be_interrupt(regs) != MIPS_BE_DISCARD) {
461 /* Assume it would be too dangerous to continue ... */
462 die_if_kernel("Oops", regs);
463 force_sig(SIGBUS, current);
464 } else if (debug_be_interrupt)
465 show_regs((struct pt_regs *)regs);
466}
467
468static int ip28_be_handler(struct pt_regs *regs, int is_fixup)
469{
470 /*
471 * We arrive here only in the unusual case of do_be() invocation,
472 * i.e. by a bus error exception without a bus error interrupt.
473 */
474 if (is_fixup) {
475 count_be_is_fixup++;
476 save_and_clear_buserr();
477 return MIPS_BE_FIXUP;
478 }
479 count_be_handler++;
480 return ip28_be_interrupt(regs);
481}
482
483void __init ip22_be_init(void)
484{
485 board_be_handler = ip28_be_handler;
486}
487
488int ip28_show_be_info(struct seq_file *m)
489{
490 seq_printf(m, "IP28 be fixups\t\t: %u\n", count_be_is_fixup);
491 seq_printf(m, "IP28 be interrupts\t: %u\n", count_be_interrupt);
492 seq_printf(m, "IP28 be handler\t\t: %u\n", count_be_handler);
493
494 return 0;
495}
496
497static int __init debug_be_setup(char *str)
498{
499 debug_be_interrupt++;
500 return 1;
501}
502__setup("ip28_debug_be", debug_be_setup);
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 3305fa9ae66d..a49e7c85f724 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -27,7 +27,6 @@
27#include <asm/sn/hub.h> 27#include <asm/sn/hub.h>
28#include <asm/sn/intr.h> 28#include <asm/sn/intr.h>
29#include <asm/current.h> 29#include <asm/current.h>
30#include <asm/smp.h>
31#include <asm/processor.h> 30#include <asm/processor.h>
32#include <asm/mmu_context.h> 31#include <asm/mmu_context.h>
33#include <asm/thread_info.h> 32#include <asm/thread_info.h>
diff --git a/arch/mips/sgi-ip27/ip27-klnuma.c b/arch/mips/sgi-ip27/ip27-klnuma.c
index f10d9839006d..48932ce1d730 100644
--- a/arch/mips/sgi-ip27/ip27-klnuma.c
+++ b/arch/mips/sgi-ip27/ip27-klnuma.c
@@ -11,7 +11,6 @@
11 11
12#include <asm/page.h> 12#include <asm/page.h>
13#include <asm/sections.h> 13#include <asm/sections.h>
14#include <asm/smp.h>
15#include <asm/sn/types.h> 14#include <asm/sn/types.h>
16#include <asm/sn/arch.h> 15#include <asm/sn/arch.h>
17#include <asm/sn/gda.h> 16#include <asm/sn/gda.h>
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index a70656d42191..f15fc93d6b35 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -140,30 +140,51 @@ static __init void intr_clear_all(nasid_t nasid)
140 REMOTE_HUB_CLR_INTR(nasid, i); 140 REMOTE_HUB_CLR_INTR(nasid, i);
141} 141}
142 142
143void __init plat_smp_setup(void) 143static void ip27_send_ipi_single(int destid, unsigned int action)
144{ 144{
145 cnodeid_t cnode; 145 int irq;
146 146
147 for_each_online_node(cnode) { 147 switch (action) {
148 if (cnode == 0) 148 case SMP_RESCHEDULE_YOURSELF:
149 continue; 149 irq = CPU_RESCHED_A_IRQ;
150 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); 150 break;
151 case SMP_CALL_FUNCTION:
152 irq = CPU_CALL_A_IRQ;
153 break;
154 default:
155 panic("sendintr");
151 } 156 }
152 157
153 replicate_kernel_text(); 158 irq += cputoslice(destid);
154 159
155 /* 160 /*
156 * Assumption to be fixed: we're always booted on logical / physical 161 * Convert the compact hub number to the NASID to get the correct
157 * processor 0. While we're always running on logical processor 0 162 * part of the address space. Then set the interrupt bit associated
158 * this still means this is physical processor zero; it might for 163 * with the CPU we want to send the interrupt to.
159 * example be disabled in the firwware.
160 */ 164 */
161 alloc_cpupda(0, 0); 165 REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq);
162} 166}
163 167
164void __init plat_prepare_cpus(unsigned int max_cpus) 168static void ip27_send_ipi_mask(cpumask_t mask, unsigned int action)
169{
170 unsigned int i;
171
172 for_each_cpu_mask(i, mask)
173 ip27_send_ipi_single(i, action);
174}
175
176static void __cpuinit ip27_init_secondary(void)
177{
178 per_cpu_init();
179 local_irq_enable();
180}
181
182static void __cpuinit ip27_smp_finish(void)
183{
184}
185
186static void __init ip27_cpus_done(void)
165{ 187{
166 /* We already did everything necessary earlier */
167} 188}
168 189
169/* 190/*
@@ -171,7 +192,7 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
171 * set sp to the kernel stack of the newly created idle process, gp to the proc 192 * set sp to the kernel stack of the newly created idle process, gp to the proc
172 * struct so that current_thread_info() will work. 193 * struct so that current_thread_info() will work.
173 */ 194 */
174void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) 195static void __cpuinit ip27_boot_secondary(int cpu, struct task_struct *idle)
175{ 196{
176 unsigned long gp = (unsigned long)task_thread_info(idle); 197 unsigned long gp = (unsigned long)task_thread_info(idle);
177 unsigned long sp = __KSTK_TOS(idle); 198 unsigned long sp = __KSTK_TOS(idle);
@@ -181,41 +202,39 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
181 0, (void *) sp, (void *) gp); 202 0, (void *) sp, (void *) gp);
182} 203}
183 204
184void __cpuinit prom_init_secondary(void) 205static void __init ip27_smp_setup(void)
185{ 206{
186 per_cpu_init(); 207 cnodeid_t cnode;
187 local_irq_enable();
188}
189
190void __init prom_cpus_done(void)
191{
192}
193
194void __cpuinit prom_smp_finish(void)
195{
196}
197
198void core_send_ipi(int destid, unsigned int action)
199{
200 int irq;
201 208
202 switch (action) { 209 for_each_online_node(cnode) {
203 case SMP_RESCHEDULE_YOURSELF: 210 if (cnode == 0)
204 irq = CPU_RESCHED_A_IRQ; 211 continue;
205 break; 212 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode));
206 case SMP_CALL_FUNCTION:
207 irq = CPU_CALL_A_IRQ;
208 break;
209 default:
210 panic("sendintr");
211 } 213 }
212 214
213 irq += cputoslice(destid); 215 replicate_kernel_text();
214 216
215 /* 217 /*
216 * Convert the compact hub number to the NASID to get the correct 218 * Assumption to be fixed: we're always booted on logical / physical
217 * part of the address space. Then set the interrupt bit associated 219 * processor 0. While we're always running on logical processor 0
218 * with the CPU we want to send the interrupt to. 220 * this still means this is physical processor zero; it might for
221 * example be disabled in the firwware.
219 */ 222 */
220 REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq); 223 alloc_cpupda(0, 0);
221} 224}
225
226static void __init ip27_prepare_cpus(unsigned int max_cpus)
227{
228 /* We already did everything necessary earlier */
229}
230
231struct plat_smp_ops ip27_smp_ops = {
232 .send_ipi_single = ip27_send_ipi_single,
233 .send_ipi_mask = ip27_send_ipi_mask,
234 .init_secondary = ip27_init_secondary,
235 .smp_finish = ip27_smp_finish,
236 .cpus_done = ip27_cpus_done,
237 .boot_secondary = ip27_boot_secondary,
238 .smp_setup = ip27_smp_setup,
239 .prepare_cpus = ip27_prepare_cpus,
240};
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 436ba78359ab..183c460b9ca1 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -23,6 +23,7 @@
23 23
24#include <asm/mmu_context.h> 24#include <asm/mmu_context.h>
25#include <asm/io.h> 25#include <asm/io.h>
26#include <asm/fw/cfe/cfe_api.h>
26#include <asm/sibyte/sb1250.h> 27#include <asm/sibyte/sb1250.h>
27#include <asm/sibyte/bcm1480_regs.h> 28#include <asm/sibyte/bcm1480_regs.h>
28#include <asm/sibyte/bcm1480_int.h> 29#include <asm/sibyte/bcm1480_int.h>
@@ -67,28 +68,114 @@ void __cpuinit bcm1480_smp_init(void)
67 change_c0_status(ST0_IM, imask); 68 change_c0_status(ST0_IM, imask);
68} 69}
69 70
70void __cpuinit bcm1480_smp_finish(void) 71/*
72 * These are routines for dealing with the sb1250 smp capabilities
73 * independent of board/firmware
74 */
75
76/*
77 * Simple enough; everything is set up, so just poke the appropriate mailbox
78 * register, and we should be set
79 */
80static void bcm1480_send_ipi_single(int cpu, unsigned int action)
81{
82 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
83}
84
85static void bcm1480_send_ipi_mask(cpumask_t mask, unsigned int action)
86{
87 unsigned int i;
88
89 for_each_cpu_mask(i, mask)
90 bcm1480_send_ipi_single(i, action);
91}
92
93/*
94 * Code to run on secondary just after probing the CPU
95 */
96static void __cpuinit bcm1480_init_secondary(void)
97{
98 extern void bcm1480_smp_init(void);
99
100 bcm1480_smp_init();
101}
102
103/*
104 * Do any tidying up before marking online and running the idle
105 * loop
106 */
107static void __cpuinit bcm1480_smp_finish(void)
71{ 108{
72 extern void sb1480_clockevent_init(void); 109 extern void sb1480_clockevent_init(void);
73 110
74 sb1480_clockevent_init(); 111 sb1480_clockevent_init();
75 local_irq_enable(); 112 local_irq_enable();
113 bcm1480_smp_finish();
76} 114}
77 115
78/* 116/*
79 * These are routines for dealing with the sb1250 smp capabilities 117 * Final cleanup after all secondaries booted
80 * independent of board/firmware
81 */ 118 */
119static void bcm1480_cpus_done(void)
120{
121}
82 122
83/* 123/*
84 * Simple enough; everything is set up, so just poke the appropriate mailbox 124 * Setup the PC, SP, and GP of a secondary processor and start it
85 * register, and we should be set 125 * running!
86 */ 126 */
87void core_send_ipi(int cpu, unsigned int action) 127static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle)
88{ 128{
89 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); 129 int retval;
130
131 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
132 __KSTK_TOS(idle),
133 (unsigned long)task_thread_info(idle), 0);
134 if (retval != 0)
135 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
90} 136}
91 137
138/*
139 * Use CFE to find out how many CPUs are available, setting up
140 * phys_cpu_present_map and the logical/physical mappings.
141 * XXXKW will the boot CPU ever not be physical 0?
142 *
143 * Common setup before any secondaries are started
144 */
145static void __init bcm1480_smp_setup(void)
146{
147 int i, num;
148
149 cpus_clear(phys_cpu_present_map);
150 cpu_set(0, phys_cpu_present_map);
151 __cpu_number_map[0] = 0;
152 __cpu_logical_map[0] = 0;
153
154 for (i = 1, num = 0; i < NR_CPUS; i++) {
155 if (cfe_cpu_stop(i) == 0) {
156 cpu_set(i, phys_cpu_present_map);
157 __cpu_number_map[i] = ++num;
158 __cpu_logical_map[num] = i;
159 }
160 }
161 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
162}
163
164static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
165{
166}
167
168struct plat_smp_ops bcm1480_smp_ops = {
169 .send_ipi_single = bcm1480_send_ipi_single,
170 .send_ipi_mask = bcm1480_send_ipi_mask,
171 .init_secondary = bcm1480_init_secondary,
172 .smp_finish = bcm1480_smp_finish,
173 .cpus_done = bcm1480_cpus_done,
174 .boot_secondary = bcm1480_boot_secondary,
175 .smp_setup = bcm1480_smp_setup,
176 .prepare_cpus = bcm1480_prepare_cpus,
177};
178
92void bcm1480_mailbox_interrupt(void) 179void bcm1480_mailbox_interrupt(void)
93{ 180{
94 int cpu = smp_processor_id(); 181 int cpu = smp_processor_id();
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
index a1214937b705..02b32e142adf 100644
--- a/arch/mips/sibyte/cfe/Makefile
+++ b/arch/mips/sibyte/cfe/Makefile
@@ -1,3 +1,2 @@
1lib-y = setup.o 1lib-y = setup.o
2lib-$(CONFIG_SMP) += smp.o
3lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o 2lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index dbd6e6fdd3f9..33fce826f8bf 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -28,6 +28,7 @@
28#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
29#include <asm/reboot.h> 29#include <asm/reboot.h>
30#include <asm/sibyte/board.h> 30#include <asm/sibyte/board.h>
31#include <asm/smp-ops.h>
31 32
32#include <asm/fw/cfe/cfe_api.h> 33#include <asm/fw/cfe/cfe_api.h>
33#include <asm/fw/cfe/cfe_error.h> 34#include <asm/fw/cfe/cfe_error.h>
@@ -232,6 +233,9 @@ static int __init initrd_setup(char *str)
232 233
233#endif 234#endif
234 235
236extern struct plat_smp_ops sb_smp_ops;
237extern struct plat_smp_ops bcm1480_smp_ops;
238
235/* 239/*
236 * prom_init is called just after the cpu type is determined, from setup_arch() 240 * prom_init is called just after the cpu type is determined, from setup_arch()
237 */ 241 */
@@ -297,9 +301,6 @@ void __init prom_init(void)
297 * command line 301 * command line
298 */ 302 */
299 strcpy(arcs_cmdline, "root=/dev/ram0 "); 303 strcpy(arcs_cmdline, "root=/dev/ram0 ");
300#ifdef CONFIG_SIBYTE_PTSWARM
301 strcat(arcs_cmdline, "console=ttyS0,115200 ");
302#endif
303 } else { 304 } else {
304 /* The loader should have set the command line */ 305 /* The loader should have set the command line */
305 /* too early for panic to do any good */ 306 /* too early for panic to do any good */
@@ -340,6 +341,13 @@ void __init prom_init(void)
340 arcs_cmdline[CL_SIZE-1] = 0; 341 arcs_cmdline[CL_SIZE-1] = 0;
341 342
342 prom_meminit(); 343 prom_meminit();
344
345#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
346 register_smp_ops(&sb_smp_ops);
347#endif
348#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
349 register_smp_ops(&bcm1480_smp_ops);
350#endif
343} 351}
344 352
345void __init prom_free_prom_memory(void) 353void __init prom_free_prom_memory(void)
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
deleted file mode 100644
index 534a62912f21..000000000000
--- a/arch/mips/sibyte/cfe/smp.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/smp.h>
22#include <asm/processor.h>
23
24#include <asm/fw/cfe/cfe_api.h>
25#include <asm/fw/cfe/cfe_error.h>
26
27/*
28 * Use CFE to find out how many CPUs are available, setting up
29 * phys_cpu_present_map and the logical/physical mappings.
30 * XXXKW will the boot CPU ever not be physical 0?
31 *
32 * Common setup before any secondaries are started
33 */
34void __init plat_smp_setup(void)
35{
36 int i, num;
37
38 cpus_clear(phys_cpu_present_map);
39 cpu_set(0, phys_cpu_present_map);
40 __cpu_number_map[0] = 0;
41 __cpu_logical_map[0] = 0;
42
43 for (i = 1, num = 0; i < NR_CPUS; i++) {
44 if (cfe_cpu_stop(i) == 0) {
45 cpu_set(i, phys_cpu_present_map);
46 __cpu_number_map[i] = ++num;
47 __cpu_logical_map[num] = i;
48 }
49 }
50 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
51}
52
53void __init plat_prepare_cpus(unsigned int max_cpus)
54{
55}
56
57/*
58 * Setup the PC, SP, and GP of a secondary processor and start it
59 * running!
60 */
61void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
62{
63 int retval;
64
65 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
66 __KSTK_TOS(idle),
67 (unsigned long)task_thread_info(idle), 0);
68 if (retval != 0)
69 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
70}
71
72/*
73 * Code to run on secondary just after probing the CPU
74 */
75void __cpuinit prom_init_secondary(void)
76{
77#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
78 extern void bcm1480_smp_init(void);
79 bcm1480_smp_init();
80#elif defined(CONFIG_SIBYTE_SB1250)
81 extern void sb1250_smp_init(void);
82 sb1250_smp_init();
83#else
84#error invalid SMP configuration
85#endif
86}
87
88/*
89 * Do any tidying up before marking online and running the idle
90 * loop
91 */
92void __cpuinit prom_smp_finish(void)
93{
94#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
95 extern void bcm1480_smp_finish(void);
96 bcm1480_smp_finish();
97#elif defined(CONFIG_SIBYTE_SB1250)
98 extern void sb1250_smp_finish(void);
99 sb1250_smp_finish();
100#else
101#error invalid SMP configuration
102#endif
103}
104
105/*
106 * Final cleanup after all secondaries booted
107 */
108void prom_cpus_done(void)
109{
110}
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index 3f52c95a4eb8..0734b933e969 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -24,6 +24,7 @@
24 24
25#include <asm/mmu_context.h> 25#include <asm/mmu_context.h>
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/fw/cfe/cfe_api.h>
27#include <asm/sibyte/sb1250.h> 28#include <asm/sibyte/sb1250.h>
28#include <asm/sibyte/sb1250_regs.h> 29#include <asm/sibyte/sb1250_regs.h>
29#include <asm/sibyte/sb1250_int.h> 30#include <asm/sibyte/sb1250_int.h>
@@ -55,7 +56,43 @@ void __cpuinit sb1250_smp_init(void)
55 change_c0_status(ST0_IM, imask); 56 change_c0_status(ST0_IM, imask);
56} 57}
57 58
58void __cpuinit sb1250_smp_finish(void) 59/*
60 * These are routines for dealing with the sb1250 smp capabilities
61 * independent of board/firmware
62 */
63
64/*
65 * Simple enough; everything is set up, so just poke the appropriate mailbox
66 * register, and we should be set
67 */
68static void sb1250_send_ipi_single(int cpu, unsigned int action)
69{
70 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
71}
72
73static inline void sb1250_send_ipi_mask(cpumask_t mask, unsigned int action)
74{
75 unsigned int i;
76
77 for_each_cpu_mask(i, mask)
78 sb1250_send_ipi_single(i, action);
79}
80
81/*
82 * Code to run on secondary just after probing the CPU
83 */
84static void __cpuinit sb1250_init_secondary(void)
85{
86 extern void sb1250_smp_init(void);
87
88 sb1250_smp_init();
89}
90
91/*
92 * Do any tidying up before marking online and running the idle
93 * loop
94 */
95static void __cpuinit sb1250_smp_finish(void)
59{ 96{
60 extern void sb1250_clockevent_init(void); 97 extern void sb1250_clockevent_init(void);
61 98
@@ -64,19 +101,68 @@ void __cpuinit sb1250_smp_finish(void)
64} 101}
65 102
66/* 103/*
67 * These are routines for dealing with the sb1250 smp capabilities 104 * Final cleanup after all secondaries booted
68 * independent of board/firmware
69 */ 105 */
106static void sb1250_cpus_done(void)
107{
108}
70 109
71/* 110/*
72 * Simple enough; everything is set up, so just poke the appropriate mailbox 111 * Setup the PC, SP, and GP of a secondary processor and start it
73 * register, and we should be set 112 * running!
74 */ 113 */
75void core_send_ipi(int cpu, unsigned int action) 114static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle)
76{ 115{
77 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); 116 int retval;
117
118 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
119 __KSTK_TOS(idle),
120 (unsigned long)task_thread_info(idle), 0);
121 if (retval != 0)
122 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
78} 123}
79 124
125/*
126 * Use CFE to find out how many CPUs are available, setting up
127 * phys_cpu_present_map and the logical/physical mappings.
128 * XXXKW will the boot CPU ever not be physical 0?
129 *
130 * Common setup before any secondaries are started
131 */
132static void __init sb1250_smp_setup(void)
133{
134 int i, num;
135
136 cpus_clear(phys_cpu_present_map);
137 cpu_set(0, phys_cpu_present_map);
138 __cpu_number_map[0] = 0;
139 __cpu_logical_map[0] = 0;
140
141 for (i = 1, num = 0; i < NR_CPUS; i++) {
142 if (cfe_cpu_stop(i) == 0) {
143 cpu_set(i, phys_cpu_present_map);
144 __cpu_number_map[i] = ++num;
145 __cpu_logical_map[num] = i;
146 }
147 }
148 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
149}
150
151static void __init sb1250_prepare_cpus(unsigned int max_cpus)
152{
153}
154
155struct plat_smp_ops sb_smp_ops = {
156 .send_ipi_single = sb1250_send_ipi_single,
157 .send_ipi_mask = sb1250_send_ipi_mask,
158 .init_secondary = sb1250_init_secondary,
159 .smp_finish = sb1250_smp_finish,
160 .cpus_done = sb1250_cpus_done,
161 .boot_secondary = sb1250_boot_secondary,
162 .smp_setup = sb1250_smp_setup,
163 .prepare_cpus = sb1250_prepare_cpus,
164};
165
80void sb1250_mailbox_interrupt(void) 166void sb1250_mailbox_interrupt(void)
81{ 167{
82 int cpu = smp_processor_id(); 168 int cpu = smp_processor_id();
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index 3a99cd62c0bd..a7dbeebe7fe6 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -3,6 +3,6 @@
3# 3#
4 4
5obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o 5obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
6obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o 6obj-$(CONFIG_EISA) += eisa.o
7 7
8EXTRA_CFLAGS += -Werror 8EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index b74607599971..3f8cf5eb2f06 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -117,10 +117,19 @@ static struct resource sc26xx_rsrc[] = {
117 } 117 }
118}; 118};
119 119
120static unsigned int sc26xx_data[2] = {
121 /* DTR | RTS | DSR | CTS | DCD | RI */
122 (8 << 0) | (4 << 4) | (6 << 8) | (0 << 12) | (6 << 16) | (0 << 20),
123 (3 << 0) | (2 << 4) | (1 << 8) | (2 << 12) | (3 << 16) | (4 << 20)
124};
125
120static struct platform_device sc26xx_pdev = { 126static struct platform_device sc26xx_pdev = {
121 .name = "SC26xx", 127 .name = "SC26xx",
122 .num_resources = ARRAY_SIZE(sc26xx_rsrc), 128 .num_resources = ARRAY_SIZE(sc26xx_rsrc),
123 .resource = sc26xx_rsrc 129 .resource = sc26xx_rsrc,
130 .dev = {
131 .platform_data = sc26xx_data,
132 }
124}; 133};
125 134
126static u32 a20r_ack_hwint(void) 135static u32 a20r_ack_hwint(void)
@@ -231,9 +240,9 @@ static int __init snirm_a20r_setup_devinit(void)
231 platform_device_register(&sc26xx_pdev); 240 platform_device_register(&sc26xx_pdev);
232 platform_device_register(&a20r_serial8250_device); 241 platform_device_register(&a20r_serial8250_device);
233 platform_device_register(&a20r_ds1216_device); 242 platform_device_register(&a20r_ds1216_device);
243 sni_eisa_root_init();
234 break; 244 break;
235 } 245 }
236
237 return 0; 246 return 0;
238} 247}
239 248
diff --git a/arch/mips/sni/eisa.c b/arch/mips/sni/eisa.c
new file mode 100644
index 000000000000..7396cd719900
--- /dev/null
+++ b/arch/mips/sni/eisa.c
@@ -0,0 +1,50 @@
1/*
2 * Virtual EISA root driver.
3 * Acts as a placeholder if we don't have a proper EISA bridge.
4 *
5 * (C) 2003 Marc Zyngier <maz@wild-wind.fr.eu.org>
6 * modified for SNI usage by Thomas Bogendoerfer
7 *
8 * This code is released under the GPL version 2.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/eisa.h>
14#include <linux/init.h>
15
16/* The default EISA device parent (virtual root device).
17 * Now use a platform device, since that's the obvious choice. */
18
19static struct platform_device eisa_root_dev = {
20 .name = "eisa",
21 .id = 0,
22};
23
24static struct eisa_root_device eisa_bus_root = {
25 .dev = &eisa_root_dev.dev,
26 .bus_base_addr = 0,
27 .res = &ioport_resource,
28 .slots = EISA_MAX_SLOTS,
29 .dma_mask = 0xffffffff,
30 .force_probe = 1,
31};
32
33int __init sni_eisa_root_init(void)
34{
35 int r;
36
37 r = platform_device_register(&eisa_root_dev);
38 if (!r)
39 return r;
40
41 eisa_root_dev.dev.driver_data = &eisa_bus_root;
42
43 if (eisa_root_register(&eisa_bus_root)) {
44 /* A real bridge may have been registered before
45 * us. So quietly unregister. */
46 platform_device_unregister(&eisa_root_dev);
47 return -1;
48 }
49 return 0;
50}
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 9ccffdfb8289..e8e72bb3a9af 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -35,14 +35,14 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
35 if (unlikely(irq < 0)) 35 if (unlikely(irq < 0))
36 return IRQ_NONE; 36 return IRQ_NONE;
37 37
38 do_IRQ(irq); 38 generic_handle_irq(irq);
39 return IRQ_HANDLED; 39 return IRQ_HANDLED;
40} 40}
41 41
42struct irqaction sni_isa_irq = { 42struct irqaction sni_isa_irq = {
43 .handler = sni_isa_irq_handler, 43 .handler = sni_isa_irq_handler,
44 .name = "ISA", 44 .name = "ISA",
45 .flags = IRQF_SHARED 45 .flags = IRQF_SHARED | IRQF_DISABLED
46}; 46};
47 47
48/* 48/*
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 416f397c768b..e5f12cf96e8e 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -76,6 +76,11 @@ static struct platform_device pcit_cmos_device = {
76 .resource = pcit_cmos_rsrc 76 .resource = pcit_cmos_rsrc
77}; 77};
78 78
79static struct platform_device pcit_pcspeaker_pdev = {
80 .name = "pcspkr",
81 .id = -1,
82};
83
79static struct resource sni_io_resource = { 84static struct resource sni_io_resource = {
80 .start = 0x00000000UL, 85 .start = 0x00000000UL,
81 .end = 0x03bfffffUL, 86 .end = 0x03bfffffUL,
@@ -277,11 +282,13 @@ static int __init snirm_pcit_setup_devinit(void)
277 case SNI_BRD_PCI_TOWER: 282 case SNI_BRD_PCI_TOWER:
278 platform_device_register(&pcit_serial8250_device); 283 platform_device_register(&pcit_serial8250_device);
279 platform_device_register(&pcit_cmos_device); 284 platform_device_register(&pcit_cmos_device);
285 platform_device_register(&pcit_pcspeaker_pdev);
280 break; 286 break;
281 287
282 case SNI_BRD_PCI_TOWER_CPLUS: 288 case SNI_BRD_PCI_TOWER_CPLUS:
283 platform_device_register(&pcit_cplus_serial8250_device); 289 platform_device_register(&pcit_cplus_serial8250_device);
284 platform_device_register(&pcit_cmos_device); 290 platform_device_register(&pcit_cmos_device);
291 platform_device_register(&pcit_pcspeaker_pdev);
285 break; 292 break;
286 } 293 }
287 return 0; 294 return 0;
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 67b061eef6cd..5310aa75afa4 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -5,30 +5,36 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) 8 * Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
9 *
10 * i8259 parts ripped out of arch/mips/kernel/i8259.c
9 */ 11 */
10 12
13#include <linux/delay.h>
11#include <linux/init.h> 14#include <linux/init.h>
12#include <linux/interrupt.h> 15#include <linux/interrupt.h>
13#include <linux/platform_device.h> 16#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
18#include <linux/io.h>
15 19
16#include <asm/sni.h> 20#include <asm/sni.h>
17#include <asm/time.h> 21#include <asm/time.h>
18#include <asm/irq_cpu.h> 22#include <asm/irq_cpu.h>
19 23
20#define PORT(_base,_irq) \ 24#define RM200_I8259A_IRQ_BASE 32
25
26#define MEMPORT(_base,_irq) \
21 { \ 27 { \
22 .iobase = _base, \ 28 .mapbase = _base, \
23 .irq = _irq, \ 29 .irq = _irq, \
24 .uartclk = 1843200, \ 30 .uartclk = 1843200, \
25 .iotype = UPIO_PORT, \ 31 .iotype = UPIO_MEM, \
26 .flags = UPF_BOOT_AUTOCONF, \ 32 .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \
27 } 33 }
28 34
29static struct plat_serial8250_port rm200_data[] = { 35static struct plat_serial8250_port rm200_data[] = {
30 PORT(0x3f8, 4), 36 MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
31 PORT(0x2f8, 3), 37 MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
32 { }, 38 { },
33}; 39};
34 40
@@ -112,15 +118,311 @@ static int __init snirm_setup_devinit(void)
112 platform_device_register(&rm200_ds1216_device); 118 platform_device_register(&rm200_ds1216_device);
113 platform_device_register(&snirm_82596_rm200_pdev); 119 platform_device_register(&snirm_82596_rm200_pdev);
114 platform_device_register(&snirm_53c710_rm200_pdev); 120 platform_device_register(&snirm_53c710_rm200_pdev);
121 sni_eisa_root_init();
115 } 122 }
116 return 0; 123 return 0;
117} 124}
118 125
119device_initcall(snirm_setup_devinit); 126device_initcall(snirm_setup_devinit);
120 127
128/*
129 * RM200 has an ISA and an EISA bus. The iSA bus is only used
130 * for onboard devices and also has twi i8259 PICs. Since these
131 * PICs are no accessible via inb/outb the following code uses
132 * readb/writeb to access them
133 */
134
135DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
136#define PIC_CMD 0x00
137#define PIC_IMR 0x01
138#define PIC_ISR PIC_CMD
139#define PIC_POLL PIC_ISR
140#define PIC_OCW3 PIC_ISR
141
142/* i8259A PIC related value */
143#define PIC_CASCADE_IR 2
144#define MASTER_ICW4_DEFAULT 0x01
145#define SLAVE_ICW4_DEFAULT 0x01
146
147/*
148 * This contains the irq mask for both 8259A irq controllers,
149 */
150static unsigned int rm200_cached_irq_mask = 0xffff;
151static __iomem u8 *rm200_pic_master;
152static __iomem u8 *rm200_pic_slave;
153
154#define cached_master_mask (rm200_cached_irq_mask)
155#define cached_slave_mask (rm200_cached_irq_mask >> 8)
156
157static void sni_rm200_disable_8259A_irq(unsigned int irq)
158{
159 unsigned int mask;
160 unsigned long flags;
161
162 irq -= RM200_I8259A_IRQ_BASE;
163 mask = 1 << irq;
164 spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
165 rm200_cached_irq_mask |= mask;
166 if (irq & 8)
167 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
168 else
169 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
170 spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
171}
172
173static void sni_rm200_enable_8259A_irq(unsigned int irq)
174{
175 unsigned int mask;
176 unsigned long flags;
177
178 irq -= RM200_I8259A_IRQ_BASE;
179 mask = ~(1 << irq);
180 spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
181 rm200_cached_irq_mask &= mask;
182 if (irq & 8)
183 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
184 else
185 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
186 spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
187}
188
189static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
190{
191 int value;
192 int irqmask = 1 << irq;
193
194 if (irq < 8) {
195 writeb(0x0B, rm200_pic_master + PIC_CMD);
196 value = readb(rm200_pic_master + PIC_CMD) & irqmask;
197 writeb(0x0A, rm200_pic_master + PIC_CMD);
198 return value;
199 }
200 writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */
201 value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8);
202 writeb(0x0A, rm200_pic_slave + PIC_CMD);
203 return value;
204}
205
206/*
207 * Careful! The 8259A is a fragile beast, it pretty
208 * much _has_ to be done exactly like this (mask it
209 * first, _then_ send the EOI, and the order of EOI
210 * to the two 8259s is important!
211 */
212void sni_rm200_mask_and_ack_8259A(unsigned int irq)
213{
214 unsigned int irqmask;
215 unsigned long flags;
216
217 irq -= RM200_I8259A_IRQ_BASE;
218 irqmask = 1 << irq;
219 spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
220 /*
221 * Lightweight spurious IRQ detection. We do not want
222 * to overdo spurious IRQ handling - it's usually a sign
223 * of hardware problems, so we only do the checks we can
224 * do without slowing down good hardware unnecessarily.
225 *
226 * Note that IRQ7 and IRQ15 (the two spurious IRQs
227 * usually resulting from the 8259A-1|2 PICs) occur
228 * even if the IRQ is masked in the 8259A. Thus we
229 * can check spurious 8259A IRQs without doing the
230 * quite slow i8259A_irq_real() call for every IRQ.
231 * This does not cover 100% of spurious interrupts,
232 * but should be enough to warn the user that there
233 * is something bad going on ...
234 */
235 if (rm200_cached_irq_mask & irqmask)
236 goto spurious_8259A_irq;
237 rm200_cached_irq_mask |= irqmask;
238
239handle_real_irq:
240 if (irq & 8) {
241 readb(rm200_pic_slave + PIC_IMR);
242 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
243 writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD);
244 writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD);
245 } else {
246 readb(rm200_pic_master + PIC_IMR);
247 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
248 writeb(0x60+irq, rm200_pic_master + PIC_CMD);
249 }
250 spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
251 return;
252
253spurious_8259A_irq:
254 /*
255 * this is the slow path - should happen rarely.
256 */
257 if (sni_rm200_i8259A_irq_real(irq))
258 /*
259 * oops, the IRQ _is_ in service according to the
260 * 8259A - not spurious, go handle it.
261 */
262 goto handle_real_irq;
263
264 {
265 static int spurious_irq_mask;
266 /*
267 * At this point we can be sure the IRQ is spurious,
268 * lets ACK and report it. [once per IRQ]
269 */
270 if (!(spurious_irq_mask & irqmask)) {
271 printk(KERN_DEBUG
272 "spurious RM200 8259A interrupt: IRQ%d.\n", irq);
273 spurious_irq_mask |= irqmask;
274 }
275 atomic_inc(&irq_err_count);
276 /*
277 * Theoretically we do not have to handle this IRQ,
278 * but in Linux this does not cause problems and is
279 * simpler for us.
280 */
281 goto handle_real_irq;
282 }
283}
284
285static struct irq_chip sni_rm200_i8259A_chip = {
286 .name = "RM200-XT-PIC",
287 .mask = sni_rm200_disable_8259A_irq,
288 .unmask = sni_rm200_enable_8259A_irq,
289 .mask_ack = sni_rm200_mask_and_ack_8259A,
290};
291
292/*
293 * Do the traditional i8259 interrupt polling thing. This is for the few
294 * cases where no better interrupt acknowledge method is available and we
295 * absolutely must touch the i8259.
296 */
297static inline int sni_rm200_i8259_irq(void)
298{
299 int irq;
300
301 spin_lock(&sni_rm200_i8259A_lock);
302
303 /* Perform an interrupt acknowledge cycle on controller 1. */
304 writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
305 irq = readb(rm200_pic_master + PIC_CMD) & 7;
306 if (irq == PIC_CASCADE_IR) {
307 /*
308 * Interrupt is cascaded so perform interrupt
309 * acknowledge on controller 2.
310 */
311 writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */
312 irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8;
313 }
314
315 if (unlikely(irq == 7)) {
316 /*
317 * This may be a spurious interrupt.
318 *
319 * Read the interrupt status register (ISR). If the most
320 * significant bit is not set then there is no valid
321 * interrupt.
322 */
323 writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */
324 if (~readb(rm200_pic_master + PIC_ISR) & 0x80)
325 irq = -1;
326 }
327
328 spin_unlock(&sni_rm200_i8259A_lock);
329
330 return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;
331}
332
333void sni_rm200_init_8259A(void)
334{
335 unsigned long flags;
336
337 spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
338
339 writeb(0xff, rm200_pic_master + PIC_IMR);
340 writeb(0xff, rm200_pic_slave + PIC_IMR);
341
342 writeb(0x11, rm200_pic_master + PIC_CMD);
343 writeb(0, rm200_pic_master + PIC_IMR);
344 writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);
345 writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);
346 writeb(0x11, rm200_pic_slave + PIC_CMD);
347 writeb(8, rm200_pic_slave + PIC_IMR);
348 writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);
349 writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);
350 udelay(100); /* wait for 8259A to initialize */
351
352 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
353 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
354
355 spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
356}
357
358/*
359 * IRQ2 is cascade interrupt to second interrupt controller
360 */
361static struct irqaction sni_rm200_irq2 = {
362 no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
363};
364
365static struct resource sni_rm200_pic1_resource = {
366 .name = "onboard ISA pic1",
367 .start = 0x16000020,
368 .end = 0x16000023,
369 .flags = IORESOURCE_BUSY
370};
371
372static struct resource sni_rm200_pic2_resource = {
373 .name = "onboard ISA pic2",
374 .start = 0x160000a0,
375 .end = 0x160000a3,
376 .flags = IORESOURCE_BUSY
377};
378
379/* ISA irq handler */
380static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p)
381{
382 int irq;
383
384 irq = sni_rm200_i8259_irq();
385 if (unlikely(irq < 0))
386 return IRQ_NONE;
387
388 do_IRQ(irq);
389 return IRQ_HANDLED;
390}
391
392struct irqaction sni_rm200_i8259A_irq = {
393 .handler = sni_rm200_i8259A_irq_handler,
394 .name = "onboard ISA",
395 .flags = IRQF_SHARED
396};
397
398void __init sni_rm200_i8259_irqs(void)
399{
400 int i;
401
402 rm200_pic_master = ioremap_nocache(0x16000020, 4);
403 if (!rm200_pic_master)
404 return;
405 rm200_pic_slave = ioremap_nocache(0x160000a0, 4);
406 if (!rm200_pic_master) {
407 iounmap(rm200_pic_master);
408 return;
409 }
410
411 insert_resource(&iomem_resource, &sni_rm200_pic1_resource);
412 insert_resource(&iomem_resource, &sni_rm200_pic2_resource);
413
414 sni_rm200_init_8259A();
415
416 for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
417 set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip,
418 handle_level_irq);
419
420 setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
421}
422
121 423
122#define SNI_RM200_INT_STAT_REG 0xbc000000 424#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)
123#define SNI_RM200_INT_ENA_REG 0xbc080000 425#define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000)
124 426
125#define SNI_RM200_INT_START 24 427#define SNI_RM200_INT_START 24
126#define SNI_RM200_INT_END 28 428#define SNI_RM200_INT_END 28
@@ -181,17 +483,17 @@ void __init sni_rm200_irq_init(void)
181 483
182 * (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f; 484 * (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f;
183 485
486 sni_rm200_i8259_irqs();
184 mips_cpu_irq_init(); 487 mips_cpu_irq_init();
185 /* Actually we've got more interrupts to handle ... */ 488 /* Actually we've got more interrupts to handle ... */
186 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) 489 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
187 set_irq_chip(i, &rm200_irq_type); 490 set_irq_chip(i, &rm200_irq_type);
188 sni_hwint = sni_rm200_hwint; 491 sni_hwint = sni_rm200_hwint;
189 change_c0_status(ST0_IM, IE_IRQ0); 492 change_c0_status(ST0_IM, IE_IRQ0);
190 setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq); 493 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
494 setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq);
191} 495}
192 496
193void __init sni_rm200_init(void) 497void __init sni_rm200_init(void)
194{ 498{
195 set_io_port_base(SNI_PORT_BASE + 0x02000000);
196 ioport_resource.end += 0x02000000;
197} 499}
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index e8b26bdee24c..5484e1c62054 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -19,11 +19,17 @@
19#include <asm/sgialib.h> 19#include <asm/sgialib.h>
20#endif 20#endif
21 21
22#ifdef CONFIG_SNIPROM
23#include <asm/mipsprom.h>
24#endif
25
26#include <asm/bootinfo.h>
22#include <asm/io.h> 27#include <asm/io.h>
23#include <asm/reboot.h> 28#include <asm/reboot.h>
24#include <asm/sni.h> 29#include <asm/sni.h>
25 30
26unsigned int sni_brd_type; 31unsigned int sni_brd_type;
32EXPORT_SYMBOL(sni_brd_type);
27 33
28extern void sni_machine_restart(char *command); 34extern void sni_machine_restart(char *command);
29extern void sni_machine_power_off(void); 35extern void sni_machine_power_off(void);
@@ -47,20 +53,152 @@ static void __init sni_display_setup(void)
47#endif 53#endif
48} 54}
49 55
56static void __init sni_console_setup(void)
57{
58#ifndef CONFIG_ARC
59 char *ctype;
60 char *cdev;
61 char *baud;
62 int port;
63 static char options[8];
64
65 cdev = prom_getenv("console_dev");
66 if (strncmp(cdev, "tty", 3) == 0) {
67 ctype = prom_getenv("console");
68 switch (*ctype) {
69 default:
70 case 'l':
71 port = 0;
72 baud = prom_getenv("lbaud");
73 break;
74 case 'r':
75 port = 1;
76 baud = prom_getenv("rbaud");
77 break;
78 }
79 if (baud)
80 strcpy(options, baud);
81 if (strncmp(cdev, "tty552", 6) == 0)
82 add_preferred_console("ttyS", port,
83 baud ? options : NULL);
84 else
85 add_preferred_console("ttySC", port,
86 baud ? options : NULL);
87 }
88#endif
89}
90
91#ifdef DEBUG
92static void __init sni_idprom_dump(void)
93{
94 int i;
95
96 pr_debug("SNI IDProm dump:\n");
97 for (i = 0; i < 256; i++) {
98 if (i%16 == 0)
99 pr_debug("%04x ", i);
100
101 printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i));
102
103 if (i % 16 == 15)
104 printk("\n");
105 }
106}
107#endif
50 108
51void __init plat_mem_setup(void) 109void __init plat_mem_setup(void)
52{ 110{
111 int cputype;
112
53 set_io_port_base(SNI_PORT_BASE); 113 set_io_port_base(SNI_PORT_BASE);
54// ioport_resource.end = sni_io_resource.end; 114// ioport_resource.end = sni_io_resource.end;
55 115
56 /* 116 /*
57 * Setup (E)ISA I/O memory access stuff 117 * Setup (E)ISA I/O memory access stuff
58 */ 118 */
59 isa_slot_offset = 0xb0000000; 119 isa_slot_offset = CKSEG1ADDR(0xb0000000);
60#ifdef CONFIG_EISA 120#ifdef CONFIG_EISA
61 EISA_bus = 1; 121 EISA_bus = 1;
62#endif 122#endif
63 123
124 sni_brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
125 cputype = *(unsigned char *)SNI_IDPROM_CPUTYPE;
126 switch (sni_brd_type) {
127 case SNI_BRD_TOWER_OASIC:
128 switch (cputype) {
129 case SNI_CPU_M8030:
130 system_type = "RM400-330";
131 break;
132 case SNI_CPU_M8031:
133 system_type = "RM400-430";
134 break;
135 case SNI_CPU_M8037:
136 system_type = "RM400-530";
137 break;
138 case SNI_CPU_M8034:
139 system_type = "RM400-730";
140 break;
141 default:
142 system_type = "RM400-xxx";
143 break;
144 }
145 break;
146 case SNI_BRD_MINITOWER:
147 switch (cputype) {
148 case SNI_CPU_M8021:
149 case SNI_CPU_M8043:
150 system_type = "RM400-120";
151 break;
152 case SNI_CPU_M8040:
153 system_type = "RM400-220";
154 break;
155 case SNI_CPU_M8053:
156 system_type = "RM400-225";
157 break;
158 case SNI_CPU_M8050:
159 system_type = "RM400-420";
160 break;
161 default:
162 system_type = "RM400-xxx";
163 break;
164 }
165 break;
166 case SNI_BRD_PCI_TOWER:
167 system_type = "RM400-Cxx";
168 break;
169 case SNI_BRD_RM200:
170 system_type = "RM200-xxx";
171 break;
172 case SNI_BRD_PCI_MTOWER:
173 system_type = "RM300-Cxx";
174 break;
175 case SNI_BRD_PCI_DESKTOP:
176 switch (read_c0_prid() & 0xff00) {
177 case PRID_IMP_R4600:
178 case PRID_IMP_R4700:
179 system_type = "RM200-C20";
180 break;
181 case PRID_IMP_R5000:
182 system_type = "RM200-C40";
183 break;
184 default:
185 system_type = "RM200-Cxx";
186 break;
187 }
188 break;
189 case SNI_BRD_PCI_TOWER_CPLUS:
190 system_type = "RM400-Exx";
191 break;
192 case SNI_BRD_PCI_MTOWER_CPLUS:
193 system_type = "RM300-Exx";
194 break;
195 }
196 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, system_type);
197
198#ifdef DEBUG
199 sni_idprom_dump();
200#endif
201
64 switch (sni_brd_type) { 202 switch (sni_brd_type) {
65 case SNI_BRD_10: 203 case SNI_BRD_10:
66 case SNI_BRD_10NEW: 204 case SNI_BRD_10NEW:
@@ -89,9 +227,10 @@ void __init plat_mem_setup(void)
89 pm_power_off = sni_machine_power_off; 227 pm_power_off = sni_machine_power_off;
90 228
91 sni_display_setup(); 229 sni_display_setup();
230 sni_console_setup();
92} 231}
93 232
94#if CONFIG_PCI 233#ifdef CONFIG_PCI
95 234
96#include <linux/pci.h> 235#include <linux/pci.h>
97#include <video/vga.h> 236#include <video/vga.h>
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
deleted file mode 100644
index eff4b89d7b75..000000000000
--- a/arch/mips/sni/sniprom.c
+++ /dev/null
@@ -1,251 +0,0 @@
1/*
2 * Big Endian PROM code for SNI RM machines
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org)
9 * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
10 */
11
12#define DEBUG
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/string.h>
17#include <linux/console.h>
18
19#include <asm/addrspace.h>
20#include <asm/sni.h>
21#include <asm/mipsprom.h>
22#include <asm/mipsregs.h>
23#include <asm/bootinfo.h>
24
25/* special SNI prom calls */
26/*
27 * This does not exist in all proms - SINIX compares
28 * the prom env variable "version" against "2.0008"
29 * or greater. If lesser it tries to probe interesting
30 * registers
31 */
32#define PROM_GET_MEMCONF 58
33
34#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
35#define PROM_ENTRY(x) (PROM_VEC + (x))
36
37
38static int *(*__prom_putchar)(int) = (int *(*)(int))PROM_ENTRY(PROM_PUTCHAR);
39
40void prom_putchar(char c)
41{
42 __prom_putchar(c);
43}
44
45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
47
48char *prom_getenv(char *s)
49{
50 return __prom_getenv(s);
51}
52
53void __init prom_free_prom_memory(void)
54{
55}
56
57/*
58 * /proc/cpuinfo system type
59 *
60 */
61static const char *systype = "Unknown";
62const char *get_system_type(void)
63{
64 return systype;
65}
66
67#define SNI_IDPROM_BASE 0xbff00000
68#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE+0x28) /* Memsize in 16MB quantities */
69#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE+0x29) /* Board Type */
70#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE+0x30) /* CPU Type */
71
72#define SNI_IDPROM_SIZE 0x1000
73
74#ifdef DEBUG
75static void __init sni_idprom_dump(void)
76{
77 int i;
78
79 pr_debug("SNI IDProm dump:\n");
80 for (i = 0; i < 256; i++) {
81 if (i%16 == 0)
82 pr_debug("%04x ", i);
83
84 printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i));
85
86 if (i % 16 == 15)
87 printk("\n");
88 }
89}
90#endif
91
92static void __init sni_mem_init(void )
93{
94 int i, memsize;
95 struct membank {
96 u32 size;
97 u32 base;
98 u32 size2;
99 u32 pad1;
100 u32 pad2;
101 } memconf[8];
102
103 /* MemSIZE from prom in 16MByte chunks */
104 memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16;
105
106 pr_debug("IDProm memsize: %lu MByte\n", memsize);
107
108 /* get memory bank layout from prom */
109 __prom_get_memconf(&memconf);
110
111 pr_debug("prom_get_mem_conf memory configuration:\n");
112 for (i = 0;i < 8 && memconf[i].size; i++) {
113 if (sni_brd_type == SNI_BRD_PCI_TOWER ||
114 sni_brd_type == SNI_BRD_PCI_TOWER_CPLUS) {
115 if (memconf[i].base >= 0x20000000 &&
116 memconf[i].base < 0x30000000) {
117 memconf[i].base -= 0x20000000;
118 }
119 }
120 pr_debug("Bank%d: %08x @ %08x\n", i,
121 memconf[i].size, memconf[i].base);
122 add_memory_region(memconf[i].base, memconf[i].size, BOOT_MEM_RAM);
123 }
124}
125
126static void __init sni_console_setup(void)
127{
128 char *ctype;
129 char *cdev;
130 char *baud;
131 int port;
132 static char options[8];
133
134 cdev = prom_getenv("console_dev");
135 if (strncmp (cdev, "tty", 3) == 0) {
136 ctype = prom_getenv("console");
137 switch (*ctype) {
138 default:
139 case 'l':
140 port = 0;
141 baud = prom_getenv("lbaud");
142 break;
143 case 'r':
144 port = 1;
145 baud = prom_getenv("rbaud");
146 break;
147 }
148 if (baud)
149 strcpy(options, baud);
150 if (strncmp (cdev, "tty552", 6) == 0)
151 add_preferred_console("ttyS", port, baud ? options : NULL);
152 else
153 add_preferred_console("ttySC", port, baud ? options : NULL);
154 }
155}
156
157void __init prom_init(void)
158{
159 int argc = fw_arg0;
160 char **argv = (void *)fw_arg1;
161 int i;
162 int cputype;
163
164 sni_brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE;
165 cputype = *(unsigned char *)SNI_IDPROM_CPUTYPE;
166 switch (sni_brd_type) {
167 case SNI_BRD_TOWER_OASIC:
168 switch (cputype) {
169 case SNI_CPU_M8030:
170 systype = "RM400-330";
171 break;
172 case SNI_CPU_M8031:
173 systype = "RM400-430";
174 break;
175 case SNI_CPU_M8037:
176 systype = "RM400-530";
177 break;
178 case SNI_CPU_M8034:
179 systype = "RM400-730";
180 break;
181 default:
182 systype = "RM400-xxx";
183 break;
184 }
185 break;
186 case SNI_BRD_MINITOWER:
187 switch (cputype) {
188 case SNI_CPU_M8021:
189 case SNI_CPU_M8043:
190 systype = "RM400-120";
191 break;
192 case SNI_CPU_M8040:
193 systype = "RM400-220";
194 break;
195 case SNI_CPU_M8053:
196 systype = "RM400-225";
197 break;
198 case SNI_CPU_M8050:
199 systype = "RM400-420";
200 break;
201 default:
202 systype = "RM400-xxx";
203 break;
204 }
205 break;
206 case SNI_BRD_PCI_TOWER:
207 systype = "RM400-Cxx";
208 break;
209 case SNI_BRD_RM200:
210 systype = "RM200-xxx";
211 break;
212 case SNI_BRD_PCI_MTOWER:
213 systype = "RM300-Cxx";
214 break;
215 case SNI_BRD_PCI_DESKTOP:
216 switch (read_c0_prid() & 0xff00) {
217 case PRID_IMP_R4600:
218 case PRID_IMP_R4700:
219 systype = "RM200-C20";
220 break;
221 case PRID_IMP_R5000:
222 systype = "RM200-C40";
223 break;
224 default:
225 systype = "RM200-Cxx";
226 break;
227 }
228 break;
229 case SNI_BRD_PCI_TOWER_CPLUS:
230 systype = "RM400-Exx";
231 break;
232 case SNI_BRD_PCI_MTOWER_CPLUS:
233 systype = "RM300-Exx";
234 break;
235 }
236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, systype);
237
238#ifdef DEBUG
239 sni_idprom_dump();
240#endif
241 sni_mem_init();
242 sni_console_setup();
243
244 /* copy prom cmdline parameters to kernel cmdline */
245 for (i = 1; i < argc; i++) {
246 strcat(arcs_cmdline, argv[i]);
247 if (i < (argc - 1))
248 strcat(arcs_cmdline, " ");
249 }
250}
251
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 6f339af08d22..796e3ce28720 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -178,6 +178,7 @@ void __init plat_time_init(void)
178 sni_a20r_timer_setup(); 178 sni_a20r_timer_setup();
179 break; 179 break;
180 } 180 }
181 setup_pit_timer();
181} 182}
182 183
183unsigned long read_persistent_clock(void) 184unsigned long read_persistent_clock(void)
diff --git a/arch/mips/tx4927/common/Makefile b/arch/mips/tx4927/common/Makefile
index e8629617f25d..a7fe76a64964 100644
--- a/arch/mips/tx4927/common/Makefile
+++ b/arch/mips/tx4927/common/Makefile
@@ -2,7 +2,7 @@
2# Makefile for common code for Toshiba TX4927 based systems 2# Makefile for common code for Toshiba TX4927 based systems
3# 3#
4 4
5obj-y += tx4927_prom.o tx4927_setup.o tx4927_irq.o 5obj-y += tx4927_prom.o tx4927_irq.o
6 6
7obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 7obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
8obj-$(CONFIG_KGDB) += tx4927_dbgio.o 8obj-$(CONFIG_KGDB) += tx4927_dbgio.o
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
deleted file mode 100644
index 36c5f200eb3d..000000000000
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2002 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#include <linux/errno.h>
28#include <linux/init.h>
29#include <linux/kernel_stat.h>
30#include <linux/module.h>
31#include <linux/signal.h>
32#include <linux/sched.h>
33#include <linux/types.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/timex.h>
37#include <linux/slab.h>
38#include <linux/random.h>
39#include <linux/irq.h>
40#include <linux/bitops.h>
41#include <asm/bootinfo.h>
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/mipsregs.h>
45#include <asm/system.h>
46#include <asm/time.h>
47#include <asm/tx4927/tx4927.h>
48
49
50#undef DEBUG
51
52void dump_cp0(char *key);
53
54
55void __init plat_mem_setup(void)
56{
57#ifdef CONFIG_TOSHIBA_RBTX4927
58 {
59 extern void toshiba_rbtx4927_setup(void);
60 toshiba_rbtx4927_setup();
61 }
62#endif
63}
64
65void __init plat_time_init(void)
66{
67#ifdef CONFIG_TOSHIBA_RBTX4927
68 {
69 extern void toshiba_rbtx4927_time_init(void);
70 toshiba_rbtx4927_time_init();
71 }
72#endif
73}
74
75#ifdef DEBUG
76void print_cp0(char *key, int num, char *name, u32 val)
77{
78 printk("%s cp0:%02d:%s=0x%08x\n", key, num, name, val);
79 return;
80}
81
82void
83dump_cp0(char *key)
84{
85 if (key == NULL)
86 key = "";
87
88 print_cp0(key, 0, "INDEX ", read_c0_index());
89 print_cp0(key, 2, "ENTRYLO1", read_c0_entrylo0());
90 print_cp0(key, 3, "ENTRYLO2", read_c0_entrylo1());
91 print_cp0(key, 4, "CONTEXT ", read_c0_context());
92 print_cp0(key, 5, "PAGEMASK", read_c0_pagemask());
93 print_cp0(key, 6, "WIRED ", read_c0_wired());
94 //print_cp0(key, 8, "BADVADDR", read_c0_badvaddr());
95 print_cp0(key, 9, "COUNT ", read_c0_count());
96 print_cp0(key, 10, "ENTRYHI ", read_c0_entryhi());
97 print_cp0(key, 11, "COMPARE ", read_c0_compare());
98 print_cp0(key, 12, "STATUS ", read_c0_status());
99 print_cp0(key, 13, "CAUSE ", read_c0_cause() & 0xffff87ff);
100 print_cp0(key, 16, "CONFIG ", read_c0_config());
101 return;
102}
103
104void print_pic(char *key, unsigned long reg, char *name)
105{
106 printk(KERN_INFO "%s pic:0x%08lx:%s=0x%08x\n", key, reg, name,
107 __raw_readl((void __iomem *)reg));
108 return;
109}
110
111
112void dump_pic(char *key)
113{
114 if (key == NULL)
115 key = "";
116
117 print_pic(key, 0xff1ff600, "IRDEN ");
118 print_pic(key, 0xff1ff604, "IRDM0 ");
119 print_pic(key, 0xff1ff608, "IRDM1 ");
120
121 print_pic(key, 0xff1ff610, "IRLVL0 ");
122 print_pic(key, 0xff1ff614, "IRLVL1 ");
123 print_pic(key, 0xff1ff618, "IRLVL2 ");
124 print_pic(key, 0xff1ff61c, "IRLVL3 ");
125 print_pic(key, 0xff1ff620, "IRLVL4 ");
126 print_pic(key, 0xff1ff624, "IRLVL5 ");
127 print_pic(key, 0xff1ff628, "IRLVL6 ");
128 print_pic(key, 0xff1ff62c, "IRLVL7 ");
129
130 print_pic(key, 0xff1ff640, "IRMSK ");
131 print_pic(key, 0xff1ff660, "IREDC ");
132 print_pic(key, 0xff1ff680, "IRPND ");
133 print_pic(key, 0xff1ff6a0, "IRCS ");
134
135 print_pic(key, 0xff1ff514, "IRFLAG1 "); /* don't read IRLAG0 -- it hangs system */
136
137 print_pic(key, 0xff1ff518, "IRPOL ");
138 print_pic(key, 0xff1ff51c, "IRRCNT ");
139 print_pic(key, 0xff1ff520, "IRMASKINT");
140 print_pic(key, 0xff1ff524, "IRMASKEXT");
141
142 return;
143}
144
145
146void print_addr(char *hdr, char *key, unsigned long addr)
147{
148 printk(KERN_INFO "%s %s:0x%08lx=0x%08x\n", hdr, key, addr,
149 __raw_readl((void __iomem *)addr));
150 return;
151}
152
153
154void dump_180(char *key)
155{
156 u32 i;
157
158 for (i = 0x80000180; i < 0x80000180 + 0x80; i += 4) {
159 print_addr("180", key, i);
160 }
161 return;
162}
163
164
165void dump_eh0(char *key)
166{
167 int i;
168 extern unsigned long exception_handlers[];
169
170 for (i = (int) exception_handlers;
171 i < (int) (exception_handlers + 20); i += 4) {
172 print_addr("eh0", key, i);
173 }
174
175 return;
176}
177
178void pk0(void)
179{
180 volatile u32 val;
181
182 __asm__ __volatile__("ori %0, $26, 0":"=r"(val)
183 );
184 printk("k0=[0x%08x]\n", val);
185}
186#endif
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 0299595ce1c4..e466e5e711d8 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -45,27 +45,19 @@
45#include <linux/init.h> 45#include <linux/init.h>
46#include <linux/kernel.h> 46#include <linux/kernel.h>
47#include <linux/types.h> 47#include <linux/types.h>
48#include <linux/mm.h>
49#include <linux/swap.h>
50#include <linux/ioport.h> 48#include <linux/ioport.h>
51#include <linux/sched.h>
52#include <linux/interrupt.h> 49#include <linux/interrupt.h>
53#include <linux/pci.h> 50#include <linux/pci.h>
54#include <linux/timex.h>
55#include <linux/pm.h> 51#include <linux/pm.h>
56#include <linux/platform_device.h> 52#include <linux/platform_device.h>
53#include <linux/clk.h>
57 54
58#include <asm/bootinfo.h> 55#include <asm/bootinfo.h>
59#include <asm/page.h>
60#include <asm/io.h> 56#include <asm/io.h>
61#include <asm/irq.h>
62#include <asm/irq_regs.h>
63#include <asm/processor.h> 57#include <asm/processor.h>
64#include <asm/reboot.h> 58#include <asm/reboot.h>
65#include <asm/time.h> 59#include <asm/time.h>
66#include <asm/txx9tmr.h> 60#include <asm/txx9tmr.h>
67#include <linux/bootmem.h>
68#include <linux/blkdev.h>
69#ifdef CONFIG_TOSHIBA_FPCIB0 61#ifdef CONFIG_TOSHIBA_FPCIB0
70#include <asm/tx4927/smsc_fdc37m81x.h> 62#include <asm/tx4927/smsc_fdc37m81x.h>
71#endif 63#endif
@@ -73,42 +65,26 @@
73#ifdef CONFIG_PCI 65#ifdef CONFIG_PCI
74#include <asm/tx4927/tx4927_pci.h> 66#include <asm/tx4927/tx4927_pci.h>
75#endif 67#endif
76#ifdef CONFIG_BLK_DEV_IDEPCI
77#include <linux/hdreg.h>
78#include <linux/ide.h>
79#endif
80#ifdef CONFIG_SERIAL_TXX9 68#ifdef CONFIG_SERIAL_TXX9
81#include <linux/tty.h>
82#include <linux/serial.h>
83#include <linux/serial_core.h> 69#include <linux/serial_core.h>
84#endif 70#endif
85 71
86#undef TOSHIBA_RBTX4927_SETUP_DEBUG 72#undef TOSHIBA_RBTX4927_SETUP_DEBUG
87 73
88#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG 74#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
89#define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
90
91#define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
92#define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
93#define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
94
95#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
96#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) 75#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
97#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) 76#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
98#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) 77#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
99#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) 78#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
100#define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
101 79
102#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff 80#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
103#endif 81#endif
104 82
105#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG 83#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
106static const u32 toshiba_rbtx4927_setup_debug_flag = 84static const u32 toshiba_rbtx4927_setup_debug_flag =
107 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO | 85 (TOSHIBA_RBTX4927_SETUP_SETUP |
108 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
109 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
110 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 | 86 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
111 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66); 87 TOSHIBA_RBTX4927_SETUP_PCI2);
112#endif 88#endif
113 89
114#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG 90#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
@@ -718,7 +694,7 @@ void toshiba_rbtx4927_power_off(void)
718 /* no return */ 694 /* no return */
719} 695}
720 696
721void __init toshiba_rbtx4927_setup(void) 697void __init plat_mem_setup(void)
722{ 698{
723 int i; 699 int i;
724 u32 cp0_config; 700 u32 cp0_config;
@@ -741,13 +717,6 @@ void __init toshiba_rbtx4927_setup(void)
741 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 717 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
742 write_c0_config(cp0_config); 718 write_c0_config(cp0_config);
743 719
744#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
745 {
746 extern void dump_cp0(char *);
747 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
748 }
749#endif
750
751 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); 720 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
752 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, 721 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
753 ":mips_io_port_base=0x%08lx\n", 722 ":mips_io_port_base=0x%08lx\n",
@@ -835,6 +804,8 @@ void __init toshiba_rbtx4927_setup(void)
835 } 804 }
836 805
837 /* CCFG */ 806 /* CCFG */
807 /* do reset on watchdog */
808 tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR;
838 /* enable Timeout BusError */ 809 /* enable Timeout BusError */
839 if (tx4927_ccfg_toeon) 810 if (tx4927_ccfg_toeon)
840 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; 811 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
@@ -936,8 +907,7 @@ void __init toshiba_rbtx4927_setup(void)
936 "+\n"); 907 "+\n");
937} 908}
938 909
939void __init 910void __init plat_time_init(void)
940toshiba_rbtx4927_time_init(void)
941{ 911{
942 mips_hpt_frequency = tx4927_cpu_clock / 2; 912 mips_hpt_frequency = tx4927_cpu_clock / 2;
943 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) 913 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
@@ -977,3 +947,55 @@ static int __init rbtx4927_ne_init(void)
977 return IS_ERR(dev) ? PTR_ERR(dev) : 0; 947 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
978} 948}
979device_initcall(rbtx4927_ne_init); 949device_initcall(rbtx4927_ne_init);
950
951/* Watchdog support */
952
953static int __init txx9_wdt_init(unsigned long base)
954{
955 struct resource res = {
956 .start = base,
957 .end = base + 0x100 - 1,
958 .flags = IORESOURCE_MEM,
959 };
960 struct platform_device *dev =
961 platform_device_register_simple("txx9wdt", -1, &res, 1);
962 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
963}
964
965static int __init rbtx4927_wdt_init(void)
966{
967 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
968}
969device_initcall(rbtx4927_wdt_init);
970
971/* Minimum CLK support */
972
973struct clk *clk_get(struct device *dev, const char *id)
974{
975 if (!strcmp(id, "imbus_clk"))
976 return (struct clk *)50000000;
977 return ERR_PTR(-ENOENT);
978}
979EXPORT_SYMBOL(clk_get);
980
981int clk_enable(struct clk *clk)
982{
983 return 0;
984}
985EXPORT_SYMBOL(clk_enable);
986
987void clk_disable(struct clk *clk)
988{
989}
990EXPORT_SYMBOL(clk_disable);
991
992unsigned long clk_get_rate(struct clk *clk)
993{
994 return (unsigned long)clk;
995}
996EXPORT_SYMBOL(clk_get_rate);
997
998void clk_put(struct clk *clk)
999{
1000}
1001EXPORT_SYMBOL(clk_put);
diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile
index eff3d1d47f88..56aa1ed1ee0c 100644
--- a/arch/mips/tx4938/common/Makefile
+++ b/arch/mips/tx4938/common/Makefile
@@ -2,7 +2,7 @@
2# Makefile for common code for Toshiba TX4927 based systems 2# Makefile for common code for Toshiba TX4927 based systems
3# 3#
4 4
5obj-y += prom.o setup.o irq.o 5obj-y += prom.o irq.o
6obj-$(CONFIG_KGDB) += dbgio.o 6obj-$(CONFIG_KGDB) += dbgio.o
7 7
8EXTRA_CFLAGS += -Werror 8EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
deleted file mode 100644
index 3ba4101d141e..000000000000
--- a/arch/mips/tx4938/common/setup.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/setup.c
3 *
4 * common tx4938 setup routines
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13
14#include <linux/errno.h>
15#include <linux/init.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/timex.h>
24#include <linux/slab.h>
25#include <linux/random.h>
26#include <linux/irq.h>
27#include <linux/bitops.h>
28#include <asm/bootinfo.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mipsregs.h>
32#include <asm/system.h>
33#include <asm/time.h>
34#include <asm/tx4938/rbtx4938.h>
35
36extern void toshiba_rbtx4938_setup(void);
37
38void __init tx4938_setup(void);
39void dump_cp0(char *key);
40
41void __init
42plat_mem_setup(void)
43{
44 toshiba_rbtx4938_setup();
45}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
index 69f21c1b7942..1644bffa501a 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
@@ -47,7 +47,6 @@ void __init prom_init(void)
47#ifndef CONFIG_TX4938_NAND_BOOT 47#ifndef CONFIG_TX4938_NAND_BOOT
48 prom_init_cmdline(); 48 prom_init_cmdline();
49#endif 49#endif
50 mips_machtype = MACH_TOSHIBA_RBTX4938;
51 50
52 msize = tx4938_get_mem_size(); 51 msize = tx4938_get_mem_size();
53 add_memory_region(0, msize << 20, BOOT_MEM_RAM); 52 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index 632e5d201353..61249f049cd6 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -24,16 +24,12 @@
24 24
25#include <asm/wbflush.h> 25#include <asm/wbflush.h>
26#include <asm/reboot.h> 26#include <asm/reboot.h>
27#include <asm/irq.h>
28#include <asm/time.h> 27#include <asm/time.h>
29#include <asm/txx9tmr.h> 28#include <asm/txx9tmr.h>
30#include <asm/uaccess.h>
31#include <asm/io.h> 29#include <asm/io.h>
32#include <asm/bootinfo.h> 30#include <asm/bootinfo.h>
33#include <asm/tx4938/rbtx4938.h> 31#include <asm/tx4938/rbtx4938.h>
34#ifdef CONFIG_SERIAL_TXX9 32#ifdef CONFIG_SERIAL_TXX9
35#include <linux/tty.h>
36#include <linux/serial.h>
37#include <linux/serial_core.h> 33#include <linux/serial_core.h>
38#endif 34#endif
39#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
@@ -728,6 +724,8 @@ void __init tx4938_board_setup(void)
728 /* CCFG */ 724 /* CCFG */
729 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ 725 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
730 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; 726 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
727 /* do reset on watchdog */
728 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR;
731 /* clear PCIC1 reset */ 729 /* clear PCIC1 reset */
732 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) 730 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
733 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; 731 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
@@ -855,7 +853,7 @@ void __init plat_time_init(void)
855 txx9_gbus_clock / 2); 853 txx9_gbus_clock / 2);
856} 854}
857 855
858void __init toshiba_rbtx4938_setup(void) 856void __init plat_mem_setup(void)
859{ 857{
860 unsigned long long pcfg; 858 unsigned long long pcfg;
861 char *argptr; 859 char *argptr;
@@ -1125,12 +1123,35 @@ static int __init rbtx4938_spi_init(void)
1125} 1123}
1126arch_initcall(rbtx4938_spi_init); 1124arch_initcall(rbtx4938_spi_init);
1127 1125
1126/* Watchdog support */
1127
1128static int __init txx9_wdt_init(unsigned long base)
1129{
1130 struct resource res = {
1131 .start = base,
1132 .end = base + 0x100 - 1,
1133 .flags = IORESOURCE_MEM,
1134 .parent = &tx4938_reg_resource,
1135 };
1136 struct platform_device *dev =
1137 platform_device_register_simple("txx9wdt", -1, &res, 1);
1138 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1139}
1140
1141static int __init rbtx4938_wdt_init(void)
1142{
1143 return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
1144}
1145device_initcall(rbtx4938_wdt_init);
1146
1128/* Minimum CLK support */ 1147/* Minimum CLK support */
1129 1148
1130struct clk *clk_get(struct device *dev, const char *id) 1149struct clk *clk_get(struct device *dev, const char *id)
1131{ 1150{
1132 if (!strcmp(id, "spi-baseclk")) 1151 if (!strcmp(id, "spi-baseclk"))
1133 return (struct clk *)(txx9_gbus_clock / 2 / 4); 1152 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1153 if (!strcmp(id, "imbus_clk"))
1154 return (struct clk *)(txx9_gbus_clock / 2);
1134 return ERR_PTR(-ENOENT); 1155 return ERR_PTR(-ENOENT);
1135} 1156}
1136EXPORT_SYMBOL(clk_get); 1157EXPORT_SYMBOL(clk_get);
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index 8d760df686c4..76d4b5ed3fc0 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -40,6 +40,8 @@ void __init plat_time_init(void)
40{ 40{
41 unsigned long tclock; 41 unsigned long tclock;
42 42
43 vr41xx_calculate_clock_frequency();
44
43 tclock = vr41xx_get_tclock_frequency(); 45 tclock = vr41xx_get_tclock_frequency();
44 if (current_cpu_data.processor_id == PRID_VR4131_REV2_0 || 46 if (current_cpu_data.processor_id == PRID_VR4131_REV2_0 ||
45 current_cpu_data.processor_id == PRID_VR4131_REV2_1) 47 current_cpu_data.processor_id == PRID_VR4131_REV2_1)
@@ -50,8 +52,6 @@ void __init plat_time_init(void)
50 52
51void __init plat_mem_setup(void) 53void __init plat_mem_setup(void)
52{ 54{
53 vr41xx_calculate_clock_frequency();
54
55 iomem_resource_init(); 55 iomem_resource_init();
56} 56}
57 57
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
index 58e47686b499..7723d2011b08 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
@@ -50,7 +50,7 @@ static struct mtd_partition cmbvr4133_mtd_parts[] = {
50 } 50 }
51}; 51};
52 52
53#define number_partitions (sizeof(cmbvr4133_mtd_parts)/sizeof(struct mtd_partition)) 53#define number_partitions ARRAY_SIZE(cmbvr4133_mtd_parts)
54#endif 54#endif
55 55
56extern void i8259_init(void); 56extern void i8259_init(void);
@@ -64,8 +64,6 @@ static void __init nec_cmbvr4133_setup(void)
64#endif 64#endif
65 set_io_port_base(KSEG1ADDR(0x16000000)); 65 set_io_port_base(KSEG1ADDR(0x16000000));
66 66
67 mips_machtype = MACH_NEC_CMBVR4133;
68
69#ifdef CONFIG_PCI 67#ifdef CONFIG_PCI
70#ifdef CONFIG_ROCKHOPPER 68#ifdef CONFIG_ROCKHOPPER
71 ali_m5229_preinit(); 69 ali_m5229_preinit();
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 0bb7a93b7a5e..569f80aacbd2 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -127,7 +127,7 @@
127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
130 ((cm)<<59) | (a)) 130 (_CONST64_(cm) << 59) | (a))
131 131
132/* 132/*
133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting 133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
index 12e17581b823..608cfcfbb3ea 100644
--- a/include/asm-mips/asm.h
+++ b/include/asm-mips/asm.h
@@ -398,4 +398,12 @@ symbol = value
398 398
399#define SSNOP sll zero, zero, 1 399#define SSNOP sll zero, zero, 1
400 400
401#ifdef CONFIG_SGI_IP28
402/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
403#include <asm/cacheops.h>
404#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
405#else
406#define R10KCBARRIER(addr)
407#endif
408
401#endif /* __ASM_ASM_H */ 409#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b2dd9b33de8f..e031bdff9920 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -48,22 +48,11 @@
48#define MACH_DS5900 10 /* DECsystem 5900 */ 48#define MACH_DS5900 10 /* DECsystem 5900 */
49 49
50/* 50/*
51 * Valid machtype for group ARC
52 */
53#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */
54#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */
55
56/*
57 * Valid machtype for group SNI_RM 51 * Valid machtype for group SNI_RM
58 */ 52 */
59#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ 53#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */
60 54
61/* 55/*
62 * Valid machtype for group ACN
63 */
64#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */
65
66/*
67 * Valid machtype for group SGI 56 * Valid machtype for group SGI
68 */ 57 */
69#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ 58#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */
@@ -73,44 +62,6 @@
73#define MACH_SGI_IP30 4 /* Octane, Octane2 */ 62#define MACH_SGI_IP30 4 /* Octane, Octane2 */
74 63
75/* 64/*
76 * Valid machtype for group COBALT
77 */
78#define MACH_COBALT_27 0 /* Proto "27" hardware */
79
80/*
81 * Valid machtype for group BAGET
82 */
83#define MACH_BAGET201 0 /* BT23-201 */
84#define MACH_BAGET202 1 /* BT23-202 */
85
86/*
87 * Cosine boards.
88 */
89#define MACH_COSINE_ORION 0
90
91/*
92 * Valid machtype for group MOMENCO
93 */
94#define MACH_MOMENCO_OCELOT 0
95#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
96#define MACH_MOMENCO_OCELOT_C 2 /* no more supported (jun 2007) */
97#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */
98#define MACH_MOMENCO_OCELOT_3 4
99
100/*
101 * Valid machtype for group PHILIPS
102 */
103#define MACH_PHILIPS_NINO 0 /* Nino */
104#define MACH_PHILIPS_VELO 1 /* Velo */
105#define MACH_PHILIPS_JBS 2 /* JBS */
106#define MACH_PHILIPS_STB810 3 /* STB810 */
107
108/*
109 * Valid machtype for group SIBYTE
110 */
111#define MACH_SWARM 0
112
113/*
114 * Valid machtypes for group Toshiba 65 * Valid machtypes for group Toshiba
115 */ 66 */
116#define MACH_PALLAS 0 67#define MACH_PALLAS 0
@@ -122,64 +73,17 @@
122#define MACH_TOSHIBA_RBTX4938 6 73#define MACH_TOSHIBA_RBTX4938 6
123 74
124/* 75/*
125 * Valid machtype for group Alchemy
126 */
127#define MACH_PB1000 0 /* Au1000-based eval board */
128#define MACH_PB1100 1 /* Au1100-based eval board */
129#define MACH_PB1500 2 /* Au1500-based eval board */
130#define MACH_DB1000 3 /* Au1000-based eval board */
131#define MACH_DB1100 4 /* Au1100-based eval board */
132#define MACH_DB1500 5 /* Au1500-based eval board */
133#define MACH_XXS1500 6 /* Au1500-based eval board */
134#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
135#define MACH_PB1550 8 /* Au1550-based eval board */
136#define MACH_DB1550 9 /* Au1550-based eval board */
137#define MACH_PB1200 10 /* Au1200-based eval board */
138#define MACH_DB1200 11 /* Au1200-based eval board */
139
140/*
141 * Valid machtype for group NEC_VR41XX
142 *
143 * Various NEC-based devices.
144 *
145 * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by
146 * technical properties, so no new additions to this group.
147 */
148#define MACH_NEC_OSPREY 0 /* Osprey eval board */
149#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */
150#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */
151#define MACH_VICTOR_MPC30X 3 /* Victor MP-C303/304 */
152#define MACH_IBM_WORKPAD 4 /* IBM WorkPad z50 */
153#define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */
154#define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */
155#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
156#define MACH_NEC_CMBVR4133 8 /* CMB VR4133 Board */
157
158#define MACH_HP_LASERJET 1
159
160/*
161 * Valid machtype for group LASAT 76 * Valid machtype for group LASAT
162 */ 77 */
163#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ 78#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
164#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ 79#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
165 80
166/* 81/*
167 * Valid machtype for group TITAN
168 */
169#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
170#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
171
172/*
173 * Valid machtype for group NEC EMMA2RH 82 * Valid machtype for group NEC EMMA2RH
174 */ 83 */
175#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */ 84#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
176 85
177/* 86/*
178 * Valid machtype for group LEMOTE
179 */
180#define MACH_LEMOTE_FULONG 0
181
182/*
183 * Valid machtype for group PMC-MSP 87 * Valid machtype for group PMC-MSP
184 */ 88 */
185#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ 89#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
@@ -190,16 +94,9 @@
190#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ 94#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
191#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ 95#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
192 96
193#define MACH_WRPPMC 1
194
195/*
196 * Valid machtype for group Broadcom
197 */
198#define MACH_GROUP_BRCM 23 /* Broadcom */
199#define MACH_BCM47XX 1 /* Broadcom BCM47XX */
200
201#define CL_SIZE COMMAND_LINE_SIZE 97#define CL_SIZE COMMAND_LINE_SIZE
202 98
99extern char *system_type;
203const char *get_system_type(void); 100const char *get_system_type(void);
204 101
205extern unsigned long mips_machtype; 102extern unsigned long mips_machtype;
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index 0d7f9c1f5546..9dc10df32078 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -1,19 +1,34 @@
1/* 1/*
2 * This is included by init/main.c to check for architecture-dependent bugs. 2 * This is included by init/main.c to check for architecture-dependent bugs.
3 * 3 *
4 * Copyright (C) 2007 Maciej W. Rozycki
5 *
4 * Needs: 6 * Needs:
5 * void check_bugs(void); 7 * void check_bugs(void);
6 */ 8 */
7#ifndef _ASM_BUGS_H 9#ifndef _ASM_BUGS_H
8#define _ASM_BUGS_H 10#define _ASM_BUGS_H
9 11
12#include <linux/bug.h>
10#include <linux/delay.h> 13#include <linux/delay.h>
14
11#include <asm/cpu.h> 15#include <asm/cpu.h>
12#include <asm/cpu-info.h> 16#include <asm/cpu-info.h>
13 17
18extern int daddiu_bug;
19
20extern void check_bugs64_early(void);
21
14extern void check_bugs32(void); 22extern void check_bugs32(void);
15extern void check_bugs64(void); 23extern void check_bugs64(void);
16 24
25static inline void check_bugs_early(void)
26{
27#ifdef CONFIG_64BIT
28 check_bugs64_early();
29#endif
30}
31
17static inline void check_bugs(void) 32static inline void check_bugs(void)
18{ 33{
19 unsigned int cpu = smp_processor_id(); 34 unsigned int cpu = smp_processor_id();
@@ -25,4 +40,14 @@ static inline void check_bugs(void)
25#endif 40#endif
26} 41}
27 42
43static inline int r4k_daddiu_bug(void)
44{
45#ifdef CONFIG_64BIT
46 WARN_ON(daddiu_bug < 0);
47 return daddiu_bug != 0;
48#else
49 return 0;
50#endif
51}
52
28#endif /* _ASM_BUGS_H */ 53#endif /* _ASM_BUGS_H */
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index ed5c02c6afbb..0c5a358863f3 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -55,6 +55,7 @@ struct cpuinfo_mips {
55 struct cache_desc scache; /* Secondary cache */ 55 struct cache_desc scache; /* Secondary cache */
56 struct cache_desc tcache; /* Tertiary/split secondary cache */ 56 struct cache_desc tcache; /* Tertiary/split secondary cache */
57 int srsets; /* Shadow register sets */ 57 int srsets; /* Shadow register sets */
58 int core; /* physical core number */
58#if defined(CONFIG_MIPS_MT_SMTC) 59#if defined(CONFIG_MIPS_MT_SMTC)
59 /* 60 /*
60 * In the MIPS MT "SMTC" model, each TC is considered 61 * In the MIPS MT "SMTC" model, each TC is considered
@@ -63,8 +64,10 @@ struct cpuinfo_mips {
63 * to all TCs within the same VPE. 64 * to all TCs within the same VPE.
64 */ 65 */
65 int vpe_id; /* Virtual Processor number */ 66 int vpe_id; /* Virtual Processor number */
66 int tc_id; /* Thread Context number */
67#endif /* CONFIG_MIPS_MT */ 67#endif /* CONFIG_MIPS_MT */
68#ifdef CONFIG_MIPS_MT_SMTC
69 int tc_id; /* Thread Context number */
70#endif
68 void *data; /* Additional data */ 71 void *data; /* Additional data */
69} __attribute__((aligned(SMP_CACHE_BYTES))); 72} __attribute__((aligned(SMP_CACHE_BYTES)));
70 73
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 54fc18a4e5a8..bf5bbc78a9f7 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -195,8 +195,8 @@ enum cpu_type_enum {
195 * MIPS32 class processors 195 * MIPS32 class processors
196 */ 196 */
197 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000, 197 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
198 CPU_AU1100, CPU_AU1200, CPU_AU1500, CPU_AU1550, CPU_PR4450, 198 CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550,
199 CPU_BCM3302, CPU_BCM4710, 199 CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
200 200
201 /* 201 /*
202 * MIPS64 class processors 202 * MIPS64 class processors
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index fab32131e9b4..b0bccd2c4ed5 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -6,13 +6,16 @@
6 * Copyright (C) 1994 by Waldorf Electronics 6 * Copyright (C) 1994 by Waldorf Electronics
7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle 7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
9 */ 10 */
10#ifndef _ASM_DELAY_H 11#ifndef _ASM_DELAY_H
11#define _ASM_DELAY_H 12#define _ASM_DELAY_H
12 13
13#include <linux/param.h> 14#include <linux/param.h>
14#include <linux/smp.h> 15#include <linux/smp.h>
16
15#include <asm/compiler.h> 17#include <asm/compiler.h>
18#include <asm/war.h>
16 19
17static inline void __delay(unsigned long loops) 20static inline void __delay(unsigned long loops)
18{ 21{
@@ -25,7 +28,7 @@ static inline void __delay(unsigned long loops)
25 " .set reorder \n" 28 " .set reorder \n"
26 : "=r" (loops) 29 : "=r" (loops)
27 : "0" (loops)); 30 : "0" (loops));
28 else if (sizeof(long) == 8) 31 else if (sizeof(long) == 8 && !DADDI_WAR)
29 __asm__ __volatile__ ( 32 __asm__ __volatile__ (
30 " .set noreorder \n" 33 " .set noreorder \n"
31 " .align 3 \n" 34 " .align 3 \n"
@@ -34,6 +37,15 @@ static inline void __delay(unsigned long loops)
34 " .set reorder \n" 37 " .set reorder \n"
35 : "=r" (loops) 38 : "=r" (loops)
36 : "0" (loops)); 39 : "0" (loops));
40 else if (sizeof(long) == 8 && DADDI_WAR)
41 __asm__ __volatile__ (
42 " .set noreorder \n"
43 " .align 3 \n"
44 "1: bnez %0, 1b \n"
45 " dsubu %0, %2 \n"
46 " .set reorder \n"
47 : "=r" (loops)
48 : "0" (loops), "r" (1));
37} 49}
38 50
39 51
@@ -50,7 +62,7 @@ static inline void __delay(unsigned long loops)
50 62
51static inline void __udelay(unsigned long usecs, unsigned long lpj) 63static inline void __udelay(unsigned long usecs, unsigned long lpj)
52{ 64{
53 unsigned long lo; 65 unsigned long hi, lo;
54 66
55 /* 67 /*
56 * The rates of 128 is rounded wrongly by the catchall case 68 * The rates of 128 is rounded wrongly by the catchall case
@@ -70,11 +82,16 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
70 : "=h" (usecs), "=l" (lo) 82 : "=h" (usecs), "=l" (lo)
71 : "r" (usecs), "r" (lpj) 83 : "r" (usecs), "r" (lpj)
72 : GCC_REG_ACCUM); 84 : GCC_REG_ACCUM);
73 else if (sizeof(long) == 8) 85 else if (sizeof(long) == 8 && !R4000_WAR)
74 __asm__("dmultu\t%2, %3" 86 __asm__("dmultu\t%2, %3"
75 : "=h" (usecs), "=l" (lo) 87 : "=h" (usecs), "=l" (lo)
76 : "r" (usecs), "r" (lpj) 88 : "r" (usecs), "r" (lpj)
77 : GCC_REG_ACCUM); 89 : GCC_REG_ACCUM);
90 else if (sizeof(long) == 8 && R4000_WAR)
91 __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
92 : "=r" (usecs), "=h" (hi), "=l" (lo)
93 : "r" (usecs), "r" (lpj)
94 : GCC_REG_ACCUM);
78 95
79 __delay(usecs); 96 __delay(usecs);
80} 97}
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index d6a6c21f16db..1353c81065d1 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -84,10 +84,9 @@
84 * Deskstations or Acer PICA but not the much more versatile DMA logic used 84 * Deskstations or Acer PICA but not the much more versatile DMA logic used
85 * for the local devices on Acer PICA or Magnums. 85 * for the local devices on Acer PICA or Magnums.
86 */ 86 */
87#ifdef CONFIG_SGI_IP22 87#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
88/* Horrible hack to have a correct DMA window on IP22 */ 88/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
89#include <asm/sgi/mc.h> 89#define MAX_DMA_ADDRESS PAGE_OFFSET
90#define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000)
91#else 90#else
92#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) 91#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
93#endif 92#endif
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index f27b96cfac2e..9cc8522a394f 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -60,16 +60,6 @@ enum fixed_addresses {
60 __end_of_fixed_addresses 60 __end_of_fixed_addresses
61}; 61};
62 62
63extern void __set_fixmap(enum fixed_addresses idx,
64 unsigned long phys, pgprot_t flags);
65
66#define set_fixmap(idx, phys) \
67 __set_fixmap(idx, phys, PAGE_KERNEL)
68/*
69 * Some hardware wants to get fixmapped without caching.
70 */
71#define set_fixmap_nocache(idx, phys) \
72 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
73/* 63/*
74 * used by vmalloc.c. 64 * used by vmalloc.c.
75 * 65 *
diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h
index 1003e7156bfc..0995575db320 100644
--- a/include/asm-mips/fw/cfe/cfe_api.h
+++ b/include/asm-mips/fw/cfe/cfe_api.h
@@ -15,49 +15,27 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18/*
19/* ********************************************************************* 19 * Broadcom Common Firmware Environment (CFE)
20 * 20 *
21 * Broadcom Common Firmware Environment (CFE) 21 * This file contains declarations for doing callbacks to
22 * 22 * cfe from an application. It should be the only header
23 * Device function prototypes File: cfe_api.h 23 * needed by the application to use this library
24 * 24 *
25 * This file contains declarations for doing callbacks to 25 * Authors: Mitch Lichtenberg, Chris Demetriou
26 * cfe from an application. It should be the only header 26 */
27 * needed by the application to use this library
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#ifndef CFE_API_H 27#ifndef CFE_API_H
34#define CFE_API_H 28#define CFE_API_H
35 29
36/*
37 * Apply customizations here for different OSes. These need to:
38 * * typedef uint64_t, int64_t, intptr_t, uintptr_t.
39 * * define cfe_strlen() if use of an existing function is desired.
40 * * define CFE_API_IMPL_NAMESPACE if API functions are to use
41 * names in the implementation namespace.
42 * Also, optionally, if the build environment does not do so automatically,
43 * CFE_API_* can be defined here as desired.
44 */
45/* Begin customization. */
46#include <linux/types.h> 30#include <linux/types.h>
47#include <linux/string.h> 31#include <linux/string.h>
48 32
49typedef long intptr_t; 33typedef long intptr_t;
50 34
51#define cfe_strlen strlen
52 35
53#define CFE_API_ALL 36/*
54#define CFE_API_STRLEN_CUSTOM 37 * Constants
55/* End customization. */ 38 */
56
57
58/* *********************************************************************
59 * Constants
60 ********************************************************************* */
61 39
62/* Seal indicating CFE's presence, passed to user program. */ 40/* Seal indicating CFE's presence, passed to user program. */
63#define CFE_EPTSEAL 0x43464531 41#define CFE_EPTSEAL 0x43464531
@@ -109,54 +87,13 @@ typedef struct {
109 87
110 88
111/* 89/*
112 * cfe_strlen is handled specially: If already defined, it has been
113 * overridden in this environment with a standard strlen-like function.
114 */
115#ifdef cfe_strlen
116# define CFE_API_STRLEN_CUSTOM
117#else
118# ifdef CFE_API_IMPL_NAMESPACE
119# define cfe_strlen(a) __cfe_strlen(a)
120# endif
121int cfe_strlen(char *name);
122#endif
123
124/*
125 * Defines and prototypes for functions which take no arguments. 90 * Defines and prototypes for functions which take no arguments.
126 */ 91 */
127#ifdef CFE_API_IMPL_NAMESPACE
128int64_t __cfe_getticks(void);
129#define cfe_getticks() __cfe_getticks()
130#else
131int64_t cfe_getticks(void); 92int64_t cfe_getticks(void);
132#endif
133 93
134/* 94/*
135 * Defines and prototypes for the rest of the functions. 95 * Defines and prototypes for the rest of the functions.
136 */ 96 */
137#ifdef CFE_API_IMPL_NAMESPACE
138#define cfe_close(a) __cfe_close(a)
139#define cfe_cpu_start(a, b, c, d, e) __cfe_cpu_start(a, b, c, d, e)
140#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
141#define cfe_enumenv(a, b, d, e, f) __cfe_enumenv(a, b, d, e, f)
142#define cfe_enummem(a, b, c, d, e) __cfe_enummem(a, b, c, d, e)
143#define cfe_exit(a, b) __cfe_exit(a, b)
144#define cfe_flushcache(a) __cfe_cacheflush(a)
145#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
146#define cfe_getenv(a, b, c) __cfe_getenv(a, b, c)
147#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
148#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
149#define cfe_init(a, b) __cfe_init(a, b)
150#define cfe_inpstat(a) __cfe_inpstat(a)
151#define cfe_ioctl(a, b, c, d, e, f) __cfe_ioctl(a, b, c, d, e, f)
152#define cfe_open(a) __cfe_open(a)
153#define cfe_read(a, b, c) __cfe_read(a, b, c)
154#define cfe_readblk(a, b, c, d) __cfe_readblk(a, b, c, d)
155#define cfe_setenv(a, b) __cfe_setenv(a, b)
156#define cfe_write(a, b, c) __cfe_write(a, b, c)
157#define cfe_writeblk(a, b, c, d) __cfe_writeblk(a, b, c, d)
158#endif /* CFE_API_IMPL_NAMESPACE */
159
160int cfe_close(int handle); 97int cfe_close(int handle);
161int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1); 98int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
162int cfe_cpu_stop(int cpu); 99int cfe_cpu_stop(int cpu);
diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h
index 975f00002cbe..b80374636279 100644
--- a/include/asm-mips/fw/cfe/cfe_error.h
+++ b/include/asm-mips/fw/cfe/cfe_error.h
@@ -16,18 +16,13 @@
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18
19/* ********************************************************************* 19/*
20 * 20 * Broadcom Common Firmware Environment (CFE)
21 * Broadcom Common Firmware Environment (CFE) 21 *
22 * 22 * CFE's global error code list is here.
23 * Error codes File: cfe_error.h 23 *
24 * 24 * Author: Mitch Lichtenberg
25 * CFE's global error code list is here. 25 */
26 *
27 * Author: Mitch Lichtenberg
28 *
29 ********************************************************************* */
30
31 26
32#define CFE_OK 0 27#define CFE_OK 0
33#define CFE_ERR -1 /* generic error */ 28#define CFE_ERR -1 /* generic error */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index a79e7caf3a86..5b9fce73f11d 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Lowlevel hardware stuff for the MIPS based Cobalt microservers. 2 * The Cobalt board ID information.
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General Public 4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
@@ -12,9 +12,6 @@
12#ifndef __ASM_COBALT_H 12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H 13#define __ASM_COBALT_H
14 14
15/*
16 * The Cobalt board ID information.
17 */
18extern int cobalt_board_id; 15extern int cobalt_board_id;
19 16
20#define COBALT_BRD_ID_QUBE1 0x3 17#define COBALT_BRD_ID_QUBE1 0x3
@@ -22,14 +19,4 @@ extern int cobalt_board_id;
22#define COBALT_BRD_ID_QUBE2 0x5 19#define COBALT_BRD_ID_QUBE2 0x5
23#define COBALT_BRD_ID_RAQ2 0x6 20#define COBALT_BRD_ID_RAQ2 0x6
24 21
25#define COBALT_KEY_PORT ((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
26# define COBALT_KEY_CLEAR (1 << 1)
27# define COBALT_KEY_LEFT (1 << 2)
28# define COBALT_KEY_UP (1 << 3)
29# define COBALT_KEY_DOWN (1 << 4)
30# define COBALT_KEY_RIGHT (1 << 5)
31# define COBALT_KEY_ENTER (1 << 6)
32# define COBALT_KEY_SELECT (1 << 7)
33# define COBALT_KEY_MASK 0xfe
34
35#endif /* __ASM_COBALT_H */ 22#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/mach-ip28/cpu-feature-overrides.h b/include/asm-mips/mach-ip28/cpu-feature-overrides.h
new file mode 100644
index 000000000000..9a53b326f848
--- /dev/null
+++ b/include/asm-mips/mach-ip28/cpu-feature-overrides.h
@@ -0,0 +1,50 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 * 6/2004 pf
8 */
9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * IP28 only comes with R10000 family processors all using the same config
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 /* see probe_pcache() */
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_icache_snoops_remote_store 1
31#define cpu_has_mipsmt 0
32#define cpu_has_userlocal 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_4kex 1
38#define cpu_has_4k_cache 1
39
40#define cpu_has_inclusive_pcaches 1
41
42#define cpu_dcache_line_size() 32
43#define cpu_icache_line_size() 64
44
45#define cpu_has_mips32r1 0
46#define cpu_has_mips32r2 0
47#define cpu_has_mips64r1 0
48#define cpu_has_mips64r2 0
49
50#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip28/ds1286.h b/include/asm-mips/mach-ip28/ds1286.h
new file mode 100644
index 000000000000..471bb9a33e0f
--- /dev/null
+++ b/include/asm-mips/mach-ip28/ds1286.h
@@ -0,0 +1,4 @@
1#ifndef __ASM_MACH_IP28_DS1286_H
2#define __ASM_MACH_IP28_DS1286_H
3#include <asm/mach-ip22/ds1286.h>
4#endif /* __ASM_MACH_IP28_DS1286_H */
diff --git a/include/asm-mips/mach-ip28/spaces.h b/include/asm-mips/mach-ip28/spaces.h
new file mode 100644
index 000000000000..05aabb27e5e7
--- /dev/null
+++ b/include/asm-mips/mach-ip28/spaces.h
@@ -0,0 +1,22 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
9 * 2004 pf
10 */
11#ifndef _ASM_MACH_IP28_SPACES_H
12#define _ASM_MACH_IP28_SPACES_H
13
14#define CAC_BASE 0xa800000000000000
15
16#define HIGHMEM_START (~0UL)
17
18#define PHYS_OFFSET _AC(0x20000000, UL)
19
20#include <asm/mach-generic/spaces.h>
21
22#endif /* _ASM_MACH_IP28_SPACES_H */
diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-ip28/war.h
index 0eaf0c548a47..a1baafab486a 100644
--- a/include/asm-mips/mach-qemu/war.h
+++ b/include/asm-mips/mach-ip28/war.h
@@ -5,8 +5,8 @@
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */ 7 */
8#ifndef __ASM_MIPS_MACH_QEMU_WAR_H 8#ifndef __ASM_MIPS_MACH_IP28_WAR_H
9#define __ASM_MIPS_MACH_QEMU_WAR_H 9#define __ASM_MIPS_MACH_IP28_WAR_H
10 10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 12#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -19,7 +19,7 @@
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0 20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
24 24
25#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ 25#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
deleted file mode 100644
index d2daaed235d5..000000000000
--- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 07 Ralf Baechle
7 */
8#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
13 */
14#define cpu_has_mips16 0
15#define cpu_has_divec 0
16#define cpu_has_cache_cdex_p 0
17#define cpu_has_prefetch 0
18#define cpu_has_mcheck 0
19#define cpu_has_ejtag 0
20
21#define cpu_has_llsc 1
22#define cpu_has_vtag_icache 0
23#define cpu_has_dc_aliases 0
24#define cpu_has_ic_fills_f_dc 0
25
26#define cpu_has_dsp 0
27#define cpu_has_mipsmt 0
28
29#define cpu_has_nofpuex 0
30#define cpu_has_64bits 0
31
32#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index d58977483534..1c39d339521e 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -97,10 +97,16 @@ extern int mips_revision_corid;
97 97
98extern int mips_revision_sconid; 98extern int mips_revision_sconid;
99 99
100extern void mips_reboot_setup(void);
101
100#ifdef CONFIG_PCI 102#ifdef CONFIG_PCI
101extern void mips_pcibios_init(void); 103extern void mips_pcibios_init(void);
102#else 104#else
103#define mips_pcibios_init() do { } while (0) 105#define mips_pcibios_init() do { } while (0)
104#endif 106#endif
105 107
108#ifdef CONFIG_KGDB
109extern void kgdb_config(void);
110#endif
111
106#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 112#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h
index ce7cff7f1e8e..146d41b67adc 100644
--- a/include/asm-mips/mipsprom.h
+++ b/include/asm-mips/mipsprom.h
@@ -71,4 +71,6 @@
71#define PROM_NV_GET 53 /* XXX */ 71#define PROM_NV_GET 53 /* XXX */
72#define PROM_NV_SET 54 /* XXX */ 72#define PROM_NV_SET 54 /* XXX */
73 73
74extern char *prom_getenv(char *);
75
74#endif /* __ASM_MIPS_PROM_H */ 76#endif /* __ASM_MIPS_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
index 0b56f55206c6..603eb737b4a8 100644
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
+++ b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
@@ -585,11 +585,7 @@
585 * UART defines * 585 * UART defines *
586 *************************************************************************** 586 ***************************************************************************
587 */ 587 */
588#ifndef CONFIG_MSP_FPGA
589#define MSP_BASE_BAUD 25000000 588#define MSP_BASE_BAUD 25000000
590#else
591#define MSP_BASE_BAUD 6000000
592#endif
593#define MSP_UART_REG_LEN 0x20 589#define MSP_UART_REG_LEN 0x20
594 590
595/* 591/*
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 2b8466ffd3ca..4c140db36786 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -403,6 +403,13 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
403__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) 403__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) 404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
405 405
406__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
407__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
408__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
409__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
410__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
411__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
412
406/* build blast_xxx_range, protected_blast_xxx_range */ 413/* build blast_xxx_range, protected_blast_xxx_range */
407#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ 414#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
408static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ 415static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index f3e3dc9bb732..343ed15f8dc4 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -138,8 +138,8 @@ struct sgioc_regs {
138 u8 _sysid[3]; 138 u8 _sysid[3];
139 volatile u8 sysid; 139 volatile u8 sysid;
140#define SGIOC_SYSID_FULLHOUSE 0x01 140#define SGIOC_SYSID_FULLHOUSE 0x01
141#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) 141#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
142#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1) 142#define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5)
143 u32 _unused2; 143 u32 _unused2;
144 u8 _read[3]; 144 u8 _read[3];
145 volatile u8 read; 145 volatile u8 read;
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
index da198a1c8c81..25372ae0e814 100644
--- a/include/asm-mips/sibyte/board.h
+++ b/include/asm-mips/sibyte/board.h
@@ -19,10 +19,8 @@
19#ifndef _SIBYTE_BOARD_H 19#ifndef _SIBYTE_BOARD_H
20#define _SIBYTE_BOARD_H 20#define _SIBYTE_BOARD_H
21 21
22#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ 22#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
23 defined(CONFIG_SIBYTE_PT1120) || defined(CONFIG_SIBYTE_PT1125) || \ 23 defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
24 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
25 defined(CONFIG_SIBYTE_LITTLESUR)
26#include <asm/sibyte/swarm.h> 24#include <asm/sibyte/swarm.h>
27#endif 25#endif
28 26
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
index 0dad844a3b5b..80c1a052662a 100644
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -48,12 +48,10 @@ extern unsigned int zbbus_mhz;
48extern void sb1250_time_init(void); 48extern void sb1250_time_init(void);
49extern void sb1250_mask_irq(int cpu, int irq); 49extern void sb1250_mask_irq(int cpu, int irq);
50extern void sb1250_unmask_irq(int cpu, int irq); 50extern void sb1250_unmask_irq(int cpu, int irq);
51extern void sb1250_smp_finish(void);
52 51
53extern void bcm1480_time_init(void); 52extern void bcm1480_time_init(void);
54extern void bcm1480_mask_irq(int cpu, int irq); 53extern void bcm1480_mask_irq(int cpu, int irq);
55extern void bcm1480_unmask_irq(int cpu, int irq); 54extern void bcm1480_unmask_irq(int cpu, int irq);
56extern void bcm1480_smp_finish(void);
57 55
58#define AT_spin \ 56#define AT_spin \
59 __asm__ __volatile__ ( \ 57 __asm__ __volatile__ ( \
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
index 540865fa7ec3..114d9d29ca9d 100644
--- a/include/asm-mips/sibyte/swarm.h
+++ b/include/asm-mips/sibyte/swarm.h
@@ -26,24 +26,6 @@
26#define SIBYTE_HAVE_PCMCIA 1 26#define SIBYTE_HAVE_PCMCIA 1
27#define SIBYTE_HAVE_IDE 1 27#define SIBYTE_HAVE_IDE 1
28#endif 28#endif
29#ifdef CONFIG_SIBYTE_PTSWARM
30#define SIBYTE_BOARD_NAME "PTSWARM"
31#define SIBYTE_HAVE_PCMCIA 1
32#define SIBYTE_HAVE_IDE 1
33#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
34#endif
35#ifdef CONFIG_SIBYTE_PT1120
36#define SIBYTE_BOARD_NAME "PT1120"
37#define SIBYTE_HAVE_PCMCIA 1
38#define SIBYTE_HAVE_IDE 1
39#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
40#endif
41#ifdef CONFIG_SIBYTE_PT1125
42#define SIBYTE_BOARD_NAME "PT1125"
43#define SIBYTE_HAVE_PCMCIA 1
44#define SIBYTE_HAVE_IDE 1
45#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
46#endif
47#ifdef CONFIG_SIBYTE_LITTLESUR 29#ifdef CONFIG_SIBYTE_LITTLESUR
48#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" 30#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
49#define SIBYTE_HAVE_PCMCIA 0 31#define SIBYTE_HAVE_PCMCIA 0
diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h
new file mode 100644
index 000000000000..b17fdfb5d818
--- /dev/null
+++ b/include/asm-mips/smp-ops.h
@@ -0,0 +1,56 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General
3 * Public License. See the file "COPYING" in the main directory of this
4 * archive for more details.
5 *
6 * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
7 * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
8 * Copyright (C) 2000, 2001, 2002 Ralf Baechle
9 * Copyright (C) 2000, 2001 Broadcom Corporation
10 */
11#ifndef __ASM_SMP_OPS_H
12#define __ASM_SMP_OPS_H
13
14#ifdef CONFIG_SMP
15
16#include <linux/cpumask.h>
17
18struct plat_smp_ops {
19 void (*send_ipi_single)(int cpu, unsigned int action);
20 void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
21 void (*init_secondary)(void);
22 void (*smp_finish)(void);
23 void (*cpus_done)(void);
24 void (*boot_secondary)(int cpu, struct task_struct *idle);
25 void (*smp_setup)(void);
26 void (*prepare_cpus)(unsigned int max_cpus);
27};
28
29extern void register_smp_ops(struct plat_smp_ops *ops);
30
31static inline void plat_smp_setup(void)
32{
33 extern struct plat_smp_ops *mp_ops; /* private */
34
35 mp_ops->smp_setup();
36}
37
38#else /* !CONFIG_SMP */
39
40struct plat_smp_ops;
41
42static inline void plat_smp_setup(void)
43{
44 /* UP, nothing to do ... */
45}
46
47static inline void register_smp_ops(struct plat_smp_ops *ops)
48{
49}
50
51#endif /* !CONFIG_SMP */
52
53extern struct plat_smp_ops up_smp_ops;
54extern struct plat_smp_ops vsmp_smp_ops;
55
56#endif /* __ASM_SMP_OPS_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index dc770025a9b0..84fef1aeec0c 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -11,14 +11,16 @@
11#ifndef __ASM_SMP_H 11#ifndef __ASM_SMP_H
12#define __ASM_SMP_H 12#define __ASM_SMP_H
13 13
14
15#ifdef CONFIG_SMP
16
17#include <linux/bitops.h> 14#include <linux/bitops.h>
18#include <linux/linkage.h> 15#include <linux/linkage.h>
19#include <linux/threads.h> 16#include <linux/threads.h>
20#include <linux/cpumask.h> 17#include <linux/cpumask.h>
18
21#include <asm/atomic.h> 19#include <asm/atomic.h>
20#include <asm/smp-ops.h>
21
22extern int smp_num_siblings;
23extern cpumask_t cpu_sibling_map[];
22 24
23#define raw_smp_processor_id() (current_thread_info()->cpu) 25#define raw_smp_processor_id() (current_thread_info()->cpu)
24 26
@@ -49,56 +51,6 @@ extern struct call_data_struct *call_data;
49extern cpumask_t phys_cpu_present_map; 51extern cpumask_t phys_cpu_present_map;
50#define cpu_possible_map phys_cpu_present_map 52#define cpu_possible_map phys_cpu_present_map
51 53
52/*
53 * These are defined by the board-specific code.
54 */
55
56/*
57 * Cause the function described by call_data to be executed on the passed
58 * cpu. When the function has finished, increment the finished field of
59 * call_data.
60 */
61extern void core_send_ipi(int cpu, unsigned int action);
62
63static inline void core_send_ipi_mask(cpumask_t mask, unsigned int action)
64{
65 unsigned int i;
66
67 for_each_cpu_mask(i, mask)
68 core_send_ipi(i, action);
69}
70
71
72/*
73 * Firmware CPU startup hook
74 */
75extern void prom_boot_secondary(int cpu, struct task_struct *idle);
76
77/*
78 * After we've done initial boot, this function is called to allow the
79 * board code to clean up state, if needed
80 */
81extern void prom_init_secondary(void);
82
83/*
84 * Populate cpu_possible_map before smp_init, called from setup_arch.
85 */
86extern void plat_smp_setup(void);
87
88/*
89 * Called in smp_prepare_cpus.
90 */
91extern void plat_prepare_cpus(unsigned int max_cpus);
92
93/*
94 * Last chance for the board code to finish SMP initialization before
95 * the CPU is "online".
96 */
97extern void prom_smp_finish(void);
98
99/* Hook for after all CPUs are online */
100extern void prom_cpus_done(void);
101
102extern void asmlinkage smp_bootstrap(void); 54extern void asmlinkage smp_bootstrap(void);
103 55
104/* 56/*
@@ -108,11 +60,11 @@ extern void asmlinkage smp_bootstrap(void);
108 */ 60 */
109static inline void smp_send_reschedule(int cpu) 61static inline void smp_send_reschedule(int cpu)
110{ 62{
111 core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF); 63 extern struct plat_smp_ops *mp_ops; /* private */
64
65 mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
112} 66}
113 67
114extern asmlinkage void smp_call_function_interrupt(void); 68extern asmlinkage void smp_call_function_interrupt(void);
115 69
116#endif /* CONFIG_SMP */
117
118#endif /* __ASM_SMP_H */ 70#endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index af081457f847..e716447e5e03 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -35,23 +35,23 @@ extern unsigned int sni_brd_type;
35#define SNI_CPU_M8050 0x0b 35#define SNI_CPU_M8050 0x0b
36#define SNI_CPU_M8053 0x0d 36#define SNI_CPU_M8053 0x0d
37 37
38#define SNI_PORT_BASE 0xb4000000 38#define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
39 39
40#ifndef __MIPSEL__ 40#ifndef __MIPSEL__
41/* 41/*
42 * ASIC PCI registers for big endian configuration. 42 * ASIC PCI registers for big endian configuration.
43 */ 43 */
44#define PCIMT_UCONF 0xbfff0004 44#define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
45#define PCIMT_IOADTIMEOUT2 0xbfff000c 45#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
46#define PCIMT_IOMEMCONF 0xbfff0014 46#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
47#define PCIMT_IOMMU 0xbfff001c 47#define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
48#define PCIMT_IOADTIMEOUT1 0xbfff0024 48#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
49#define PCIMT_DMAACCESS 0xbfff002c 49#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
50#define PCIMT_DMAHIT 0xbfff0034 50#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
51#define PCIMT_ERRSTATUS 0xbfff003c 51#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
52#define PCIMT_ERRADDR 0xbfff0044 52#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
53#define PCIMT_SYNDROME 0xbfff004c 53#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
54#define PCIMT_ITPEND 0xbfff0054 54#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
55#define IT_INT2 0x01 55#define IT_INT2 0x01
56#define IT_INTD 0x02 56#define IT_INTD 0x02
57#define IT_INTC 0x04 57#define IT_INTC 0x04
@@ -60,32 +60,32 @@ extern unsigned int sni_brd_type;
60#define IT_EISA 0x20 60#define IT_EISA 0x20
61#define IT_SCSI 0x40 61#define IT_SCSI 0x40
62#define IT_ETH 0x80 62#define IT_ETH 0x80
63#define PCIMT_IRQSEL 0xbfff005c 63#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
64#define PCIMT_TESTMEM 0xbfff0064 64#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
65#define PCIMT_ECCREG 0xbfff006c 65#define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
66#define PCIMT_CONFIG_ADDRESS 0xbfff0074 66#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
67#define PCIMT_ASIC_ID 0xbfff007c /* read */ 67#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
68#define PCIMT_SOFT_RESET 0xbfff007c /* write */ 68#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
69#define PCIMT_PIA_OE 0xbfff0084 69#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
70#define PCIMT_PIA_DATAOUT 0xbfff008c 70#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
71#define PCIMT_PIA_DATAIN 0xbfff0094 71#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
72#define PCIMT_CACHECONF 0xbfff009c 72#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
73#define PCIMT_INVSPACE 0xbfff00a4 73#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
74#else 74#else
75/* 75/*
76 * ASIC PCI registers for little endian configuration. 76 * ASIC PCI registers for little endian configuration.
77 */ 77 */
78#define PCIMT_UCONF 0xbfff0000 78#define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
79#define PCIMT_IOADTIMEOUT2 0xbfff0008 79#define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
80#define PCIMT_IOMEMCONF 0xbfff0010 80#define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
81#define PCIMT_IOMMU 0xbfff0018 81#define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
82#define PCIMT_IOADTIMEOUT1 0xbfff0020 82#define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
83#define PCIMT_DMAACCESS 0xbfff0028 83#define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
84#define PCIMT_DMAHIT 0xbfff0030 84#define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
85#define PCIMT_ERRSTATUS 0xbfff0038 85#define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
86#define PCIMT_ERRADDR 0xbfff0040 86#define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
87#define PCIMT_SYNDROME 0xbfff0048 87#define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
88#define PCIMT_ITPEND 0xbfff0050 88#define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
89#define IT_INT2 0x01 89#define IT_INT2 0x01
90#define IT_INTD 0x02 90#define IT_INTD 0x02
91#define IT_INTC 0x04 91#define IT_INTC 0x04
@@ -94,20 +94,20 @@ extern unsigned int sni_brd_type;
94#define IT_EISA 0x20 94#define IT_EISA 0x20
95#define IT_SCSI 0x40 95#define IT_SCSI 0x40
96#define IT_ETH 0x80 96#define IT_ETH 0x80
97#define PCIMT_IRQSEL 0xbfff0058 97#define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
98#define PCIMT_TESTMEM 0xbfff0060 98#define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
99#define PCIMT_ECCREG 0xbfff0068 99#define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
100#define PCIMT_CONFIG_ADDRESS 0xbfff0070 100#define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
101#define PCIMT_ASIC_ID 0xbfff0078 /* read */ 101#define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
102#define PCIMT_SOFT_RESET 0xbfff0078 /* write */ 102#define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
103#define PCIMT_PIA_OE 0xbfff0080 103#define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
104#define PCIMT_PIA_DATAOUT 0xbfff0088 104#define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
105#define PCIMT_PIA_DATAIN 0xbfff0090 105#define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
106#define PCIMT_CACHECONF 0xbfff0098 106#define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
107#define PCIMT_INVSPACE 0xbfff00a0 107#define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
108#endif 108#endif
109 109
110#define PCIMT_PCI_CONF 0xbfff0100 110#define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
111 111
112/* 112/*
113 * Data port for the PCI bus in IO space 113 * Data port for the PCI bus in IO space
@@ -117,34 +117,34 @@ extern unsigned int sni_brd_type;
117/* 117/*
118 * Board specific registers 118 * Board specific registers
119 */ 119 */
120#define PCIMT_CSMSR 0xbfd00000 120#define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
121#define PCIMT_CSSWITCH 0xbfd10000 121#define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
122#define PCIMT_CSITPEND 0xbfd20000 122#define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
123#define PCIMT_AUTO_PO_EN 0xbfd30000 123#define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
124#define PCIMT_CLR_TEMP 0xbfd40000 124#define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
125#define PCIMT_AUTO_PO_DIS 0xbfd50000 125#define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
126#define PCIMT_EXMSR 0xbfd60000 126#define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
127#define PCIMT_UNUSED1 0xbfd70000 127#define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
128#define PCIMT_CSWCSM 0xbfd80000 128#define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
129#define PCIMT_UNUSED2 0xbfd90000 129#define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
130#define PCIMT_CSLED 0xbfda0000 130#define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
131#define PCIMT_CSMAPISA 0xbfdb0000 131#define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
132#define PCIMT_CSRSTBP 0xbfdc0000 132#define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
133#define PCIMT_CLRPOFF 0xbfdd0000 133#define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
134#define PCIMT_CSTIMER 0xbfde0000 134#define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
135#define PCIMT_PWDN 0xbfdf0000 135#define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
136 136
137/* 137/*
138 * A20R based boards 138 * A20R based boards
139 */ 139 */
140#define A20R_PT_CLOCK_BASE 0xbc040000 140#define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
141#define A20R_PT_TIM0_ACK 0xbc050000 141#define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
142#define A20R_PT_TIM1_ACK 0xbc060000 142#define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
143 143
144#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE 144#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
145#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) 145#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
146 146
147#define SNI_PCIT_INT_REG 0xbfff000c 147#define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
148 148
149#define SNI_PCIT_INT_START 24 149#define SNI_PCIT_INT_START 24
150#define SNI_PCIT_INT_END 30 150#define SNI_PCIT_INT_END 30
@@ -186,10 +186,30 @@ extern unsigned int sni_brd_type;
186/* 186/*
187 * Base address for the mapped 16mb EISA bus segment. 187 * Base address for the mapped 16mb EISA bus segment.
188 */ 188 */
189#define PCIMT_EISA_BASE 0xb0000000 189#define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
190 190
191/* PCI EISA Interrupt acknowledge */ 191/* PCI EISA Interrupt acknowledge */
192#define PCIMT_INT_ACKNOWLEDGE 0xba000000 192#define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
193
194/*
195 * SNI ID PROM
196 *
197 * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities
198 * SNI_IDPROM_BRDTYPE Board Type
199 * SNI_IDPROM_CPUTYPE CPU Type on RM400
200 */
201#ifdef CONFIG_CPU_BIG_ENDIAN
202#define __SNI_END 0
203#endif
204#ifdef CONFIG_CPU_LITTLE_ENDIAN
205#define __SNI_END 3
206#endif
207#define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)
208#define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
209#define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
210#define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
211
212#define SNI_IDPROM_SIZE 0x1000
193 213
194/* board specific init functions */ 214/* board specific init functions */
195extern void sni_a20r_init(void); 215extern void sni_a20r_init(void);
@@ -207,6 +227,9 @@ extern void sni_pcimt_irq_init(void);
207/* timer inits */ 227/* timer inits */
208extern void sni_cpu_time_init(void); 228extern void sni_cpu_time_init(void);
209 229
230/* eisa init for RM200/400 */
231extern int sni_eisa_root_init(void);
232
210/* common irq stuff */ 233/* common irq stuff */
211extern void (*sni_hwint)(void); 234extern void (*sni_hwint)(void);
212extern struct irqaction sni_isa_irq; 235extern struct irqaction sni_isa_irq;
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index fb41a8d76392..051e1af0bb95 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -6,6 +6,7 @@
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle 6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. 7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc. 8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
9 */ 10 */
10#ifndef _ASM_STACKFRAME_H 11#ifndef _ASM_STACKFRAME_H
11#define _ASM_STACKFRAME_H 12#define _ASM_STACKFRAME_H
@@ -145,8 +146,16 @@
145 .set reorder 146 .set reorder
146 /* Called from user mode, new stack. */ 147 /* Called from user mode, new stack. */
147 get_saved_sp 148 get_saved_sp
149#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
1488: move k0, sp 1508: move k0, sp
149 PTR_SUBU sp, k1, PT_SIZE 151 PTR_SUBU sp, k1, PT_SIZE
152#else
153 .set at=k0
1548: PTR_SUBU k1, PT_SIZE
155 .set noat
156 move k0, sp
157 move sp, k1
158#endif
150 LONG_S k0, PT_R29(sp) 159 LONG_S k0, PT_R29(sp)
151 LONG_S $3, PT_R3(sp) 160 LONG_S $3, PT_R3(sp)
152 /* 161 /*
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index 7717934f94c3..a8fd16e1981f 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -31,20 +31,13 @@ extern int rtc_mips_set_time(unsigned long);
31extern int rtc_mips_set_mmss(unsigned long); 31extern int rtc_mips_set_mmss(unsigned long);
32 32
33/* 33/*
34 * Timer interrupt functions.
35 * mips_timer_state is needed for high precision timer calibration.
36 */
37extern int (*mips_timer_state)(void);
38
39/*
40 * board specific routines required by time_init(). 34 * board specific routines required by time_init().
41 */ 35 */
42extern void plat_time_init(void); 36extern void plat_time_init(void);
43 37
44/* 38/*
45 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible 39 * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
46 * counter as a timer interrupt source; otherwise it can be set up 40 * counter as a timer interrupt source.
47 * automagically with an aid of mips_timer_state.
48 */ 41 */
49extern unsigned int mips_hpt_frequency; 42extern unsigned int mips_hpt_frequency;
50 43
diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h
index 0440fb9f2180..259145e07e97 100644
--- a/include/asm-mips/topology.h
+++ b/include/asm-mips/topology.h
@@ -1 +1,17 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8#ifndef __ASM_TOPOLOGY_H
9#define __ASM_TOPOLOGY_H
10
1#include <topology.h> 11#include <topology.h>
12
13#ifdef CONFIG_SMP
14#define smt_capable() (smp_num_siblings > 1)
15#endif
16
17#endif /* __ASM_TOPOLOGY_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 3f1e470192e3..0be77df70f2b 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -9,6 +9,7 @@
9#define __ASM_TX4927_TX4927_PCI_H 9#define __ASM_TX4927_TX4927_PCI_H
10 10
11#define TX4927_CCFG_TOE 0x00004000 11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_WR 0x00008000
12#define TX4927_CCFG_TINTDIS 0x01000000 13#define TX4927_CCFG_TINTDIS 0x01000000
13 14
14#define TX4927_PCIMEM 0x08000000 15#define TX4927_PCIMEM 0x08000000
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index c30c718994c9..66523d610950 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle 6 * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2007 Maciej W. Rozycki
8 */ 9 */
9#ifndef _ASM_UACCESS_H 10#ifndef _ASM_UACCESS_H
10#define _ASM_UACCESS_H 11#define _ASM_UACCESS_H
@@ -387,6 +388,12 @@ extern void __put_user_unknown(void);
387 "jal\t" #destination "\n\t" 388 "jal\t" #destination "\n\t"
388#endif 389#endif
389 390
391#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
392#define DADDI_SCRATCH "$0"
393#else
394#define DADDI_SCRATCH "$3"
395#endif
396
390extern size_t __copy_user(void *__to, const void *__from, size_t __n); 397extern size_t __copy_user(void *__to, const void *__from, size_t __n);
391 398
392#define __invoke_copy_to_user(to, from, n) \ 399#define __invoke_copy_to_user(to, from, n) \
@@ -403,7 +410,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
403 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 410 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
404 : \ 411 : \
405 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 412 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \
406 "memory"); \ 413 DADDI_SCRATCH, "memory"); \
407 __cu_len_r; \ 414 __cu_len_r; \
408}) 415})
409 416
@@ -512,7 +519,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
512 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 519 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
513 : \ 520 : \
514 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 521 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \
515 "memory"); \ 522 DADDI_SCRATCH, "memory"); \
516 __cu_len_r; \ 523 __cu_len_r; \
517}) 524})
518 525
@@ -535,7 +542,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
535 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 542 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
536 : \ 543 : \
537 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 544 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \
538 "memory"); \ 545 DADDI_SCRATCH, "memory"); \
539 __cu_len_r; \ 546 __cu_len_r; \
540}) 547})
541 548
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index d2808edfd4e9..22361d5e3bf0 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -4,6 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
7 * Copyright (C) 2007 Maciej W. Rozycki
7 */ 8 */
8#ifndef _ASM_WAR_H 9#ifndef _ASM_WAR_H
9#define _ASM_WAR_H 10#define _ASM_WAR_H
@@ -11,6 +12,67 @@
11#include <war.h> 12#include <war.h>
12 13
13/* 14/*
15 * Work around certain R4000 CPU errata (as implemented by GCC):
16 *
17 * - A double-word or a variable shift may give an incorrect result
18 * if executed immediately after starting an integer division:
19 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
20 * erratum #28
21 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
22 * #19
23 *
24 * - A double-word or a variable shift may give an incorrect result
25 * if executed while an integer multiplication is in progress:
26 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
27 * errata #16 & #28
28 *
29 * - An integer division may give an incorrect result if started in
30 * a delay slot of a taken branch or a jump:
31 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
32 * erratum #52
33 */
34#ifdef CONFIG_CPU_R4000_WORKAROUNDS
35#define R4000_WAR 1
36#else
37#define R4000_WAR 0
38#endif
39
40/*
41 * Work around certain R4400 CPU errata (as implemented by GCC):
42 *
43 * - A double-word or a variable shift may give an incorrect result
44 * if executed immediately after starting an integer division:
45 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
46 * "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
47 */
48#ifdef CONFIG_CPU_R4400_WORKAROUNDS
49#define R4400_WAR 1
50#else
51#define R4400_WAR 0
52#endif
53
54/*
55 * Work around the "daddi" and "daddiu" CPU errata:
56 *
57 * - The `daddi' instruction fails to trap on overflow.
58 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
59 * erratum #23
60 *
61 * - The `daddiu' instruction can produce an incorrect result.
62 * "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
63 * erratum #41
64 * "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
65 * #15
66 * "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
67 * "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
68 */
69#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
70#define DADDI_WAR 1
71#else
72#define DADDI_WAR 0
73#endif
74
75/*
14 * Another R4600 erratum. Due to the lack of errata information the exact 76 * Another R4600 erratum. Due to the lack of errata information the exact
15 * technical details aren't known. I've experimentally found that disabling 77 * technical details aren't known. I've experimentally found that disabling
16 * interrupts during indexed I-cache flushes seems to be sufficient to deal 78 * interrupts during indexed I-cache flushes seems to be sufficient to deal
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 02:25:59 -0500