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authorLinus Torvalds <torvalds@linux-foundation.org>2014-10-08 17:06:53 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-10-08 17:06:53 -0400
commit212fe84a6f215c39795a76517c1c02114d428681 (patch)
tree4692680312616d6a5c562f2d494c12d21b697237
parent4a4743e840d06a5772be7c21110807165c5b3c9f (diff)
parent05301fe7de11dac87638f1728f8ee8b31bc1cf31 (diff)
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Arnd Bergmann: "This time around, the cleanup branch contains mostly code removal. A number of board files for at91, imx and msm have become obsolete because of the DT conversion and are now ready to be removed. The OMAP platform has traditionally had its own DMA engine abstraction and as this is being phased out, a lot of the original code is now unused and can be removed as well. S3C24xx can be simplified now that the restart code is a proper device driver. Finally, a number of cleanups in shmobile are done to prepare for the addition of new code in other branches" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) ARM: at91: Remove the support for the RSI EWS board arm: mach-omap2: Convert pr_warning to pr_warn ARM: OMAP: Remove unused pieces of legacy DMA API ARM: at91: remove board file for Acme Systems Fox G20 ARM: orion5x: Convert pr_warning to pr_warn ARM: S3C24XX: remove separate restart code ARM: EXYNOS: Do not calculate boot address twice ARM: sunxi: Remove sun4i reboot code from mach directory ARM: imx: Remove mach-mxt_td60 board file ARM: shmobile: armadillo800eva legacy: Use rmobile_add_devices_to_domains() ARM: shmobile: r8a7740: Clean up pm domain table ARM: shmobile: r8a7740: Use rmobile_add_devices_to_domains() ARM: shmobile: sh7372: Make domain_devices[] static __initdata ARM: shmobile: mackerel: Make domain_devices[] static __initdata clocksource: tcb_clksrc: sanitize IRQ request ARM: at91/tclib: mask interruptions at shutdown and probe ARM: at91/tclib: move initialization from alloc to probe ARM: at91/tclib: prefer using of devm_* functions ARM: clps711x: Switch CLPS711X subarch to use clk and clocksource driver ARM: shmobile: r8a7791 is now called "R-Car M2-W" ...
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts1
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig5
-rw-r--r--arch/arm/mach-at91/Kconfig17
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt18
-rw-r--r--arch/arm/mach-at91/Makefile5
-rw-r--r--arch/arm/mach-at91/board-dt-rm9200.c13
-rw-r--r--arch/arm/mach-at91/board-dt-sam9.c13
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c13
-rw-r--r--arch/arm/mach-at91/board-foxg20.c272
-rw-r--r--arch/arm/mach-at91/board-rsi-ews.c232
-rw-r--r--arch/arm/mach-at91/irq.c270
-rw-r--r--arch/arm/mach-at91/pm.c32
-rw-r--r--arch/arm/mach-at91/setup.c3
-rw-r--r--arch/arm/mach-clps711x/common.c138
-rw-r--r--arch/arm/mach-clps711x/common.h5
-rw-r--r--arch/arm/mach-exynos/include/mach/memory.h26
-rw-r--r--arch/arm/mach-exynos/platsmp.c4
-rw-r--r--arch/arm/mach-imx/Kconfig103
-rw-r--r--arch/arm/mach-imx/Makefile6
-rw-r--r--arch/arm/mach-imx/board-pcm038.h36
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/cpuidle-imx6q.c4
-rw-r--r--arch/arm/mach-imx/eukrea-baseboards.h10
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c351
-rw-r--r--arch/arm/mach-imx/iomux-imx31.c7
-rw-r--r--arch/arm/mach-imx/iomux-v1.c2
-rw-r--r--arch/arm/mach-imx/iomux-v3.c2
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c321
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c154
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c273
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c358
-rw-r--r--arch/arm/mach-imx/pcm970-baseboard.c231
-rw-r--r--arch/arm/mach-imx/platsmp.c10
-rw-r--r--arch/arm/mach-msm/board-mahimahi.c83
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c2
-rw-r--r--arch/arm/mach-msm/board-trout-gpio.c2
-rw-r--r--arch/arm/mach-msm/board-trout.c2
-rw-r--r--arch/arm/mach-msm/io.c6
-rw-r--r--arch/arm/mach-omap2/display.c2
-rw-r--r--arch/arm/mach-omap2/hdq1w.c4
-rw-r--r--arch/arm/mach-omap2/i2c.c2
-rw-r--r--arch/arm/mach-omap2/msdi.c4
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c26
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c4
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--arch/arm/mach-omap2/smartreflex-class3.c4
-rw-r--r--arch/arm/mach-omap2/sr_device.c2
-rw-r--r--arch/arm/mach-omap2/vc.c2
-rw-r--r--arch/arm/mach-omap2/voltage.c22
-rw-r--r--arch/arm/mach-omap2/wd_timer.c4
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c8
-rw-r--r--arch/arm/mach-orion5x/terastation_pro2-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c2
-rw-r--r--arch/arm/mach-orion5x/ts78xx-setup.c4
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig2
-rw-r--r--arch/arm/mach-s3c24xx/common.c4
-rw-r--r--arch/arm/mach-s3c24xx/common.h5
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h2
-rw-r--r--arch/arm/mach-s3c24xx/mach-amlm5900.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-anubis.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-at2440evb.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-bast.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-gta02.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-h1940.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-mini2440.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-n30.c2
-rw-r--r--arch/arm/mach-s3c24xx/mach-nexcoder.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-osiris.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-otom.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-qt2410.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-rx1950.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-rx3715.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-s3c2416-dt.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2410.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2413.c3
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2416.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2440.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-smdk2443.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-tct_hammer.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-vr1000.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-vstms.c1
-rw-r--r--arch/arm/mach-s3c24xx/s3c2410.c13
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c23
-rw-r--r--arch/arm/mach-s3c24xx/s3c2416.c8
-rw-r--r--arch/arm/mach-s3c24xx/s3c2443.c8
-rw-r--r--arch/arm/mach-s3c24xx/s3c244x.c12
-rw-r--r--arch/arm/mach-s5pv210/pm.c3
-rw-r--r--arch/arm/mach-s5pv210/regs-clock.h (renamed from arch/arm/mach-s5pv210/include/mach/regs-clock.h)3
-rw-r--r--arch/arm/mach-s5pv210/s5pv210.c2
-rw-r--r--arch/arm/mach-shmobile/Kconfig77
-rw-r--r--arch/arm/mach-shmobile/Makefile30
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c8
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c2
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7740.c10
-rw-r--r--arch/arm/mach-shmobile/pm-rcar.c4
-rw-r--r--arch/arm/mach-shmobile/pm-rmobile.c2
-rw-r--r--arch/arm/mach-shmobile/pm-rmobile.h4
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c26
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c2
-rw-r--r--arch/arm/mach-sunxi/sunxi.c76
-rw-r--r--arch/arm/plat-omap/dma.c737
-rw-r--r--drivers/clocksource/tcb_clksrc.c15
-rw-r--r--drivers/misc/atmel_tclib.c101
-rw-r--r--drivers/pwm/pwm-atmel-tcb.c2
-rw-r--r--include/linux/atmel_tc.h13
-rw-r--r--include/linux/omap-dma.h37
110 files changed, 261 insertions, 4129 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 32cbbd565902..314bdf1163f9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -650,6 +650,7 @@ config ARCH_SHMOBILE_LEGACY
650 select ARCH_SHMOBILE 650 select ARCH_SHMOBILE
651 select ARM_PATCH_PHYS_VIRT if MMU 651 select ARM_PATCH_PHYS_VIRT if MMU
652 select CLKDEV_LOOKUP 652 select CLKDEV_LOOKUP
653 select CPU_V7
653 select GENERIC_CLOCKEVENTS 654 select GENERIC_CLOCKEVENTS
654 select HAVE_ARM_SCU if SMP 655 select HAVE_ARM_SCU if SMP
655 select HAVE_ARM_TWD if SMP 656 select HAVE_ARM_TWD if SMP
@@ -660,6 +661,7 @@ config ARCH_SHMOBILE_LEGACY
660 select NO_IOPORT_MAP 661 select NO_IOPORT_MAP
661 select PINCTRL 662 select PINCTRL
662 select PM_GENERIC_DOMAINS if PM 663 select PM_GENERIC_DOMAINS if PM
664 select SH_CLK_CPG
663 select SPARSE_IRQ 665 select SPARSE_IRQ
664 help 666 help
665 Support for Renesas ARM SoC platforms using a non-multiplatform 667 Support for Renesas ARM SoC platforms using a non-multiplatform
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index b8a5e8c68f06..e4bffbae515f 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -76,7 +76,6 @@
76 76
77 simple-audio-card,cpu { 77 simple-audio-card,cpu {
78 sound-dai = <&sai2>; 78 sound-dai = <&sai2>;
79 master-clkdir-out;
80 frame-master; 79 frame-master;
81 bitclock-master; 80 bitclock-master;
82 }; 81 };
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 63bde0efc041..a3fb8662ff6c 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -22,7 +22,6 @@ CONFIG_ARCH_MULTI_V5=y
22# CONFIG_ARCH_MULTI_V7 is not set 22# CONFIG_ARCH_MULTI_V7 is not set
23CONFIG_ARCH_MXC=y 23CONFIG_ARCH_MXC=y
24CONFIG_MXC_IRQ_PRIOR=y 24CONFIG_MXC_IRQ_PRIOR=y
25CONFIG_ARCH_MX1ADS=y
26CONFIG_MACH_SCB9328=y 25CONFIG_MACH_SCB9328=y
27CONFIG_MACH_APF9328=y 26CONFIG_MACH_APF9328=y
28CONFIG_MACH_MX21ADS=y 27CONFIG_MACH_MX21ADS=y
@@ -30,10 +29,6 @@ CONFIG_MACH_MX25_3DS=y
30CONFIG_MACH_EUKREA_CPUIMX25SD=y 29CONFIG_MACH_EUKREA_CPUIMX25SD=y
31CONFIG_MACH_IMX25_DT=y 30CONFIG_MACH_IMX25_DT=y
32CONFIG_MACH_MX27ADS=y 31CONFIG_MACH_MX27ADS=y
33CONFIG_MACH_PCM038=y
34CONFIG_MACH_CPUIMX27=y
35CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
36CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
37CONFIG_MACH_MX27_3DS=y 32CONFIG_MACH_MX27_3DS=y
38CONFIG_MACH_IMX27_VISSTRIM_M10=y 33CONFIG_MACH_IMX27_VISSTRIM_M10=y
39CONFIG_MACH_PCA100=y 34CONFIG_MACH_PCA100=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6cc6f7aebdae..dd28e1fedbdc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -28,6 +28,11 @@ config OLD_CLK_AT91
28 bool 28 bool
29 default AT91_PMC_UNIT && AT91_USE_OLD_CLK 29 default AT91_PMC_UNIT && AT91_USE_OLD_CLK
30 30
31config OLD_IRQ_AT91
32 bool
33 select MULTI_IRQ_HANDLER
34 select SPARSE_IRQ
35
31config AT91_SAM9_ALT_RESET 36config AT91_SAM9_ALT_RESET
32 bool 37 bool
33 default !ARCH_AT91X40 38 default !ARCH_AT91X40
@@ -45,18 +50,16 @@ config HAVE_AT91_SMD
45config SOC_AT91SAM9 50config SOC_AT91SAM9
46 bool 51 bool
47 select AT91_SAM9_TIME 52 select AT91_SAM9_TIME
53 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
48 select CPU_ARM926T 54 select CPU_ARM926T
49 select GENERIC_CLOCKEVENTS 55 select GENERIC_CLOCKEVENTS
50 select MULTI_IRQ_HANDLER
51 select SPARSE_IRQ
52 56
53config SOC_SAMA5 57config SOC_SAMA5
54 bool 58 bool
55 select AT91_SAM9_TIME 59 select AT91_SAM9_TIME
60 select ATMEL_AIC5_IRQ
56 select CPU_V7 61 select CPU_V7
57 select GENERIC_CLOCKEVENTS 62 select GENERIC_CLOCKEVENTS
58 select MULTI_IRQ_HANDLER
59 select SPARSE_IRQ
60 select USE_OF 63 select USE_OF
61 64
62menu "Atmel AT91 System-on-Chip" 65menu "Atmel AT91 System-on-Chip"
@@ -70,8 +73,7 @@ config ARCH_AT91X40
70 depends on !MMU 73 depends on !MMU
71 select CPU_ARM7TDMI 74 select CPU_ARM7TDMI
72 select ARCH_USES_GETTIMEOFFSET 75 select ARCH_USES_GETTIMEOFFSET
73 select MULTI_IRQ_HANDLER 76 select OLD_IRQ_AT91
74 select SPARSE_IRQ
75 77
76 help 78 help
77 Select this if you are using one of Atmel's AT91X40 SoC. 79 Select this if you are using one of Atmel's AT91X40 SoC.
@@ -108,11 +110,10 @@ endif
108if SOC_SAM_V4_V5 110if SOC_SAM_V4_V5
109config SOC_AT91RM9200 111config SOC_AT91RM9200
110 bool "AT91RM9200" 112 bool "AT91RM9200"
113 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
111 select CPU_ARM920T 114 select CPU_ARM920T
112 select GENERIC_CLOCKEVENTS 115 select GENERIC_CLOCKEVENTS
113 select HAVE_AT91_DBGU0 116 select HAVE_AT91_DBGU0
114 select MULTI_IRQ_HANDLER
115 select SPARSE_IRQ
116 select HAVE_AT91_USB_CLK 117 select HAVE_AT91_USB_CLK
117 118
118config SOC_AT91SAM9260 119config SOC_AT91SAM9260
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 44ace320d2e1..d8e88219edb4 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,31 +14,37 @@ config ARCH_AT91RM9200
14 bool "AT91RM9200" 14 bool "AT91RM9200"
15 select SOC_AT91RM9200 15 select SOC_AT91RM9200
16 select AT91_USE_OLD_CLK 16 select AT91_USE_OLD_CLK
17 select OLD_IRQ_AT91
17 18
18config ARCH_AT91SAM9260 19config ARCH_AT91SAM9260
19 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" 20 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
20 select SOC_AT91SAM9260 21 select SOC_AT91SAM9260
21 select AT91_USE_OLD_CLK 22 select AT91_USE_OLD_CLK
23 select OLD_IRQ_AT91
22 24
23config ARCH_AT91SAM9261 25config ARCH_AT91SAM9261
24 bool "AT91SAM9261 or AT91SAM9G10" 26 bool "AT91SAM9261 or AT91SAM9G10"
25 select SOC_AT91SAM9261 27 select SOC_AT91SAM9261
26 select AT91_USE_OLD_CLK 28 select AT91_USE_OLD_CLK
29 select OLD_IRQ_AT91
27 30
28config ARCH_AT91SAM9263 31config ARCH_AT91SAM9263
29 bool "AT91SAM9263" 32 bool "AT91SAM9263"
30 select SOC_AT91SAM9263 33 select SOC_AT91SAM9263
31 select AT91_USE_OLD_CLK 34 select AT91_USE_OLD_CLK
35 select OLD_IRQ_AT91
32 36
33config ARCH_AT91SAM9RL 37config ARCH_AT91SAM9RL
34 bool "AT91SAM9RL" 38 bool "AT91SAM9RL"
35 select SOC_AT91SAM9RL 39 select SOC_AT91SAM9RL
36 select AT91_USE_OLD_CLK 40 select AT91_USE_OLD_CLK
41 select OLD_IRQ_AT91
37 42
38config ARCH_AT91SAM9G45 43config ARCH_AT91SAM9G45
39 bool "AT91SAM9G45" 44 bool "AT91SAM9G45"
40 select SOC_AT91SAM9G45 45 select SOC_AT91SAM9G45
41 select AT91_USE_OLD_CLK 46 select AT91_USE_OLD_CLK
47 select OLD_IRQ_AT91
42 48
43endchoice 49endchoice
44 50
@@ -132,12 +138,6 @@ config MACH_ECO920
132 bool "eco920" 138 bool "eco920"
133 help 139 help
134 Select this if you are using the eco920 board 140 Select this if you are using the eco920 board
135
136config MACH_RSI_EWS
137 bool "RSI Embedded Webserver"
138 depends on ARCH_AT91RM9200
139 help
140 Select this if you are using RSIs EWS board.
141endif 141endif
142 142
143# ---------------------------------------------------------- 143# ----------------------------------------------------------
@@ -212,12 +212,6 @@ config MACH_CPU9G20
212 Select this if you are using a Eukrea Electromatique's 212 Select this if you are using a Eukrea Electromatique's
213 CPU9G20 Board <http://www.eukrea.com/> 213 CPU9G20 Board <http://www.eukrea.com/>
214 214
215config MACH_ACMENETUSFOXG20
216 bool "Acme Systems srl FOX Board G20"
217 help
218 Select this if you are using Acme Systems
219 FOX Board G20 <http://www.acmesystems.it>
220
221config MACH_PORTUXG20 215config MACH_PORTUXG20
222 bool "taskit PortuxG20" 216 bool "taskit PortuxG20"
223 help 217 help
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 78e9cec282f4..40946f4e8921 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,11 +2,12 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o gpio.o setup.o sysirq_mask.o 5obj-y := gpio.o setup.o sysirq_mask.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
10obj-$(CONFIG_OLD_CLK_AT91) += clock.o 11obj-$(CONFIG_OLD_CLK_AT91) += clock.o
11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o 12obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o 13obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
@@ -46,7 +47,6 @@ obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
46obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o 47obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
47obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o 48obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
48obj-$(CONFIG_MACH_ECO920) += board-eco920.o 49obj-$(CONFIG_MACH_ECO920) += board-eco920.o
49obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o
50 50
51# AT91SAM9260 board-specific support 51# AT91SAM9260 board-specific support
52obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o 52obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -69,7 +69,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
69# AT91SAM9G20 board-specific support 69# AT91SAM9G20 board-specific support
70obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 70obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
71obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 71obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
72obj-$(CONFIG_MACH_ACMENETUSFOXG20) += board-foxg20.o
73obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 72obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
74obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 73obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
75obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o 74obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index f4b6e91843e4..226563f850b8 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -25,17 +25,6 @@
25#include "at91_aic.h" 25#include "at91_aic.h"
26#include "generic.h" 26#include "generic.h"
27 27
28
29static const struct of_device_id irq_of_match[] __initconst = {
30 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
31 { /*sentinel*/ }
32};
33
34static void __init at91rm9200_dt_init_irq(void)
35{
36 of_irq_init(irq_of_match);
37}
38
39static void __init at91rm9200_dt_timer_init(void) 28static void __init at91rm9200_dt_timer_init(void)
40{ 29{
41#if defined(CONFIG_COMMON_CLK) 30#if defined(CONFIG_COMMON_CLK)
@@ -52,8 +41,6 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
52DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)") 41DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
53 .init_time = at91rm9200_dt_timer_init, 42 .init_time = at91rm9200_dt_timer_init,
54 .map_io = at91_map_io, 43 .map_io = at91_map_io,
55 .handle_irq = at91_aic_handle_irq,
56 .init_early = at91rm9200_dt_initialize, 44 .init_early = at91rm9200_dt_initialize,
57 .init_irq = at91rm9200_dt_init_irq,
58 .dt_compat = at91rm9200_dt_board_compat, 45 .dt_compat = at91rm9200_dt_board_compat,
59MACHINE_END 46MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 575b0be66ca8..dfa8d48146fe 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -34,17 +34,6 @@ static void __init sam9_dt_timer_init(void)
34 at91sam926x_pit_init(); 34 at91sam926x_pit_init();
35} 35}
36 36
37static const struct of_device_id irq_of_match[] __initconst = {
38
39 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
40 { /*sentinel*/ }
41};
42
43static void __init at91_dt_init_irq(void)
44{
45 of_irq_init(irq_of_match);
46}
47
48static const char *at91_dt_board_compat[] __initdata = { 37static const char *at91_dt_board_compat[] __initdata = {
49 "atmel,at91sam9", 38 "atmel,at91sam9",
50 NULL 39 NULL
@@ -54,8 +43,6 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
54 /* Maintainer: Atmel */ 43 /* Maintainer: Atmel */
55 .init_time = sam9_dt_timer_init, 44 .init_time = sam9_dt_timer_init,
56 .map_io = at91_map_io, 45 .map_io = at91_map_io,
57 .handle_irq = at91_aic_handle_irq,
58 .init_early = at91_dt_initialize, 46 .init_early = at91_dt_initialize,
59 .init_irq = at91_dt_init_irq,
60 .dt_compat = at91_dt_board_compat, 47 .dt_compat = at91_dt_board_compat,
61MACHINE_END 48MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 075ec0576ada..d6fe04bcaabd 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -35,17 +35,6 @@ static void __init sama5_dt_timer_init(void)
35 at91sam926x_pit_init(); 35 at91sam926x_pit_init();
36} 36}
37 37
38static const struct of_device_id irq_of_match[] __initconst = {
39
40 { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
41 { /*sentinel*/ }
42};
43
44static void __init at91_dt_init_irq(void)
45{
46 of_irq_init(irq_of_match);
47}
48
49static int ksz9021rn_phy_fixup(struct phy_device *phy) 38static int ksz9021rn_phy_fixup(struct phy_device *phy)
50{ 39{
51 int value; 40 int value;
@@ -82,9 +71,7 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
82 /* Maintainer: Atmel */ 71 /* Maintainer: Atmel */
83 .init_time = sama5_dt_timer_init, 72 .init_time = sama5_dt_timer_init,
84 .map_io = at91_map_io, 73 .map_io = at91_map_io,
85 .handle_irq = at91_aic5_handle_irq,
86 .init_early = at91_dt_initialize, 74 .init_early = at91_dt_initialize,
87 .init_irq = at91_dt_init_irq,
88 .init_machine = sama5_dt_device_init, 75 .init_machine = sama5_dt_device_init,
89 .dt_compat = sama5_dt_board_compat, 76 .dt_compat = sama5_dt_board_compat,
90MACHINE_END 77MACHINE_END
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
deleted file mode 100644
index 8b22c60bb238..000000000000
--- a/arch/arm/mach-at91/board-foxg20.c
+++ /dev/null
@@ -1,272 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2008 Atmel
4 * Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com
5 * Copyright (C) 2010 Sergio Tanzilli - tanzilli@acmesystems.it
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/at73c213.h>
29#include <linux/gpio.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/clk.h>
33#include <linux/w1-gpio.h>
34
35#include <mach/hardware.h>
36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/irq.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43
44#include <mach/at91sam9_smc.h>
45
46#include "at91_aic.h"
47#include "board.h"
48#include "sam9_smc.h"
49#include "generic.h"
50#include "gpio.h"
51
52/*
53 * The FOX Board G20 hardware comes as the "Netus G20" board with
54 * just the cpu, ram, dataflash and two header connectors.
55 * This is plugged into the FOX Board which provides the ethernet,
56 * usb, rtc, leds, switch, ...
57 *
58 * For more info visit: http://www.acmesystems.it/foxg20
59 */
60
61
62static void __init foxg20_init_early(void)
63{
64 /* Initialize processor: 18.432 MHz crystal */
65 at91_initialize(18432000);
66}
67
68/*
69 * USB Host port
70 */
71static struct at91_usbh_data __initdata foxg20_usbh_data = {
72 .ports = 2,
73 .vbus_pin = {-EINVAL, -EINVAL},
74 .overcurrent_pin= {-EINVAL, -EINVAL},
75};
76
77/*
78 * USB Device port
79 */
80static struct at91_udc_data __initdata foxg20_udc_data = {
81 .vbus_pin = AT91_PIN_PC6,
82 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
83};
84
85
86/*
87 * SPI devices.
88 */
89static struct spi_board_info foxg20_spi_devices[] = {
90#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
91 {
92 .modalias = "mtd_dataflash",
93 .chip_select = 1,
94 .max_speed_hz = 15 * 1000 * 1000,
95 .bus_num = 0,
96 },
97#endif
98};
99
100
101/*
102 * MACB Ethernet device
103 */
104static struct macb_platform_data __initdata foxg20_macb_data = {
105 .phy_irq_pin = AT91_PIN_PA7,
106 .is_rmii = 1,
107};
108
109/*
110 * MCI (SD/MMC)
111 * det_pin, wp_pin and vcc_pin are not connected
112 */
113static struct mci_platform_data __initdata foxg20_mci0_data = {
114 .slot[1] = {
115 .bus_width = 4,
116 .detect_pin = -EINVAL,
117 .wp_pin = -EINVAL,
118 },
119};
120
121
122/*
123 * LEDs
124 */
125static struct gpio_led foxg20_leds[] = {
126 { /* user led, red */
127 .name = "user_led",
128 .gpio = AT91_PIN_PC7,
129 .active_low = 0,
130 .default_trigger = "heartbeat",
131 },
132};
133
134
135/*
136 * GPIO Buttons
137 */
138#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
139static struct gpio_keys_button foxg20_buttons[] = {
140 {
141 .gpio = AT91_PIN_PC4,
142 .code = BTN_1,
143 .desc = "Button 1",
144 .active_low = 1,
145 .wakeup = 1,
146 },
147};
148
149static struct gpio_keys_platform_data foxg20_button_data = {
150 .buttons = foxg20_buttons,
151 .nbuttons = ARRAY_SIZE(foxg20_buttons),
152};
153
154static struct platform_device foxg20_button_device = {
155 .name = "gpio-keys",
156 .id = -1,
157 .num_resources = 0,
158 .dev = {
159 .platform_data = &foxg20_button_data,
160 }
161};
162
163static void __init foxg20_add_device_buttons(void)
164{
165 at91_set_gpio_input(AT91_PIN_PC4, 1); /* btn1 */
166 at91_set_deglitch(AT91_PIN_PC4, 1);
167
168 platform_device_register(&foxg20_button_device);
169}
170#else
171static void __init foxg20_add_device_buttons(void) {}
172#endif
173
174
175#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
176static struct w1_gpio_platform_data w1_gpio_pdata = {
177 /* If you choose to use a pin other than PB16 it needs to be 3.3V */
178 .pin = AT91_PIN_PB16,
179 .is_open_drain = 1,
180 .ext_pullup_enable_pin = -EINVAL,
181};
182
183static struct platform_device w1_device = {
184 .name = "w1-gpio",
185 .id = -1,
186 .dev.platform_data = &w1_gpio_pdata,
187};
188
189static void __init at91_add_device_w1(void)
190{
191 at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
192 at91_set_multi_drive(w1_gpio_pdata.pin, 1);
193 platform_device_register(&w1_device);
194}
195
196#endif
197
198
199static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
200 {
201 I2C_BOARD_INFO("24c512", 0x50),
202 },
203};
204
205
206static void __init foxg20_board_init(void)
207{
208 /* Serial */
209 /* DBGU on ttyS0. (Rx & Tx only) */
210 at91_register_uart(0, 0, 0);
211
212 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
213 at91_register_uart(AT91SAM9260_ID_US0, 1,
214 ATMEL_UART_CTS
215 | ATMEL_UART_RTS
216 | ATMEL_UART_DTR
217 | ATMEL_UART_DSR
218 | ATMEL_UART_DCD
219 | ATMEL_UART_RI);
220
221 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
222 at91_register_uart(AT91SAM9260_ID_US1, 2,
223 ATMEL_UART_CTS
224 | ATMEL_UART_RTS);
225
226 /* USART2 on ttyS3. (Rx & Tx only) */
227 at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
228
229 /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
230 at91_register_uart(AT91SAM9260_ID_US3, 4,
231 ATMEL_UART_CTS
232 | ATMEL_UART_RTS);
233
234 /* USART4 on ttyS5. (Rx & Tx only) */
235 at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
236
237 /* USART5 on ttyS6. (Rx & Tx only) */
238 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
239
240 /* Set the internal pull-up resistor on DRXD */
241 at91_set_A_periph(AT91_PIN_PB14, 1);
242 at91_add_device_serial();
243 /* USB Host */
244 at91_add_device_usbh(&foxg20_usbh_data);
245 /* USB Device */
246 at91_add_device_udc(&foxg20_udc_data);
247 /* SPI */
248 at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices));
249 /* Ethernet */
250 at91_add_device_eth(&foxg20_macb_data);
251 /* MMC */
252 at91_add_device_mci(0, &foxg20_mci0_data);
253 /* I2C */
254 at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices));
255 /* LEDs */
256 at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds));
257 /* Push Buttons */
258 foxg20_add_device_buttons();
259#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
260 at91_add_device_w1();
261#endif
262}
263
264MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
265 /* Maintainer: Sergio Tanzilli */
266 .init_time = at91sam926x_pit_init,
267 .map_io = at91_map_io,
268 .handle_irq = at91_aic_handle_irq,
269 .init_early = foxg20_init_early,
270 .init_irq = at91_init_irq_default,
271 .init_machine = foxg20_board_init,
272MACHINE_END
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
deleted file mode 100644
index f28e8b74df4b..000000000000
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ /dev/null
@@ -1,232 +0,0 @@
1/*
2 * board-rsi-ews.c
3 *
4 * Copyright (C)
5 * 2005 SAN People,
6 * 2008-2011 R-S-I Elektrotechnik GmbH & Co. KG
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/mtd/physmap.h>
18
19#include <asm/setup.h>
20#include <asm/mach-types.h>
21#include <asm/irq.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <mach/hardware.h>
28
29#include <linux/gpio.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "generic.h"
34#include "gpio.h"
35
36static void __init rsi_ews_init_early(void)
37{
38 /* Initialize processor: 18.432 MHz crystal */
39 at91_initialize(18432000);
40}
41
42/*
43 * Ethernet
44 */
45static struct macb_platform_data rsi_ews_eth_data __initdata = {
46 .phy_irq_pin = AT91_PIN_PC4,
47 .is_rmii = 1,
48};
49
50/*
51 * USB Host
52 */
53static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
54 .ports = 1,
55 .vbus_pin = {-EINVAL, -EINVAL},
56 .overcurrent_pin= {-EINVAL, -EINVAL},
57};
58
59/*
60 * SD/MC
61 */
62static struct mci_platform_data __initdata rsi_ews_mci0_data = {
63 .slot[0] = {
64 .bus_width = 4,
65 .detect_pin = AT91_PIN_PB27,
66 .wp_pin = AT91_PIN_PB29,
67 },
68};
69
70/*
71 * I2C
72 */
73static struct i2c_board_info rsi_ews_i2c_devices[] __initdata = {
74 {
75 I2C_BOARD_INFO("ds1337", 0x68),
76 },
77 {
78 I2C_BOARD_INFO("24c01", 0x50),
79 }
80};
81
82/*
83 * LEDs
84 */
85static struct gpio_led rsi_ews_leds[] = {
86 {
87 .name = "led0",
88 .gpio = AT91_PIN_PB6,
89 .active_low = 0,
90 },
91 {
92 .name = "led1",
93 .gpio = AT91_PIN_PB7,
94 .active_low = 0,
95 },
96 {
97 .name = "led2",
98 .gpio = AT91_PIN_PB8,
99 .active_low = 0,
100 },
101 {
102 .name = "led3",
103 .gpio = AT91_PIN_PB9,
104 .active_low = 0,
105 },
106};
107
108/*
109 * DataFlash
110 */
111static struct spi_board_info rsi_ews_spi_devices[] = {
112 { /* DataFlash chip 1*/
113 .modalias = "mtd_dataflash",
114 .chip_select = 0,
115 .max_speed_hz = 5 * 1000 * 1000,
116 },
117 { /* DataFlash chip 2*/
118 .modalias = "mtd_dataflash",
119 .chip_select = 1,
120 .max_speed_hz = 5 * 1000 * 1000,
121 },
122};
123
124/*
125 * NOR flash
126 */
127static struct mtd_partition rsiews_nor_partitions[] = {
128 {
129 .name = "boot",
130 .offset = 0,
131 .size = 3 * SZ_128K,
132 .mask_flags = MTD_WRITEABLE
133 },
134 {
135 .name = "kernel",
136 .offset = MTDPART_OFS_NXTBLK,
137 .size = SZ_2M - (3 * SZ_128K)
138 },
139 {
140 .name = "root",
141 .offset = MTDPART_OFS_NXTBLK,
142 .size = SZ_8M
143 },
144 {
145 .name = "kernelupd",
146 .offset = MTDPART_OFS_NXTBLK,
147 .size = 3 * SZ_512K,
148 .mask_flags = MTD_WRITEABLE
149 },
150 {
151 .name = "rootupd",
152 .offset = MTDPART_OFS_NXTBLK,
153 .size = 9 * SZ_512K,
154 .mask_flags = MTD_WRITEABLE
155 },
156};
157
158static struct physmap_flash_data rsiews_nor_data = {
159 .width = 2,
160 .parts = rsiews_nor_partitions,
161 .nr_parts = ARRAY_SIZE(rsiews_nor_partitions),
162};
163
164#define NOR_BASE AT91_CHIPSELECT_0
165#define NOR_SIZE SZ_16M
166
167static struct resource nor_flash_resources[] = {
168 {
169 .start = NOR_BASE,
170 .end = NOR_BASE + NOR_SIZE - 1,
171 .flags = IORESOURCE_MEM,
172 }
173};
174
175static struct platform_device rsiews_nor_flash = {
176 .name = "physmap-flash",
177 .id = 0,
178 .dev = {
179 .platform_data = &rsiews_nor_data,
180 },
181 .resource = nor_flash_resources,
182 .num_resources = ARRAY_SIZE(nor_flash_resources),
183};
184
185/*
186 * Init Func
187 */
188static void __init rsi_ews_board_init(void)
189{
190 /* Serial */
191 /* DBGU on ttyS0. (Rx & Tx only) */
192 /* This one is for debugging */
193 at91_register_uart(0, 0, 0);
194
195 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
196 /* Dialin/-out modem interface */
197 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
198 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
199 | ATMEL_UART_RI);
200
201 /* USART3 on ttyS4. (Rx, Tx, RTS) */
202 /* RS485 communication */
203 at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
204 at91_add_device_serial();
205 at91_set_gpio_output(AT91_PIN_PA21, 0);
206 /* Ethernet */
207 at91_add_device_eth(&rsi_ews_eth_data);
208 /* USB Host */
209 at91_add_device_usbh(&rsi_ews_usbh_data);
210 /* I2C */
211 at91_add_device_i2c(rsi_ews_i2c_devices,
212 ARRAY_SIZE(rsi_ews_i2c_devices));
213 /* SPI */
214 at91_add_device_spi(rsi_ews_spi_devices,
215 ARRAY_SIZE(rsi_ews_spi_devices));
216 /* MMC */
217 at91_add_device_mci(0, &rsi_ews_mci0_data);
218 /* NOR Flash */
219 platform_device_register(&rsiews_nor_flash);
220 /* LEDs */
221 at91_gpio_leds(rsi_ews_leds, ARRAY_SIZE(rsi_ews_leds));
222}
223
224MACHINE_START(RSI_EWS, "RSI EWS")
225 /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
226 .init_time = at91rm9200_timer_init,
227 .map_io = at91_map_io,
228 .handle_irq = at91_aic_handle_irq,
229 .init_early = rsi_ews_init_early,
230 .init_irq = at91_init_irq_default,
231 .init_machine = rsi_ews_board_init,
232MACHINE_END
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 3d192c5aee66..cdb3ec9efd2b 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -48,11 +48,6 @@ void __iomem *at91_aic_base;
48static struct irq_domain *at91_aic_domain; 48static struct irq_domain *at91_aic_domain;
49static struct device_node *at91_aic_np; 49static struct device_node *at91_aic_np;
50static unsigned int n_irqs = NR_AIC_IRQS; 50static unsigned int n_irqs = NR_AIC_IRQS;
51static unsigned long at91_aic_caps = 0;
52
53/* AIC5 introduces a Source Select Register */
54#define AT91_AIC_CAP_AIC5 (1 << 0)
55#define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5)
56 51
57#ifdef CONFIG_PM 52#ifdef CONFIG_PM
58 53
@@ -92,50 +87,14 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
92 87
93void at91_irq_suspend(void) 88void at91_irq_suspend(void)
94{ 89{
95 int bit = -1; 90 at91_aic_write(AT91_AIC_IDCR, *backups);
96 91 at91_aic_write(AT91_AIC_IECR, *wakeups);
97 if (has_aic5()) {
98 /* disable enabled irqs */
99 while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
100 at91_aic_write(AT91_AIC5_SSR,
101 bit & AT91_AIC5_INTSEL_MSK);
102 at91_aic_write(AT91_AIC5_IDCR, 1);
103 }
104 /* enable wakeup irqs */
105 bit = -1;
106 while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
107 at91_aic_write(AT91_AIC5_SSR,
108 bit & AT91_AIC5_INTSEL_MSK);
109 at91_aic_write(AT91_AIC5_IECR, 1);
110 }
111 } else {
112 at91_aic_write(AT91_AIC_IDCR, *backups);
113 at91_aic_write(AT91_AIC_IECR, *wakeups);
114 }
115} 92}
116 93
117void at91_irq_resume(void) 94void at91_irq_resume(void)
118{ 95{
119 int bit = -1; 96 at91_aic_write(AT91_AIC_IDCR, *wakeups);
120 97 at91_aic_write(AT91_AIC_IECR, *backups);
121 if (has_aic5()) {
122 /* disable wakeup irqs */
123 while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
124 at91_aic_write(AT91_AIC5_SSR,
125 bit & AT91_AIC5_INTSEL_MSK);
126 at91_aic_write(AT91_AIC5_IDCR, 1);
127 }
128 /* enable irqs disabled for suspend */
129 bit = -1;
130 while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
131 at91_aic_write(AT91_AIC5_SSR,
132 bit & AT91_AIC5_INTSEL_MSK);
133 at91_aic_write(AT91_AIC5_IECR, 1);
134 }
135 } else {
136 at91_aic_write(AT91_AIC_IDCR, *wakeups);
137 at91_aic_write(AT91_AIC_IECR, *backups);
138 }
139} 98}
140 99
141#else 100#else
@@ -169,21 +128,6 @@ at91_aic_handle_irq(struct pt_regs *regs)
169 handle_IRQ(irqnr, regs); 128 handle_IRQ(irqnr, regs);
170} 129}
171 130
172asmlinkage void __exception_irq_entry
173at91_aic5_handle_irq(struct pt_regs *regs)
174{
175 u32 irqnr;
176 u32 irqstat;
177
178 irqnr = at91_aic_read(AT91_AIC5_IVR);
179 irqstat = at91_aic_read(AT91_AIC5_ISR);
180
181 if (!irqstat)
182 at91_aic_write(AT91_AIC5_EOICR, 0);
183 else
184 handle_IRQ(irqnr, regs);
185}
186
187static void at91_aic_mask_irq(struct irq_data *d) 131static void at91_aic_mask_irq(struct irq_data *d)
188{ 132{
189 /* Disable interrupt on AIC */ 133 /* Disable interrupt on AIC */
@@ -192,15 +136,6 @@ static void at91_aic_mask_irq(struct irq_data *d)
192 clear_backup(d->hwirq); 136 clear_backup(d->hwirq);
193} 137}
194 138
195static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
196{
197 /* Disable interrupt on AIC5 */
198 at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
199 at91_aic_write(AT91_AIC5_IDCR, 1);
200 /* Update ISR cache */
201 clear_backup(d->hwirq);
202}
203
204static void at91_aic_unmask_irq(struct irq_data *d) 139static void at91_aic_unmask_irq(struct irq_data *d)
205{ 140{
206 /* Enable interrupt on AIC */ 141 /* Enable interrupt on AIC */
@@ -209,15 +144,6 @@ static void at91_aic_unmask_irq(struct irq_data *d)
209 set_backup(d->hwirq); 144 set_backup(d->hwirq);
210} 145}
211 146
212static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
213{
214 /* Enable interrupt on AIC5 */
215 at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
216 at91_aic_write(AT91_AIC5_IECR, 1);
217 /* Update ISR cache */
218 set_backup(d->hwirq);
219}
220
221static void at91_aic_eoi(struct irq_data *d) 147static void at91_aic_eoi(struct irq_data *d)
222{ 148{
223 /* 149 /*
@@ -227,11 +153,6 @@ static void at91_aic_eoi(struct irq_data *d)
227 at91_aic_write(AT91_AIC_EOICR, 0); 153 at91_aic_write(AT91_AIC_EOICR, 0);
228} 154}
229 155
230static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
231{
232 at91_aic_write(AT91_AIC5_EOICR, 0);
233}
234
235static unsigned long *at91_extern_irq; 156static unsigned long *at91_extern_irq;
236 157
237u32 at91_get_extern_irq(void) 158u32 at91_get_extern_irq(void)
@@ -282,16 +203,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
282 if (srctype < 0) 203 if (srctype < 0)
283 return srctype; 204 return srctype;
284 205
285 if (has_aic5()) { 206 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
286 at91_aic_write(AT91_AIC5_SSR, 207 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
287 d->hwirq & AT91_AIC5_INTSEL_MSK);
288 smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
289 at91_aic_write(AT91_AIC5_SMR, smr | srctype);
290 } else {
291 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
292 & ~AT91_AIC_SRCTYPE;
293 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
294 }
295 208
296 return 0; 209 return 0;
297} 210}
@@ -331,177 +244,6 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
331 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); 244 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
332} 245}
333 246
334static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
335{
336 int i;
337
338 /*
339 * Perform 8 End Of Interrupt Command to make sure AIC
340 * will not Lock out nIRQ
341 */
342 for (i = 0; i < 8; i++)
343 at91_aic_write(AT91_AIC5_EOICR, 0);
344
345 /*
346 * Spurious Interrupt ID in Spurious Vector Register.
347 * When there is no current interrupt, the IRQ Vector Register
348 * reads the value stored in AIC_SPU
349 */
350 at91_aic_write(AT91_AIC5_SPU, spu_vector);
351
352 /* No debugging in AIC: Debug (Protect) Control Register */
353 at91_aic_write(AT91_AIC5_DCR, 0);
354
355 /* Disable and clear all interrupts initially */
356 for (i = 0; i < n_irqs; i++) {
357 at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
358 at91_aic_write(AT91_AIC5_IDCR, 1);
359 at91_aic_write(AT91_AIC5_ICCR, 1);
360 }
361}
362
363#if defined(CONFIG_OF)
364static unsigned int *at91_aic_irq_priorities;
365
366static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
367 irq_hw_number_t hw)
368{
369 /* Put virq number in Source Vector Register */
370 at91_aic_write(AT91_AIC_SVR(hw), virq);
371
372 /* Active Low interrupt, with priority */
373 at91_aic_write(AT91_AIC_SMR(hw),
374 AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
375
376 irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
377 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
378
379 return 0;
380}
381
382static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
383 irq_hw_number_t hw)
384{
385 at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
386
387 /* Put virq number in Source Vector Register */
388 at91_aic_write(AT91_AIC5_SVR, virq);
389
390 /* Active Low interrupt, with priority */
391 at91_aic_write(AT91_AIC5_SMR,
392 AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
393
394 irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
395 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
396
397 return 0;
398}
399
400static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
401 const u32 *intspec, unsigned int intsize,
402 irq_hw_number_t *out_hwirq, unsigned int *out_type)
403{
404 if (WARN_ON(intsize < 3))
405 return -EINVAL;
406 if (WARN_ON(intspec[0] >= n_irqs))
407 return -EINVAL;
408 if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
409 || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
410 return -EINVAL;
411
412 *out_hwirq = intspec[0];
413 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
414 at91_aic_irq_priorities[*out_hwirq] = intspec[2];
415
416 return 0;
417}
418
419static struct irq_domain_ops at91_aic_irq_ops = {
420 .map = at91_aic_irq_map,
421 .xlate = at91_aic_irq_domain_xlate,
422};
423
424int __init at91_aic_of_common_init(struct device_node *node,
425 struct device_node *parent)
426{
427 struct property *prop;
428 const __be32 *p;
429 u32 val;
430
431 at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
432 * sizeof(*at91_extern_irq), GFP_KERNEL);
433 if (!at91_extern_irq)
434 return -ENOMEM;
435
436 if (at91_aic_pm_init()) {
437 kfree(at91_extern_irq);
438 return -ENOMEM;
439 }
440
441 at91_aic_irq_priorities = kzalloc(n_irqs
442 * sizeof(*at91_aic_irq_priorities),
443 GFP_KERNEL);
444 if (!at91_aic_irq_priorities)
445 return -ENOMEM;
446
447 at91_aic_base = of_iomap(node, 0);
448 at91_aic_np = node;
449
450 at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
451 &at91_aic_irq_ops, NULL);
452 if (!at91_aic_domain)
453 panic("Unable to add AIC irq domain (DT)\n");
454
455 of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
456 if (val >= n_irqs)
457 pr_warn("AIC: external irq %d >= %d skip it\n",
458 val, n_irqs);
459 else
460 set_bit(val, at91_extern_irq);
461 }
462
463 irq_set_default_host(at91_aic_domain);
464
465 return 0;
466}
467
468int __init at91_aic_of_init(struct device_node *node,
469 struct device_node *parent)
470{
471 int err;
472
473 err = at91_aic_of_common_init(node, parent);
474 if (err)
475 return err;
476
477 at91_aic_hw_init(n_irqs);
478
479 return 0;
480}
481
482int __init at91_aic5_of_init(struct device_node *node,
483 struct device_node *parent)
484{
485 int err;
486
487 at91_aic_caps |= AT91_AIC_CAP_AIC5;
488 n_irqs = NR_AIC5_IRQS;
489 at91_aic_chip.irq_ack = at91_aic5_mask_irq;
490 at91_aic_chip.irq_mask = at91_aic5_mask_irq;
491 at91_aic_chip.irq_unmask = at91_aic5_unmask_irq;
492 at91_aic_chip.irq_eoi = at91_aic5_eoi;
493 at91_aic_irq_ops.map = at91_aic5_irq_map;
494
495 err = at91_aic_of_common_init(node, parent);
496 if (err)
497 return err;
498
499 at91_aic5_hw_init(n_irqs);
500
501 return 0;
502}
503#endif
504
505/* 247/*
506 * Initialize the AIC interrupt controller. 248 * Initialize the AIC interrupt controller.
507 */ 249 */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e95554532987..5920373809c5 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -206,16 +206,19 @@ static int at91_pm_enter(suspend_state_t state)
206 at91_pinctrl_gpio_suspend(); 206 at91_pinctrl_gpio_suspend();
207 else 207 else
208 at91_gpio_suspend(); 208 at91_gpio_suspend();
209 at91_irq_suspend();
210 209
211 pr_debug("AT91: PM - wake mask %08x, pm state %d\n", 210 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
212 /* remember all the always-wake irqs */ 211 at91_irq_suspend();
213 (at91_pmc_read(AT91_PMC_PCSR) 212
214 | (1 << AT91_ID_FIQ) 213 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
215 | (1 << AT91_ID_SYS) 214 /* remember all the always-wake irqs */
216 | (at91_get_extern_irq())) 215 (at91_pmc_read(AT91_PMC_PCSR)
217 & at91_aic_read(AT91_AIC_IMR), 216 | (1 << AT91_ID_FIQ)
218 state); 217 | (1 << AT91_ID_SYS)
218 | (at91_get_extern_irq()))
219 & at91_aic_read(AT91_AIC_IMR),
220 state);
221 }
219 222
220 switch (state) { 223 switch (state) {
221 /* 224 /*
@@ -280,12 +283,17 @@ static int at91_pm_enter(suspend_state_t state)
280 goto error; 283 goto error;
281 } 284 }
282 285
283 pr_debug("AT91: PM - wakeup %08x\n", 286 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
284 at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); 287 pr_debug("AT91: PM - wakeup %08x\n",
288 at91_aic_read(AT91_AIC_IPR) &
289 at91_aic_read(AT91_AIC_IMR));
285 290
286error: 291error:
287 target_state = PM_SUSPEND_ON; 292 target_state = PM_SUSPEND_ON;
288 at91_irq_resume(); 293
294 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
295 at91_irq_resume();
296
289 if (of_have_populated_dt()) 297 if (of_have_populated_dt())
290 at91_pinctrl_gpio_resume(); 298 at91_pinctrl_gpio_resume();
291 else 299 else
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f7a07a58ebb6..0bf893a574f9 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -49,7 +49,8 @@ void __init at91_init_irq_default(void)
49void __init at91_init_interrupts(unsigned int *priority) 49void __init at91_init_interrupts(unsigned int *priority)
50{ 50{
51 /* Initialize the AIC interrupt controller */ 51 /* Initialize the AIC interrupt controller */
52 at91_aic_init(priority, at91_boot_soc.extern_irq); 52 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
53 at91_aic_init(priority, at91_boot_soc.extern_irq);
53 54
54 /* Enable GPIO interrupts */ 55 /* Enable GPIO interrupts */
55 at91_gpio_irq_setup(); 56 at91_gpio_irq_setup();
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 2a6323b15782..671acc5a3282 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -19,29 +19,17 @@
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */ 21 */
22#include <linux/io.h> 22
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/sizes.h> 24#include <linux/sizes.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/clk.h>
28#include <linux/clkdev.h>
29#include <linux/clockchips.h>
30#include <linux/clocksource.h>
31#include <linux/clk-provider.h>
32#include <linux/sched_clock.h>
33 25
34#include <asm/mach/map.h> 26#include <asm/mach/map.h>
35#include <asm/mach/time.h>
36#include <asm/system_misc.h> 27#include <asm/system_misc.h>
37 28
38#include <mach/hardware.h> 29#include <mach/hardware.h>
39 30
40#include "common.h" 31#include "common.h"
41 32
42static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
43 *clk_tint, *clk_spi;
44
45/* 33/*
46 * This maps the generic CLPS711x registers 34 * This maps the generic CLPS711x registers
47 */ 35 */
@@ -64,129 +52,11 @@ void __init clps711x_init_irq(void)
64 clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K); 52 clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
65} 53}
66 54
67static u64 notrace clps711x_sched_clock_read(void)
68{
69 return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
70}
71
72static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
73 struct clock_event_device *evt)
74{
75 disable_irq(IRQ_TC2OI);
76
77 switch (mode) {
78 case CLOCK_EVT_MODE_PERIODIC:
79 enable_irq(IRQ_TC2OI);
80 break;
81 case CLOCK_EVT_MODE_ONESHOT:
82 /* Not supported */
83 case CLOCK_EVT_MODE_SHUTDOWN:
84 case CLOCK_EVT_MODE_UNUSED:
85 case CLOCK_EVT_MODE_RESUME:
86 /* Left event sources disabled, no more interrupts appear */
87 break;
88 }
89}
90
91static struct clock_event_device clockevent_clps711x = {
92 .name = "clps711x-clockevent",
93 .rating = 300,
94 .features = CLOCK_EVT_FEAT_PERIODIC,
95 .set_mode = clps711x_clockevent_set_mode,
96};
97
98static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
99{
100 clockevent_clps711x.event_handler(&clockevent_clps711x);
101
102 return IRQ_HANDLED;
103}
104
105static struct irqaction clps711x_timer_irq = {
106 .name = "clps711x-timer",
107 .flags = IRQF_TIMER | IRQF_IRQPOLL,
108 .handler = clps711x_timer_interrupt,
109};
110
111static void add_fixed_clk(struct clk *clk, const char *name, int rate)
112{
113 clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
114 clk_register_clkdev(clk, name, NULL);
115}
116
117void __init clps711x_timer_init(void) 55void __init clps711x_timer_init(void)
118{ 56{
119 int osc, ext, pll, cpu, bus, timl, timh, uart, spi; 57 clps711x_clk_init(CLPS711X_VIRT_BASE);
120 u32 tmp; 58 clps711x_clksrc_init(CLPS711X_VIRT_BASE + TC1D,
121 59 CLPS711X_VIRT_BASE + TC2D, IRQ_TC2OI);
122 osc = 3686400;
123 ext = 13000000;
124
125 tmp = clps_readl(PLLR) >> 24;
126 if (tmp)
127 pll = (osc * tmp) / 2;
128 else
129 pll = 73728000; /* Default value */
130
131 tmp = clps_readl(SYSFLG2);
132 if (tmp & SYSFLG2_CKMODE) {
133 cpu = ext;
134 bus = cpu;
135 spi = 135400;
136 pll = 0;
137 } else {
138 cpu = pll;
139 if (cpu >= 36864000)
140 bus = cpu / 2;
141 else
142 bus = 36864000 / 2;
143 spi = cpu / 576;
144 }
145
146 uart = bus / 10;
147
148 if (tmp & SYSFLG2_CKMODE) {
149 tmp = clps_readl(SYSCON2);
150 if (tmp & SYSCON2_OSTB)
151 timh = ext / 26;
152 else
153 timh = 541440;
154 } else
155 timh = DIV_ROUND_CLOSEST(cpu, 144);
156
157 timl = DIV_ROUND_CLOSEST(timh, 256);
158
159 /* All clocks are fixed */
160 add_fixed_clk(clk_pll, "pll", pll);
161 add_fixed_clk(clk_bus, "bus", bus);
162 add_fixed_clk(clk_uart, "uart", uart);
163 add_fixed_clk(clk_timerl, "timer_lf", timl);
164 add_fixed_clk(clk_timerh, "timer_hf", timh);
165 add_fixed_clk(clk_tint, "tint", 64);
166 add_fixed_clk(clk_spi, "spi", spi);
167
168 pr_info("CPU frequency set at %i Hz.\n", cpu);
169
170 /* Start Timer1 in free running mode (Low frequency) */
171 tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
172 clps_writel(tmp, SYSCON1);
173
174 sched_clock_register(clps711x_sched_clock_read, 16, timl);
175
176 clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
177 "clps711x_clocksource", timl, 300, 16,
178 clocksource_mmio_readw_down);
179
180 /* Set Timer2 prescaler */
181 clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
182
183 /* Start Timer2 in prescale mode (High frequency)*/
184 tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
185 clps_writel(tmp, SYSCON1);
186
187 clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
188
189 setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
190} 60}
191 61
192void clps711x_restart(enum reboot_mode mode, const char *cmd) 62void clps711x_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f88189963898..370200b26333 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -16,3 +16,8 @@ extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
16 16
17/* drivers/irqchip/irq-clps711x.c */ 17/* drivers/irqchip/irq-clps711x.c */
18void clps711x_intc_init(phys_addr_t, resource_size_t); 18void clps711x_intc_init(phys_addr_t, resource_size_t);
19/* drivers/clk/clk-clps711x.c */
20void clps711x_clk_init(void __iomem *base);
21/* drivers/clocksource/clps711x-timer.c */
22void clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
23 unsigned int irq);
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h
deleted file mode 100644
index e19df1f18c0d..000000000000
--- a/arch/arm/mach-exynos/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4 - Memory definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H __FILE__
14
15#define PLAT_PHYS_OFFSET UL(0x40000000)
16
17#ifndef CONFIG_ARM_LPAE
18/* Maximum of 256MiB in one bank */
19#define MAX_PHYSMEM_BITS 32
20#define SECTION_SIZE_BITS 28
21#else
22#define MAX_PHYSMEM_BITS 36
23#define SECTION_SIZE_BITS 31
24#endif
25
26#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a9f1cf759949..41ae28d69e6f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -224,7 +224,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
224 ret = PTR_ERR(boot_reg); 224 ret = PTR_ERR(boot_reg);
225 goto fail; 225 goto fail;
226 } 226 }
227 __raw_writel(boot_addr, cpu_boot_reg(core_id)); 227 __raw_writel(boot_addr, boot_reg);
228 } 228 }
229 229
230 call_firmware_op(cpu_boot, core_id); 230 call_firmware_op(cpu_boot, core_id);
@@ -313,7 +313,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
313 313
314 if (IS_ERR(boot_reg)) 314 if (IS_ERR(boot_reg))
315 break; 315 break;
316 __raw_writel(boot_addr, cpu_boot_reg(core_id)); 316 __raw_writel(boot_addr, boot_reg);
317 } 317 }
318 } 318 }
319} 319}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index be9a51afe05a..4e9b4f63d42b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -108,17 +108,6 @@ config SOC_IMX35
108if ARCH_MULTI_V4T 108if ARCH_MULTI_V4T
109 109
110comment "MX1 platforms:" 110comment "MX1 platforms:"
111config MACH_MXLADS
112 bool
113
114config ARCH_MX1ADS
115 bool "MX1ADS platform"
116 select IMX_HAVE_PLATFORM_IMX_I2C
117 select IMX_HAVE_PLATFORM_IMX_UART
118 select MACH_MXLADS
119 select SOC_IMX1
120 help
121 Say Y here if you are using Motorola MX1ADS/MXLADS boards
122 111
123config MACH_SCB9328 112config MACH_SCB9328
124 bool "Synertronixx scb9328" 113 bool "Synertronixx scb9328"
@@ -223,86 +212,6 @@ config MACH_MX27ADS
223 Include support for MX27ADS platform. This includes specific 212 Include support for MX27ADS platform. This includes specific
224 configurations for the board and its peripherals. 213 configurations for the board and its peripherals.
225 214
226config MACH_PCM038
227 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
228 select IMX_HAVE_PLATFORM_IMX2_WDT
229 select IMX_HAVE_PLATFORM_IMX_I2C
230 select IMX_HAVE_PLATFORM_IMX_UART
231 select IMX_HAVE_PLATFORM_MXC_EHCI
232 select IMX_HAVE_PLATFORM_MXC_NAND
233 select IMX_HAVE_PLATFORM_MXC_W1
234 select IMX_HAVE_PLATFORM_SPI_IMX
235 select USB_ULPI_VIEWPORT if USB_ULPI
236 select SOC_IMX27
237 help
238 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
239 includes specific configurations for the module and its peripherals.
240
241choice
242 prompt "Baseboard"
243 depends on MACH_PCM038
244 default MACH_PCM970_BASEBOARD
245
246config MACH_PCM970_BASEBOARD
247 bool "PHYTEC PCM970 development board"
248 select IMX_HAVE_PLATFORM_IMX_FB
249 select IMX_HAVE_PLATFORM_MXC_MMC
250 help
251 This adds board specific devices that can be found on Phytec's
252 PCM970 evaluation board.
253
254endchoice
255
256config MACH_CPUIMX27
257 bool "Eukrea CPUIMX27 module"
258 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
259 select IMX_HAVE_PLATFORM_IMX2_WDT
260 select IMX_HAVE_PLATFORM_IMX_I2C
261 select IMX_HAVE_PLATFORM_IMX_UART
262 select IMX_HAVE_PLATFORM_MXC_EHCI
263 select IMX_HAVE_PLATFORM_MXC_NAND
264 select IMX_HAVE_PLATFORM_MXC_W1
265 select USB_ULPI_VIEWPORT if USB_ULPI
266 select SOC_IMX27
267 help
268 Include support for Eukrea CPUIMX27 platform. This includes
269 specific configurations for the module and its peripherals.
270
271config MACH_EUKREA_CPUIMX27_USESDHC2
272 bool "CPUIMX27 integrates SDHC2 module"
273 depends on MACH_CPUIMX27
274 select IMX_HAVE_PLATFORM_MXC_MMC
275 help
276 This adds support for the internal SDHC2 used on CPUIMX27
277 for wifi or eMMC.
278
279config MACH_EUKREA_CPUIMX27_USEUART4
280 bool "CPUIMX27 integrates UART4 module"
281 depends on MACH_CPUIMX27
282 help
283 This adds support for the internal UART4 used on CPUIMX27
284 for bluetooth.
285
286choice
287 prompt "Baseboard"
288 depends on MACH_CPUIMX27
289 default MACH_EUKREA_MBIMX27_BASEBOARD
290
291config MACH_EUKREA_MBIMX27_BASEBOARD
292 bool "Eukrea MBIMX27 development board"
293 select IMX_HAVE_PLATFORM_IMX_FB
294 select IMX_HAVE_PLATFORM_IMX_KEYPAD
295 select IMX_HAVE_PLATFORM_IMX_SSI
296 select IMX_HAVE_PLATFORM_IMX_UART
297 select IMX_HAVE_PLATFORM_MXC_MMC
298 select IMX_HAVE_PLATFORM_SPI_IMX
299 select LEDS_GPIO_REGISTER
300 help
301 This adds board specific devices that can be found on Eukrea's
302 MBIMX27 evaluation board.
303
304endchoice
305
306config MACH_MX27_3DS 215config MACH_MX27_3DS
307 bool "MX27PDK platform" 216 bool "MX27PDK platform"
308 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 217 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
@@ -359,18 +268,6 @@ config MACH_PCA100
359 Include support for phyCARD-s (aka pca100) platform. This 268 Include support for phyCARD-s (aka pca100) platform. This
360 includes specific configurations for the module and its peripherals. 269 includes specific configurations for the module and its peripherals.
361 270
362config MACH_MXT_TD60
363 bool "Maxtrack i-MXT TD60"
364 select IMX_HAVE_PLATFORM_IMX_FB
365 select IMX_HAVE_PLATFORM_IMX_I2C
366 select IMX_HAVE_PLATFORM_IMX_UART
367 select IMX_HAVE_PLATFORM_MXC_MMC
368 select IMX_HAVE_PLATFORM_MXC_NAND
369 select SOC_IMX27
370 help
371 Include support for i-MXT (aka td60) platform. This
372 includes specific configurations for the module and its peripherals.
373
374config MACH_IMX27_DT 271config MACH_IMX27_DT
375 bool "Support i.MX27 platforms from device tree" 272 bool "Support i.MX27 platforms from device tree"
376 select SOC_IMX27 273 select SOC_IMX27
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 23c02932bf84..4147729775d2 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -41,7 +41,6 @@ obj-y += ssi-fiq-ksym.o
41endif 41endif
42 42
43# i.MX1 based machines 43# i.MX1 based machines
44obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
45obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o 44obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
46obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o 45obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
47 46
@@ -56,14 +55,9 @@ obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o
56 55
57# i.MX27 based machines 56# i.MX27 based machines
58obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 57obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
59obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
60obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
61obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o 58obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
62obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o 59obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
63obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
64obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
65obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 60obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
66obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
67obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o 61obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
68 62
69# i.MX31 based machines 63# i.MX31 based machines
diff --git a/arch/arm/mach-imx/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h
deleted file mode 100644
index 6f371e35753d..000000000000
--- a/arch/arm/mach-imx/board-pcm038.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21
22#ifndef __ASSEMBLY__
23/*
24 * This CPU module needs a baseboard to work. After basic initializing
25 * its own devices, it calls the baseboard's init function.
26 * TODO: Add your own baseboard init function and call it from
27 * inside pcm038_init().
28 *
29 * This example here is for the development board. Refer pcm970-baseboard.c
30 */
31
32extern void pcm970_baseboard_init(void);
33
34#endif
35
36#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 22ba8973bcb9..1dabf435c592 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -98,11 +98,9 @@ void imx_set_cpu_arg(int cpu, u32 arg);
98void v7_secondary_startup(void); 98void v7_secondary_startup(void);
99void imx_scu_map_io(void); 99void imx_scu_map_io(void);
100void imx_smp_prepare(void); 100void imx_smp_prepare(void);
101void imx_scu_standby_enable(void);
102#else 101#else
103static inline void imx_scu_map_io(void) {} 102static inline void imx_scu_map_io(void) {}
104static inline void imx_smp_prepare(void) {} 103static inline void imx_smp_prepare(void) {}
105static inline void imx_scu_standby_enable(void) {}
106#endif 104#endif
107void imx_src_init(void); 105void imx_src_init(void);
108void imx_gpc_init(void); 106void imx_gpc_init(void);
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 10844d3bb926..aa935787b743 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -66,10 +66,6 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
66 66
67int __init imx6q_cpuidle_init(void) 67int __init imx6q_cpuidle_init(void)
68{ 68{
69 /* Need to enable SCU standby for entering WAIT modes */
70 if (!cpu_is_imx6sx())
71 imx_scu_standby_enable();
72
73 /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ 69 /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
74 imx6q_set_int_mem_clk_lpm(true); 70 imx6q_set_int_mem_clk_lpm(true);
75 71
diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h
index a21d3313f994..bb2c90d65914 100644
--- a/arch/arm/mach-imx/eukrea-baseboards.h
+++ b/arch/arm/mach-imx/eukrea-baseboards.h
@@ -27,23 +27,15 @@
27 * This CPU module needs a baseboard to work. After basic initializing 27 * This CPU module needs a baseboard to work. After basic initializing
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() 30 * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init()
31 * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
32 * or eukrea_cpuimx51sd_init().
33 * 31 *
34 * This example here is for the development board. Refer 32 * This example here is for the development board. Refer
35 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 33 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
36 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
37 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 34 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
38 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
39 * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
40 */ 35 */
41 36
42extern void eukrea_mbimxsd25_baseboard_init(void); 37extern void eukrea_mbimxsd25_baseboard_init(void);
43extern void eukrea_mbimx27_baseboard_init(void);
44extern void eukrea_mbimxsd35_baseboard_init(void); 38extern void eukrea_mbimxsd35_baseboard_init(void);
45extern void eukrea_mbimx51_baseboard_init(void);
46extern void eukrea_mbimxsd51_baseboard_init(void);
47 39
48#endif 40#endif
49 41
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
deleted file mode 100644
index b2f08bfbbdd3..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ /dev/null
@@ -1,351 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/gpio.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h>
27#include <linux/backlight.h>
28#include <video/platform_lcd.h>
29
30#include <asm/mach/arch.h>
31
32#include "common.h"
33#include "devices-imx27.h"
34#include "hardware.h"
35#include "iomux-mx27.h"
36
37static const int eukrea_mbimx27_pins[] __initconst = {
38 /* UART2 */
39 PE3_PF_UART2_CTS,
40 PE4_PF_UART2_RTS,
41 PE6_PF_UART2_TXD,
42 PE7_PF_UART2_RXD,
43 /* UART3 */
44 PE8_PF_UART3_TXD,
45 PE9_PF_UART3_RXD,
46 PE10_PF_UART3_CTS,
47 PE11_PF_UART3_RTS,
48 /* UART4 */
49#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
50 PB26_AF_UART4_RTS,
51 PB28_AF_UART4_TXD,
52 PB29_AF_UART4_CTS,
53 PB31_AF_UART4_RXD,
54#endif
55 /* SDHC1*/
56 PE18_PF_SD1_D0,
57 PE19_PF_SD1_D1,
58 PE20_PF_SD1_D2,
59 PE21_PF_SD1_D3,
60 PE22_PF_SD1_CMD,
61 PE23_PF_SD1_CLK,
62 /* display */
63 PA5_PF_LSCLK,
64 PA6_PF_LD0,
65 PA7_PF_LD1,
66 PA8_PF_LD2,
67 PA9_PF_LD3,
68 PA10_PF_LD4,
69 PA11_PF_LD5,
70 PA12_PF_LD6,
71 PA13_PF_LD7,
72 PA14_PF_LD8,
73 PA15_PF_LD9,
74 PA16_PF_LD10,
75 PA17_PF_LD11,
76 PA18_PF_LD12,
77 PA19_PF_LD13,
78 PA20_PF_LD14,
79 PA21_PF_LD15,
80 PA22_PF_LD16,
81 PA23_PF_LD17,
82 PA28_PF_HSYNC,
83 PA29_PF_VSYNC,
84 PA30_PF_CONTRAST,
85 PA31_PF_OE_ACD,
86 /* SPI1 */
87 PD29_PF_CSPI1_SCLK,
88 PD30_PF_CSPI1_MISO,
89 PD31_PF_CSPI1_MOSI,
90 /* SSI4 */
91#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
92 || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
93 PC16_PF_SSI4_FS,
94 PC17_PF_SSI4_RXD | GPIO_PUEN,
95 PC18_PF_SSI4_TXD | GPIO_PUEN,
96 PC19_PF_SSI4_CLK,
97#endif
98};
99
100static const uint32_t eukrea_mbimx27_keymap[] = {
101 KEY(0, 0, KEY_UP),
102 KEY(0, 1, KEY_DOWN),
103 KEY(1, 0, KEY_RIGHT),
104 KEY(1, 1, KEY_LEFT),
105};
106
107static const struct matrix_keymap_data
108eukrea_mbimx27_keymap_data __initconst = {
109 .keymap = eukrea_mbimx27_keymap,
110 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
111};
112
113static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = {
114 {
115 .name = "led1",
116 .default_trigger = "heartbeat",
117 .active_low = 1,
118 .gpio = GPIO_PORTF | 16,
119 },
120 {
121 .name = "led2",
122 .default_trigger = "none",
123 .active_low = 1,
124 .gpio = GPIO_PORTF | 19,
125 },
126};
127
128static const struct gpio_led_platform_data
129 eukrea_mbimx27_gpio_led_info __initconst = {
130 .leds = eukrea_mbimx27_gpio_leds,
131 .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds),
132};
133
134static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
135 {
136 .mode = {
137 .name = "CMO-QVGA",
138 .refresh = 60,
139 .xres = 320,
140 .yres = 240,
141 .pixclock = 156000,
142 .hsync_len = 30,
143 .left_margin = 38,
144 .right_margin = 20,
145 .vsync_len = 3,
146 .upper_margin = 15,
147 .lower_margin = 4,
148 },
149 .pcr = 0xFAD08B80,
150 .bpp = 16,
151 }, {
152 .mode = {
153 .name = "DVI-VGA",
154 .refresh = 60,
155 .xres = 640,
156 .yres = 480,
157 .pixclock = 32000,
158 .hsync_len = 1,
159 .left_margin = 35,
160 .right_margin = 0,
161 .vsync_len = 1,
162 .upper_margin = 7,
163 .lower_margin = 0,
164 },
165 .pcr = 0xFA208B80,
166 .bpp = 16,
167 }, {
168 .mode = {
169 .name = "DVI-SVGA",
170 .refresh = 60,
171 .xres = 800,
172 .yres = 600,
173 .pixclock = 25000,
174 .hsync_len = 1,
175 .left_margin = 35,
176 .right_margin = 0,
177 .vsync_len = 1,
178 .upper_margin = 7,
179 .lower_margin = 0,
180 },
181 .pcr = 0xFA208B80,
182 .bpp = 16,
183 },
184};
185
186static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
187 .mode = eukrea_mbimx27_modes,
188 .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
189
190 .pwmr = 0x00A903FF,
191 .lscr1 = 0x00120300,
192 .dmacr = 0x00040060,
193};
194
195static void eukrea_mbimx27_bl_set_intensity(int intensity)
196{
197 if (intensity)
198 gpio_direction_output(GPIO_PORTE | 5, 1);
199 else
200 gpio_direction_output(GPIO_PORTE | 5, 0);
201}
202
203static struct generic_bl_info eukrea_mbimx27_bl_info = {
204 .name = "eukrea_mbimx27-bl",
205 .max_intensity = 0xff,
206 .default_intensity = 0xff,
207 .set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
208};
209
210static struct platform_device eukrea_mbimx27_bl_dev = {
211 .name = "generic-bl",
212 .id = 1,
213 .dev = {
214 .platform_data = &eukrea_mbimx27_bl_info,
215 },
216};
217
218static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
219 unsigned int power)
220{
221 if (power)
222 gpio_direction_output(GPIO_PORTA | 25, 1);
223 else
224 gpio_direction_output(GPIO_PORTA | 25, 0);
225}
226
227static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
228 .set_power = eukrea_mbimx27_lcd_power_set,
229};
230
231static struct platform_device eukrea_mbimx27_lcd_powerdev = {
232 .name = "platform-lcd",
233 .dev.platform_data = &eukrea_mbimx27_lcd_power_data,
234};
235
236static const struct imxuart_platform_data uart_pdata __initconst = {
237 .flags = IMXUART_HAVE_RTSCTS,
238};
239
240#define ADS7846_PENDOWN (GPIO_PORTD | 25)
241
242static void __maybe_unused ads7846_dev_init(void)
243{
244 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
245 printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
246 return;
247 }
248 gpio_direction_input(ADS7846_PENDOWN);
249}
250
251static int ads7846_get_pendown_state(void)
252{
253 return !gpio_get_value(ADS7846_PENDOWN);
254}
255
256static struct ads7846_platform_data ads7846_config __initdata = {
257 .get_pendown_state = ads7846_get_pendown_state,
258 .keep_vref_on = 1,
259};
260
261static struct spi_board_info __maybe_unused
262 eukrea_mbimx27_spi_board_info[] __initdata = {
263 [0] = {
264 .modalias = "ads7846",
265 .bus_num = 0,
266 .chip_select = 0,
267 .max_speed_hz = 1500000,
268 /* irq number is run-time assigned */
269 .platform_data = &ads7846_config,
270 .mode = SPI_MODE_2,
271 },
272};
273
274static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
275
276static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
277 .chipselect = eukrea_mbimx27_spi_cs,
278 .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
279};
280
281static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
282 {
283 I2C_BOARD_INFO("tlv320aic23", 0x1a),
284 },
285};
286
287static const struct imxmmc_platform_data sdhc_pdata __initconst = {
288 .dat3_card_detect = 1,
289};
290
291static const
292struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
293 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
294};
295
296/*
297 * system init for baseboard usage. Will be called by cpuimx27 init.
298 *
299 * Add platform devices present on this baseboard and init
300 * them from CPU side as far as required to use them later on
301 */
302void __init eukrea_mbimx27_baseboard_init(void)
303{
304 mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
305 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
306
307 imx27_add_imx_uart1(&uart_pdata);
308 imx27_add_imx_uart2(&uart_pdata);
309#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
310 imx27_add_imx_uart3(&uart_pdata);
311#endif
312
313 imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
314 imx27_add_mxc_mmc(0, &sdhc_pdata);
315
316 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
317 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
318
319 imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
320
321#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
322 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
323 /* ADS7846 Touchscreen controller init */
324 mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
325 ads7846_dev_init();
326#endif
327
328 /* SPI_CS0 init */
329 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
330 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
331 eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
332 spi_register_board_info(eukrea_mbimx27_spi_board_info,
333 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
334
335 /* Leds configuration */
336 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
337 mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
338 /* Backlight */
339 mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
340 gpio_request(GPIO_PORTE | 5, "backlight");
341 platform_device_register(&eukrea_mbimx27_bl_dev);
342 /* LCD Reset */
343 mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
344 gpio_request(GPIO_PORTA | 25, "lcd_enable");
345 platform_device_register(&eukrea_mbimx27_lcd_powerdev);
346
347 imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
348
349 gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
350 imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
351}
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index 7c66805d2cc0..1657fe64cd0f 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -64,7 +64,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
64 64
65 return ret; 65 return ret;
66} 66}
67EXPORT_SYMBOL(mxc_iomux_mode);
68 67
69/* 68/*
70 * This function configures the pad value for a IOMUX pin. 69 * This function configures the pad value for a IOMUX pin.
@@ -90,7 +89,6 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
90 89
91 spin_unlock(&gpio_mux_lock); 90 spin_unlock(&gpio_mux_lock);
92} 91}
93EXPORT_SYMBOL(mxc_iomux_set_pad);
94 92
95/* 93/*
96 * allocs a single pin: 94 * allocs a single pin:
@@ -116,7 +114,6 @@ int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
116 114
117 return 0; 115 return 0;
118} 116}
119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
120 117
121int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, 118int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
122 const char *label) 119 const char *label)
@@ -137,7 +134,6 @@ setup_error:
137 mxc_iomux_release_multiple_pins(pin_list, i); 134 mxc_iomux_release_multiple_pins(pin_list, i);
138 return ret; 135 return ret;
139} 136}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141 137
142void mxc_iomux_release_pin(unsigned int pin) 138void mxc_iomux_release_pin(unsigned int pin)
143{ 139{
@@ -146,7 +142,6 @@ void mxc_iomux_release_pin(unsigned int pin)
146 if (pad < (PIN_MAX + 1)) 142 if (pad < (PIN_MAX + 1))
147 clear_bit(pad, mxc_pin_alloc_map); 143 clear_bit(pad, mxc_pin_alloc_map);
148} 144}
149EXPORT_SYMBOL(mxc_iomux_release_pin);
150 145
151void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) 146void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
152{ 147{
@@ -158,7 +153,6 @@ void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
158 p++; 153 p++;
159 } 154 }
160} 155}
161EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
162 156
163/* 157/*
164 * This function enables/disables the general purpose function for a particular 158 * This function enables/disables the general purpose function for a particular
@@ -178,4 +172,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
178 __raw_writel(l, IOMUXGPR); 172 __raw_writel(l, IOMUXGPR);
179 spin_unlock(&gpio_mux_lock); 173 spin_unlock(&gpio_mux_lock);
180} 174}
181EXPORT_SYMBOL(mxc_iomux_set_gpr);
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
index 2b156d1d9e21..ecd543664644 100644
--- a/arch/arm/mach-imx/iomux-v1.c
+++ b/arch/arm/mach-imx/iomux-v1.c
@@ -153,7 +153,6 @@ int mxc_gpio_mode(int gpio_mode)
153 153
154 return 0; 154 return 0;
155} 155}
156EXPORT_SYMBOL(mxc_gpio_mode);
157 156
158static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) 157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
159{ 158{
@@ -178,7 +177,6 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
178 ret = imx_iomuxv1_setup_multiple(pin_list, count); 177 ret = imx_iomuxv1_setup_multiple(pin_list, count);
179 return ret; 178 return ret;
180} 179}
181EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
182 180
183int __init imx_iomuxv1_init(void __iomem *base, int numports) 181int __init imx_iomuxv1_init(void __iomem *base, int numports)
184{ 182{
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
index 9dae74bf47fc..d61f9606fc56 100644
--- a/arch/arm/mach-imx/iomux-v3.c
+++ b/arch/arm/mach-imx/iomux-v3.c
@@ -55,7 +55,6 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
55 55
56 return 0; 56 return 0;
57} 57}
58EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
59 58
60int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) 59int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
61{ 60{
@@ -71,7 +70,6 @@ int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
71 } 70 }
72 return 0; 71 return 0;
73} 72}
74EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
75 73
76void mxc_iomux_v3_init(void __iomem *iomux_v3_base) 74void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
77{ 75{
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
deleted file mode 100644
index e6d4b9929571..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ /dev/null
@@ -1,321 +0,0 @@
1/*
2 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm038.c which is :
5 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
6 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/mtd/plat-ram.h>
26#include <linux/mtd/physmap.h>
27#include <linux/platform_device.h>
28#include <linux/serial_8250.h>
29#include <linux/usb/otg.h>
30#include <linux/usb/ulpi.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35#include <asm/mach/map.h>
36
37#include "common.h"
38#include "devices-imx27.h"
39#include "ehci.h"
40#include "eukrea-baseboards.h"
41#include "hardware.h"
42#include "iomux-mx27.h"
43#include "ulpi.h"
44
45static const int eukrea_cpuimx27_pins[] __initconst = {
46 /* UART1 */
47 PE12_PF_UART1_TXD,
48 PE13_PF_UART1_RXD,
49 PE14_PF_UART1_CTS,
50 PE15_PF_UART1_RTS,
51 /* UART4 */
52#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
53 PB26_AF_UART4_RTS,
54 PB28_AF_UART4_TXD,
55 PB29_AF_UART4_CTS,
56 PB31_AF_UART4_RXD,
57#endif
58 /* FEC */
59 PD0_AIN_FEC_TXD0,
60 PD1_AIN_FEC_TXD1,
61 PD2_AIN_FEC_TXD2,
62 PD3_AIN_FEC_TXD3,
63 PD4_AOUT_FEC_RX_ER,
64 PD5_AOUT_FEC_RXD1,
65 PD6_AOUT_FEC_RXD2,
66 PD7_AOUT_FEC_RXD3,
67 PD8_AF_FEC_MDIO,
68 PD9_AIN_FEC_MDC,
69 PD10_AOUT_FEC_CRS,
70 PD11_AOUT_FEC_TX_CLK,
71 PD12_AOUT_FEC_RXD0,
72 PD13_AOUT_FEC_RX_DV,
73 PD14_AOUT_FEC_RX_CLK,
74 PD15_AOUT_FEC_COL,
75 PD16_AIN_FEC_TX_ER,
76 PF23_AIN_FEC_TX_EN,
77 /* I2C1 */
78 PD17_PF_I2C_DATA,
79 PD18_PF_I2C_CLK,
80 /* SDHC2 */
81#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
82 PB4_PF_SD2_D0,
83 PB5_PF_SD2_D1,
84 PB6_PF_SD2_D2,
85 PB7_PF_SD2_D3,
86 PB8_PF_SD2_CMD,
87 PB9_PF_SD2_CLK,
88#endif
89#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
90 /* Quad UART's IRQ */
91 GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
92 GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
93 GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
94 GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
95#endif
96 /* OTG */
97 PC7_PF_USBOTG_DATA5,
98 PC8_PF_USBOTG_DATA6,
99 PC9_PF_USBOTG_DATA0,
100 PC10_PF_USBOTG_DATA2,
101 PC11_PF_USBOTG_DATA1,
102 PC12_PF_USBOTG_DATA4,
103 PC13_PF_USBOTG_DATA3,
104 PE0_PF_USBOTG_NXT,
105 PE1_PF_USBOTG_STP,
106 PE2_PF_USBOTG_DIR,
107 PE24_PF_USBOTG_CLK,
108 PE25_PF_USBOTG_DATA7,
109 /* USBH2 */
110 PA0_PF_USBH2_CLK,
111 PA1_PF_USBH2_DIR,
112 PA2_PF_USBH2_DATA7,
113 PA3_PF_USBH2_NXT,
114 PA4_PF_USBH2_STP,
115 PD19_AF_USBH2_DATA4,
116 PD20_AF_USBH2_DATA3,
117 PD21_AF_USBH2_DATA6,
118 PD22_AF_USBH2_DATA0,
119 PD23_AF_USBH2_DATA2,
120 PD24_AF_USBH2_DATA1,
121 PD26_AF_USBH2_DATA5,
122};
123
124static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
125 .width = 2,
126};
127
128static struct resource eukrea_cpuimx27_flash_resource = {
129 .start = 0xc0000000,
130 .end = 0xc3ffffff,
131 .flags = IORESOURCE_MEM,
132};
133
134static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
135 .name = "physmap-flash",
136 .id = 0,
137 .dev = {
138 .platform_data = &eukrea_cpuimx27_flash_data,
139 },
140 .num_resources = 1,
141 .resource = &eukrea_cpuimx27_flash_resource,
142};
143
144static const struct imxuart_platform_data uart_pdata __initconst = {
145 .flags = IMXUART_HAVE_RTSCTS,
146};
147
148static const struct mxc_nand_platform_data
149cpuimx27_nand_board_info __initconst = {
150 .width = 1,
151 .hw_ecc = 1,
152};
153
154static struct platform_device *platform_devices[] __initdata = {
155 &eukrea_cpuimx27_nor_mtd_device,
156};
157
158static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
159 .bitrate = 100000,
160};
161
162static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
163 {
164 I2C_BOARD_INFO("pcf8563", 0x51),
165 },
166};
167
168#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
169static struct plat_serial8250_port serial_platform_data[] = {
170 {
171 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
172 /* irq number is run-time assigned */
173 .uartclk = 14745600,
174 .regshift = 1,
175 .iotype = UPIO_MEM,
176 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
177 }, {
178 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
179 /* irq number is run-time assigned */
180 .uartclk = 14745600,
181 .regshift = 1,
182 .iotype = UPIO_MEM,
183 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
184 }, {
185 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
186 /* irq number is run-time assigned */
187 .uartclk = 14745600,
188 .regshift = 1,
189 .iotype = UPIO_MEM,
190 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
191 }, {
192 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
193 /* irq number is run-time assigned */
194 .uartclk = 14745600,
195 .regshift = 1,
196 .iotype = UPIO_MEM,
197 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
198 }, {
199 }
200};
201
202static struct platform_device serial_device = {
203 .name = "serial8250",
204 .id = 0,
205 .dev = {
206 .platform_data = serial_platform_data,
207 },
208};
209#endif
210
211static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
212{
213 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
214}
215
216static struct mxc_usbh_platform_data otg_pdata __initdata = {
217 .init = eukrea_cpuimx27_otg_init,
218 .portsc = MXC_EHCI_MODE_ULPI,
219};
220
221static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
222{
223 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
224}
225
226static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
227 .init = eukrea_cpuimx27_usbh2_init,
228 .portsc = MXC_EHCI_MODE_ULPI,
229};
230
231static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
232 .operating_mode = FSL_USB2_DR_DEVICE,
233 .phy_mode = FSL_USB2_PHY_ULPI,
234};
235
236static bool otg_mode_host __initdata;
237
238static int __init eukrea_cpuimx27_otg_mode(char *options)
239{
240 if (!strcmp(options, "host"))
241 otg_mode_host = true;
242 else if (!strcmp(options, "device"))
243 otg_mode_host = false;
244 else
245 pr_info("otg_mode neither \"host\" nor \"device\". "
246 "Defaulting to device\n");
247 return 1;
248}
249__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
250
251static void __init eukrea_cpuimx27_init(void)
252{
253 imx27_soc_init();
254
255 mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
256 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
257
258 imx27_add_imx_uart0(&uart_pdata);
259
260 imx27_add_mxc_nand(&cpuimx27_nand_board_info);
261
262 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
263 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
264
265 imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
266
267 imx27_add_fec(NULL);
268 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
269 imx27_add_imx2_wdt();
270 imx27_add_mxc_w1();
271
272#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
273 /* SDHC2 can be used for Wifi */
274 imx27_add_mxc_mmc(1, NULL);
275#endif
276#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
277 /* in which case UART4 is also used for Bluetooth */
278 imx27_add_imx_uart3(&uart_pdata);
279#endif
280
281#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
282 serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
283 serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
284 serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
285 serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
286 platform_device_register(&serial_device);
287#endif
288
289 if (otg_mode_host) {
290 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
291 ULPI_OTG_DRVVBUS_EXT);
292 if (otg_pdata.otg)
293 imx27_add_mxc_ehci_otg(&otg_pdata);
294 } else {
295 imx27_add_fsl_usb2_udc(&otg_device_pdata);
296 }
297
298 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
299 ULPI_OTG_DRVVBUS_EXT);
300 if (usbh2_pdata.otg)
301 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
302
303#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
304 eukrea_mbimx27_baseboard_init();
305#endif
306}
307
308static void __init eukrea_cpuimx27_timer_init(void)
309{
310 mx27_clocks_init(26000000);
311}
312
313MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
314 .atag_offset = 0x100,
315 .map_io = mx27_map_io,
316 .init_early = imx27_init_early,
317 .init_irq = mx27_init_irq,
318 .init_time = eukrea_cpuimx27_timer_init,
319 .init_machine = eukrea_cpuimx27_init,
320 .restart = mxc_restart,
321MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
deleted file mode 100644
index 77fda3de4290..000000000000
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * arch/arm/mach-imx/mach-mx1ads.c
3 *
4 * Initially based on:
5 * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
6 * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
7 *
8 * 2004 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/i2c.h>
16#include <linux/i2c/pcf857x.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/mach/time.h>
25
26#include "common.h"
27#include "devices-imx1.h"
28#include "hardware.h"
29#include "iomux-mx1.h"
30
31static const int mx1ads_pins[] __initconst = {
32 /* UART1 */
33 PC9_PF_UART1_CTS,
34 PC10_PF_UART1_RTS,
35 PC11_PF_UART1_TXD,
36 PC12_PF_UART1_RXD,
37 /* UART2 */
38 PB28_PF_UART2_CTS,
39 PB29_PF_UART2_RTS,
40 PB30_PF_UART2_TXD,
41 PB31_PF_UART2_RXD,
42 /* I2C */
43 PA15_PF_I2C_SDA,
44 PA16_PF_I2C_SCL,
45 /* SPI */
46 PC13_PF_SPI1_SPI_RDY,
47 PC14_PF_SPI1_SCLK,
48 PC15_PF_SPI1_SS,
49 PC16_PF_SPI1_MISO,
50 PC17_PF_SPI1_MOSI,
51};
52
53/*
54 * UARTs platform data
55 */
56
57static const struct imxuart_platform_data uart0_pdata __initconst = {
58 .flags = IMXUART_HAVE_RTSCTS,
59};
60
61static const struct imxuart_platform_data uart1_pdata __initconst = {
62 .flags = IMXUART_HAVE_RTSCTS,
63};
64
65/*
66 * Physmap flash
67 */
68
69static const struct physmap_flash_data mx1ads_flash_data __initconst = {
70 .width = 4, /* bankwidth in bytes */
71};
72
73static const struct resource flash_resource __initconst = {
74 .start = MX1_CS0_PHYS,
75 .end = MX1_CS0_PHYS + SZ_32M - 1,
76 .flags = IORESOURCE_MEM,
77};
78
79/*
80 * I2C
81 */
82static struct pcf857x_platform_data pcf857x_data[] = {
83 {
84 .gpio_base = 4 * 32,
85 }, {
86 .gpio_base = 4 * 32 + 16,
87 }
88};
89
90static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
91 .bitrate = 100000,
92};
93
94static struct i2c_board_info mx1ads_i2c_devices[] = {
95 {
96 I2C_BOARD_INFO("pcf8575", 0x22),
97 .platform_data = &pcf857x_data[0],
98 }, {
99 I2C_BOARD_INFO("pcf8575", 0x24),
100 .platform_data = &pcf857x_data[1],
101 },
102};
103
104/*
105 * Board init
106 */
107static void __init mx1ads_init(void)
108{
109 imx1_soc_init();
110
111 mxc_gpio_setup_multiple_pins(mx1ads_pins,
112 ARRAY_SIZE(mx1ads_pins), "mx1ads");
113
114 /* UART */
115 imx1_add_imx_uart0(&uart0_pdata);
116 imx1_add_imx_uart1(&uart1_pdata);
117
118 /* Physmap flash */
119 platform_device_register_resndata(NULL, "physmap-flash", 0,
120 &flash_resource, 1,
121 &mx1ads_flash_data, sizeof(mx1ads_flash_data));
122
123 /* I2C */
124 i2c_register_board_info(0, mx1ads_i2c_devices,
125 ARRAY_SIZE(mx1ads_i2c_devices));
126
127 imx1_add_imx_i2c(&mx1ads_i2c_data);
128}
129
130static void __init mx1ads_timer_init(void)
131{
132 mx1_clocks_init(32000);
133}
134
135MACHINE_START(MX1ADS, "Freescale MX1ADS")
136 /* Maintainer: Sascha Hauer, Pengutronix */
137 .atag_offset = 0x100,
138 .map_io = mx1_map_io,
139 .init_early = imx1_init_early,
140 .init_irq = mx1_init_irq,
141 .init_time = mx1ads_timer_init,
142 .init_machine = mx1ads_init,
143 .restart = mxc_restart,
144MACHINE_END
145
146MACHINE_START(MXLADS, "Freescale MXLADS")
147 .atag_offset = 0x100,
148 .map_io = mx1_map_io,
149 .init_early = imx1_init_early,
150 .init_irq = mx1_init_irq,
151 .init_time = mx1ads_timer_init,
152 .init_machine = mx1ads_init,
153 .restart = mxc_restart,
154MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
deleted file mode 100644
index 0b5d1ca31b9f..000000000000
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_device.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/map.h>
20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h>
22#include <linux/i2c.h>
23#include <linux/irq.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28#include <linux/gpio.h>
29#include <linux/platform_data/pca953x.h>
30
31#include "common.h"
32#include "devices-imx27.h"
33#include "hardware.h"
34#include "iomux-mx27.h"
35
36static const int mxt_td60_pins[] __initconst = {
37 /* UART0 */
38 PE12_PF_UART1_TXD,
39 PE13_PF_UART1_RXD,
40 PE14_PF_UART1_CTS,
41 PE15_PF_UART1_RTS,
42 /* UART1 */
43 PE3_PF_UART2_CTS,
44 PE4_PF_UART2_RTS,
45 PE6_PF_UART2_TXD,
46 PE7_PF_UART2_RXD,
47 /* UART2 */
48 PE8_PF_UART3_TXD,
49 PE9_PF_UART3_RXD,
50 PE10_PF_UART3_CTS,
51 PE11_PF_UART3_RTS,
52 /* FEC */
53 PD0_AIN_FEC_TXD0,
54 PD1_AIN_FEC_TXD1,
55 PD2_AIN_FEC_TXD2,
56 PD3_AIN_FEC_TXD3,
57 PD4_AOUT_FEC_RX_ER,
58 PD5_AOUT_FEC_RXD1,
59 PD6_AOUT_FEC_RXD2,
60 PD7_AOUT_FEC_RXD3,
61 PD8_AF_FEC_MDIO,
62 PD9_AIN_FEC_MDC,
63 PD10_AOUT_FEC_CRS,
64 PD11_AOUT_FEC_TX_CLK,
65 PD12_AOUT_FEC_RXD0,
66 PD13_AOUT_FEC_RX_DV,
67 PD14_AOUT_FEC_RX_CLK,
68 PD15_AOUT_FEC_COL,
69 PD16_AIN_FEC_TX_ER,
70 PF23_AIN_FEC_TX_EN,
71 /* I2C1 */
72 PD17_PF_I2C_DATA,
73 PD18_PF_I2C_CLK,
74 /* I2C2 */
75 PC5_PF_I2C2_SDA,
76 PC6_PF_I2C2_SCL,
77 /* FB */
78 PA5_PF_LSCLK,
79 PA6_PF_LD0,
80 PA7_PF_LD1,
81 PA8_PF_LD2,
82 PA9_PF_LD3,
83 PA10_PF_LD4,
84 PA11_PF_LD5,
85 PA12_PF_LD6,
86 PA13_PF_LD7,
87 PA14_PF_LD8,
88 PA15_PF_LD9,
89 PA16_PF_LD10,
90 PA17_PF_LD11,
91 PA18_PF_LD12,
92 PA19_PF_LD13,
93 PA20_PF_LD14,
94 PA21_PF_LD15,
95 PA22_PF_LD16,
96 PA23_PF_LD17,
97 PA25_PF_CLS,
98 PA27_PF_SPL_SPR,
99 PA28_PF_HSYNC,
100 PA29_PF_VSYNC,
101 PA30_PF_CONTRAST,
102 PA31_PF_OE_ACD,
103 /* OWIRE */
104 PE16_AF_OWIRE,
105 /* SDHC1*/
106 PE18_PF_SD1_D0,
107 PE19_PF_SD1_D1,
108 PE20_PF_SD1_D2,
109 PE21_PF_SD1_D3,
110 PE22_PF_SD1_CMD,
111 PE23_PF_SD1_CLK,
112 PF8_AF_ATA_IORDY,
113 /* SDHC2*/
114 PB4_PF_SD2_D0,
115 PB5_PF_SD2_D1,
116 PB6_PF_SD2_D2,
117 PB7_PF_SD2_D3,
118 PB8_PF_SD2_CMD,
119 PB9_PF_SD2_CLK,
120};
121
122static const struct mxc_nand_platform_data
123mxt_td60_nand_board_info __initconst = {
124 .width = 1,
125 .hw_ecc = 1,
126};
127
128static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
129 .bitrate = 100000,
130};
131
132/* PCA9557 */
133static int mxt_td60_pca9557_setup(struct i2c_client *client,
134 unsigned gpio_base, unsigned ngpio,
135 void *context)
136{
137 static int mxt_td60_gpio_value[] = {
138 -1, -1, -1, -1, -1, -1, -1, 1
139 };
140 int n;
141
142 for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
143 gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
144 if (mxt_td60_gpio_value[n] < 0)
145 gpio_direction_input(gpio_base + n);
146 else
147 gpio_direction_output(gpio_base + n,
148 mxt_td60_gpio_value[n]);
149 gpio_export(gpio_base + n, 0);
150 }
151
152 return 0;
153}
154
155static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
156 .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */
157 .invert = 0, /* Do not invert */
158 .setup = mxt_td60_pca9557_setup,
159};
160
161static struct i2c_board_info mxt_td60_i2c_devices[] = {
162 {
163 I2C_BOARD_INFO("pca9557", 0x18),
164 .platform_data = &mxt_td60_pca9557_pdata,
165 },
166};
167
168static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
169 .bitrate = 100000,
170};
171
172static struct i2c_board_info mxt_td60_i2c2_devices[] = {
173};
174
175static struct imx_fb_videomode mxt_td60_modes[] = {
176 {
177 .mode = {
178 .name = "Chimei LW700AT9003",
179 .refresh = 60,
180 .xres = 800,
181 .yres = 480,
182 .pixclock = 30303,
183 .hsync_len = 64,
184 .left_margin = 0x67,
185 .right_margin = 0x68,
186 .vsync_len = 16,
187 .upper_margin = 0x0f,
188 .lower_margin = 0x0f,
189 },
190 .bpp = 16,
191 .pcr = 0xFA208B83,
192 },
193};
194
195static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
196 .mode = mxt_td60_modes,
197 .num_modes = ARRAY_SIZE(mxt_td60_modes),
198
199 /*
200 * - HSYNC active high
201 * - VSYNC active high
202 * - clk notenabled while idle
203 * - clock inverted
204 * - data not inverted
205 * - data enable low active
206 * - enable sharp mode
207 */
208 .pwmr = 0x00A903FF,
209 .lscr1 = 0x00120300,
210 .dmacr = 0x00020010,
211};
212
213static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
214 void *data)
215{
216 return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
217 IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
218}
219
220static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
221{
222 free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
223}
224
225static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
226 .init = mxt_td60_sdhc1_init,
227 .exit = mxt_td60_sdhc1_exit,
228};
229
230static const struct imxuart_platform_data uart_pdata __initconst = {
231 .flags = IMXUART_HAVE_RTSCTS,
232};
233
234static void __init mxt_td60_board_init(void)
235{
236 imx27_soc_init();
237
238 mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
239 "MXT_TD60");
240
241 imx27_add_imx_uart0(&uart_pdata);
242 imx27_add_imx_uart1(&uart_pdata);
243 imx27_add_imx_uart2(&uart_pdata);
244 imx27_add_mxc_nand(&mxt_td60_nand_board_info);
245
246 i2c_register_board_info(0, mxt_td60_i2c_devices,
247 ARRAY_SIZE(mxt_td60_i2c_devices));
248
249 i2c_register_board_info(1, mxt_td60_i2c2_devices,
250 ARRAY_SIZE(mxt_td60_i2c2_devices));
251
252 imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
253 imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
254 imx27_add_imx_fb(&mxt_td60_fb_data);
255 imx27_add_mxc_mmc(0, &sdhc1_pdata);
256 imx27_add_fec(NULL);
257}
258
259static void __init mxt_td60_timer_init(void)
260{
261 mx27_clocks_init(26000000);
262}
263
264MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
265 /* maintainer: Maxtrack Industrial */
266 .atag_offset = 0x100,
267 .map_io = mx27_map_io,
268 .init_early = imx27_init_early,
269 .init_irq = mx27_init_irq,
270 .init_time = mxt_td60_timer_init,
271 .init_machine = mxt_td60_board_init,
272 .restart = mxc_restart,
273MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
deleted file mode 100644
index ee862ad6b6fc..000000000000
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ /dev/null
@@ -1,358 +0,0 @@
1/*
2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/i2c.h>
21#include <linux/platform_data/at24.h>
22#include <linux/io.h>
23#include <linux/mtd/plat-ram.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26#include <linux/regulator/machine.h>
27#include <linux/mfd/mc13783.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
30#include <linux/gpio.h>
31
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/time.h>
35
36#include "board-pcm038.h"
37#include "common.h"
38#include "devices-imx27.h"
39#include "ehci.h"
40#include "hardware.h"
41#include "iomux-mx27.h"
42#include "ulpi.h"
43
44static const int pcm038_pins[] __initconst = {
45 /* UART1 */
46 PE12_PF_UART1_TXD,
47 PE13_PF_UART1_RXD,
48 PE14_PF_UART1_CTS,
49 PE15_PF_UART1_RTS,
50 /* UART2 */
51 PE3_PF_UART2_CTS,
52 PE4_PF_UART2_RTS,
53 PE6_PF_UART2_TXD,
54 PE7_PF_UART2_RXD,
55 /* UART3 */
56 PE8_PF_UART3_TXD,
57 PE9_PF_UART3_RXD,
58 PE10_PF_UART3_CTS,
59 PE11_PF_UART3_RTS,
60 /* FEC */
61 PD0_AIN_FEC_TXD0,
62 PD1_AIN_FEC_TXD1,
63 PD2_AIN_FEC_TXD2,
64 PD3_AIN_FEC_TXD3,
65 PD4_AOUT_FEC_RX_ER,
66 PD5_AOUT_FEC_RXD1,
67 PD6_AOUT_FEC_RXD2,
68 PD7_AOUT_FEC_RXD3,
69 PD8_AF_FEC_MDIO,
70 PD9_AIN_FEC_MDC,
71 PD10_AOUT_FEC_CRS,
72 PD11_AOUT_FEC_TX_CLK,
73 PD12_AOUT_FEC_RXD0,
74 PD13_AOUT_FEC_RX_DV,
75 PD14_AOUT_FEC_RX_CLK,
76 PD15_AOUT_FEC_COL,
77 PD16_AIN_FEC_TX_ER,
78 PF23_AIN_FEC_TX_EN,
79 /* I2C2 */
80 PC5_PF_I2C2_SDA,
81 PC6_PF_I2C2_SCL,
82 /* SPI1 */
83 PD25_PF_CSPI1_RDY,
84 PD29_PF_CSPI1_SCLK,
85 PD30_PF_CSPI1_MISO,
86 PD31_PF_CSPI1_MOSI,
87 /* SSI1 */
88 PC20_PF_SSI1_FS,
89 PC21_PF_SSI1_RXD,
90 PC22_PF_SSI1_TXD,
91 PC23_PF_SSI1_CLK,
92 /* SSI4 */
93 PC16_PF_SSI4_FS,
94 PC17_PF_SSI4_RXD,
95 PC18_PF_SSI4_TXD,
96 PC19_PF_SSI4_CLK,
97 /* USB host */
98 PA0_PF_USBH2_CLK,
99 PA1_PF_USBH2_DIR,
100 PA2_PF_USBH2_DATA7,
101 PA3_PF_USBH2_NXT,
102 PA4_PF_USBH2_STP,
103 PD19_AF_USBH2_DATA4,
104 PD20_AF_USBH2_DATA3,
105 PD21_AF_USBH2_DATA6,
106 PD22_AF_USBH2_DATA0,
107 PD23_AF_USBH2_DATA2,
108 PD24_AF_USBH2_DATA1,
109 PD26_AF_USBH2_DATA5,
110};
111
112/*
113 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
114 * 16 bit width
115 */
116
117static struct platdata_mtd_ram pcm038_sram_data = {
118 .bankwidth = 2,
119};
120
121static struct resource pcm038_sram_resource = {
122 .start = MX27_CS1_BASE_ADDR,
123 .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
124 .flags = IORESOURCE_MEM,
125};
126
127static struct platform_device pcm038_sram_mtd_device = {
128 .name = "mtd-ram",
129 .id = 0,
130 .dev = {
131 .platform_data = &pcm038_sram_data,
132 },
133 .num_resources = 1,
134 .resource = &pcm038_sram_resource,
135};
136
137/*
138 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
139 * 16 bit width
140 */
141static struct physmap_flash_data pcm038_flash_data = {
142 .width = 2,
143};
144
145static struct resource pcm038_flash_resource = {
146 .start = 0xc0000000,
147 .end = 0xc1ffffff,
148 .flags = IORESOURCE_MEM,
149};
150
151static struct platform_device pcm038_nor_mtd_device = {
152 .name = "physmap-flash",
153 .id = 0,
154 .dev = {
155 .platform_data = &pcm038_flash_data,
156 },
157 .num_resources = 1,
158 .resource = &pcm038_flash_resource,
159};
160
161static const struct imxuart_platform_data uart_pdata __initconst = {
162 .flags = IMXUART_HAVE_RTSCTS,
163};
164
165static const struct mxc_nand_platform_data
166pcm038_nand_board_info __initconst = {
167 .width = 1,
168 .hw_ecc = 1,
169};
170
171static struct platform_device *platform_devices[] __initdata = {
172 &pcm038_nor_mtd_device,
173 &pcm038_sram_mtd_device,
174};
175
176/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
177 * setup other stuffs to access the sram. */
178static void __init pcm038_init_sram(void)
179{
180 __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1)));
181 __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1)));
182 __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1)));
183}
184
185static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
186 .bitrate = 100000,
187};
188
189static struct at24_platform_data board_eeprom = {
190 .byte_len = 4096,
191 .page_size = 32,
192 .flags = AT24_FLAG_ADDR16,
193};
194
195static struct i2c_board_info pcm038_i2c_devices[] = {
196 {
197 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
198 .platform_data = &board_eeprom,
199 }, {
200 I2C_BOARD_INFO("pcf8563", 0x51),
201 }, {
202 I2C_BOARD_INFO("lm75", 0x4a),
203 }
204};
205
206static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
207
208static const struct spi_imx_master pcm038_spi0_data __initconst = {
209 .chipselect = pcm038_spi_cs,
210 .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
211};
212
213static struct regulator_consumer_supply sdhc1_consumers[] = {
214 {
215 .dev_name = "imx21-mmc.1",
216 .supply = "sdhc_vcc",
217 },
218};
219
220static struct regulator_init_data sdhc1_data = {
221 .constraints = {
222 .min_uV = 3000000,
223 .max_uV = 3400000,
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
225 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
226 .valid_modes_mask = REGULATOR_MODE_NORMAL |
227 REGULATOR_MODE_FAST,
228 .always_on = 0,
229 .boot_on = 0,
230 },
231 .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
232 .consumer_supplies = sdhc1_consumers,
233};
234
235static struct regulator_consumer_supply cam_consumers[] = {
236 {
237 .dev_name = NULL,
238 .supply = "imx_cam_vcc",
239 },
240};
241
242static struct regulator_init_data cam_data = {
243 .constraints = {
244 .min_uV = 3000000,
245 .max_uV = 3400000,
246 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
247 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
248 .valid_modes_mask = REGULATOR_MODE_NORMAL |
249 REGULATOR_MODE_FAST,
250 .always_on = 0,
251 .boot_on = 0,
252 },
253 .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
254 .consumer_supplies = cam_consumers,
255};
256
257static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
258 {
259 .id = MC13783_REG_VCAM,
260 .init_data = &cam_data,
261 }, {
262 .id = MC13783_REG_VMMC1,
263 .init_data = &sdhc1_data,
264 },
265};
266
267static struct mc13xxx_platform_data pcm038_pmic = {
268 .regulators = {
269 .regulators = pcm038_regulators,
270 .num_regulators = ARRAY_SIZE(pcm038_regulators),
271 },
272 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
273};
274
275static struct spi_board_info pcm038_spi_board_info[] __initdata = {
276 {
277 .modalias = "mc13783",
278 /* irq number is run-time assigned */
279 .max_speed_hz = 300000,
280 .bus_num = 0,
281 .chip_select = 0,
282 .platform_data = &pcm038_pmic,
283 .mode = SPI_CS_HIGH,
284 }
285};
286
287static int pcm038_usbh2_init(struct platform_device *pdev)
288{
289 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
290 MXC_EHCI_INTERFACE_DIFF_UNI);
291}
292
293static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
294 .init = pcm038_usbh2_init,
295 .portsc = MXC_EHCI_MODE_ULPI,
296};
297
298static void __init pcm038_init(void)
299{
300 imx27_soc_init();
301
302 mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
303 "PCM038");
304
305 pcm038_init_sram();
306
307 imx27_add_imx_uart0(&uart_pdata);
308 imx27_add_imx_uart1(&uart_pdata);
309 imx27_add_imx_uart2(&uart_pdata);
310
311 mxc_gpio_mode(PE16_AF_OWIRE);
312 imx27_add_mxc_nand(&pcm038_nand_board_info);
313
314 /* only the i2c master 1 is used on this CPU card */
315 i2c_register_board_info(1, pcm038_i2c_devices,
316 ARRAY_SIZE(pcm038_i2c_devices));
317
318 imx27_add_imx_i2c(1, &pcm038_i2c1_data);
319
320 /* PE18 for user-LED D40 */
321 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
322
323 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
324
325 /* MC13783 IRQ */
326 mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
327
328 imx27_add_spi_imx0(&pcm038_spi0_data);
329 pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
330 spi_register_board_info(pcm038_spi_board_info,
331 ARRAY_SIZE(pcm038_spi_board_info));
332
333 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
334
335 imx27_add_fec(NULL);
336 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
337 imx27_add_imx2_wdt();
338 imx27_add_mxc_w1();
339
340#ifdef CONFIG_MACH_PCM970_BASEBOARD
341 pcm970_baseboard_init();
342#endif
343}
344
345static void __init pcm038_timer_init(void)
346{
347 mx27_clocks_init(26000000);
348}
349
350MACHINE_START(PCM038, "phyCORE-i.MX27")
351 .atag_offset = 0x100,
352 .map_io = mx27_map_io,
353 .init_early = imx27_init_early,
354 .init_irq = mx27_init_irq,
355 .init_time = pcm038_timer_init,
356 .init_machine = pcm038_init,
357 .restart = mxc_restart,
358MACHINE_END
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
deleted file mode 100644
index 51c608234089..000000000000
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/gpio.h>
20#include <linux/irq.h>
21#include <linux/platform_device.h>
22#include <linux/can/platform/sja1000.h>
23
24#include <asm/mach/arch.h>
25
26#include "common.h"
27#include "devices-imx27.h"
28#include "hardware.h"
29#include "iomux-mx27.h"
30
31static const int pcm970_pins[] __initconst = {
32 /* SDHC */
33 PB4_PF_SD2_D0,
34 PB5_PF_SD2_D1,
35 PB6_PF_SD2_D2,
36 PB7_PF_SD2_D3,
37 PB8_PF_SD2_CMD,
38 PB9_PF_SD2_CLK,
39 /* display */
40 PA5_PF_LSCLK,
41 PA6_PF_LD0,
42 PA7_PF_LD1,
43 PA8_PF_LD2,
44 PA9_PF_LD3,
45 PA10_PF_LD4,
46 PA11_PF_LD5,
47 PA12_PF_LD6,
48 PA13_PF_LD7,
49 PA14_PF_LD8,
50 PA15_PF_LD9,
51 PA16_PF_LD10,
52 PA17_PF_LD11,
53 PA18_PF_LD12,
54 PA19_PF_LD13,
55 PA20_PF_LD14,
56 PA21_PF_LD15,
57 PA22_PF_LD16,
58 PA23_PF_LD17,
59 PA24_PF_REV,
60 PA25_PF_CLS,
61 PA26_PF_PS,
62 PA27_PF_SPL_SPR,
63 PA28_PF_HSYNC,
64 PA29_PF_VSYNC,
65 PA30_PF_CONTRAST,
66 PA31_PF_OE_ACD,
67 /*
68 * it seems the data line misses a pullup, so we must enable
69 * the internal pullup as a local workaround
70 */
71 PD17_PF_I2C_DATA | GPIO_PUEN,
72 PD18_PF_I2C_CLK,
73 /* Camera */
74 PB10_PF_CSI_D0,
75 PB11_PF_CSI_D1,
76 PB12_PF_CSI_D2,
77 PB13_PF_CSI_D3,
78 PB14_PF_CSI_D4,
79 PB15_PF_CSI_MCLK,
80 PB16_PF_CSI_PIXCLK,
81 PB17_PF_CSI_D5,
82 PB18_PF_CSI_D6,
83 PB19_PF_CSI_D7,
84 PB20_PF_CSI_VSYNC,
85 PB21_PF_CSI_HSYNC,
86};
87
88static int pcm970_sdhc2_get_ro(struct device *dev)
89{
90 return gpio_get_value(GPIO_PORTC + 28);
91}
92
93static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
94{
95 int ret;
96
97 ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
98 IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
99 if (ret)
100 return ret;
101
102 ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
103 if (ret) {
104 free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
105 return ret;
106 }
107
108 gpio_direction_input(GPIO_PORTC + 28);
109
110 return 0;
111}
112
113static void pcm970_sdhc2_exit(struct device *dev, void *data)
114{
115 free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
116 gpio_free(GPIO_PORTC + 28);
117}
118
119static const struct imxmmc_platform_data sdhc_pdata __initconst = {
120 .get_ro = pcm970_sdhc2_get_ro,
121 .init = pcm970_sdhc2_init,
122 .exit = pcm970_sdhc2_exit,
123};
124
125static struct imx_fb_videomode pcm970_modes[] = {
126 {
127 .mode = {
128 .name = "Sharp-LQ035Q7",
129 .refresh = 60,
130 .xres = 240,
131 .yres = 320,
132 .pixclock = 188679, /* in ps (5.3MHz) */
133 .hsync_len = 7,
134 .left_margin = 5,
135 .right_margin = 16,
136 .vsync_len = 1,
137 .upper_margin = 7,
138 .lower_margin = 9,
139 },
140 /*
141 * - HSYNC active high
142 * - VSYNC active high
143 * - clk notenabled while idle
144 * - clock not inverted
145 * - data not inverted
146 * - data enable low active
147 * - enable sharp mode
148 */
149 .pcr = 0xF00080C0,
150 .bpp = 16,
151 }, {
152 .mode = {
153 .name = "TX090",
154 .refresh = 60,
155 .xres = 240,
156 .yres = 320,
157 .pixclock = 38255,
158 .left_margin = 144,
159 .right_margin = 0,
160 .upper_margin = 7,
161 .lower_margin = 40,
162 .hsync_len = 96,
163 .vsync_len = 1,
164 },
165 /*
166 * - HSYNC active low (1 << 22)
167 * - VSYNC active low (1 << 23)
168 * - clk notenabled while idle
169 * - clock not inverted
170 * - data not inverted
171 * - data enable low active
172 * - enable sharp mode
173 */
174 .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
175 .bpp = 32,
176 },
177};
178
179static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
180 .mode = pcm970_modes,
181 .num_modes = ARRAY_SIZE(pcm970_modes),
182
183 .pwmr = 0x00A903FF,
184 .lscr1 = 0x00120300,
185 .dmacr = 0x00020010,
186};
187
188static struct resource pcm970_sja1000_resources[] = {
189 {
190 .start = MX27_CS4_BASE_ADDR,
191 .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
192 .flags = IORESOURCE_MEM,
193 }, {
194 /* irq number is run-time assigned */
195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
196 },
197};
198
199static struct sja1000_platform_data pcm970_sja1000_platform_data = {
200 .osc_freq = 16000000,
201 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
202 .cdr = CDR_CBP,
203};
204
205static struct platform_device pcm970_sja1000 = {
206 .name = "sja1000_platform",
207 .dev = {
208 .platform_data = &pcm970_sja1000_platform_data,
209 },
210 .resource = pcm970_sja1000_resources,
211 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
212};
213
214/*
215 * system init for baseboard usage. Will be called by pcm038 init.
216 *
217 * Add platform devices present on this baseboard and init
218 * them from CPU side as far as required to use them later on
219 */
220void __init pcm970_baseboard_init(void)
221{
222 mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
223 "PCM970");
224
225 imx27_add_imx_fb(&pcm038_fb_data);
226 mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
227 imx27_add_mxc_mmc(1, &sdhc_pdata);
228 pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
229 pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
230 platform_device_register(&pcm970_sja1000);
231}
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 5b57c17c06bd..771bd25c1025 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -20,8 +20,6 @@
20#include "common.h" 20#include "common.h"
21#include "hardware.h" 21#include "hardware.h"
22 22
23#define SCU_STANDBY_ENABLE (1 << 5)
24
25u32 g_diag_reg; 23u32 g_diag_reg;
26static void __iomem *scu_base; 24static void __iomem *scu_base;
27 25
@@ -45,14 +43,6 @@ void __init imx_scu_map_io(void)
45 scu_base = IMX_IO_ADDRESS(base); 43 scu_base = IMX_IO_ADDRESS(base);
46} 44}
47 45
48void imx_scu_standby_enable(void)
49{
50 u32 val = readl_relaxed(scu_base);
51
52 val |= SCU_STANDBY_ENABLE;
53 writel_relaxed(val, scu_base);
54}
55
56static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) 46static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
57{ 47{
58 imx_set_cpu_jump(cpu, v7_secondary_startup); 48 imx_set_cpu_jump(cpu, v7_secondary_startup);
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
deleted file mode 100644
index 873c3ca3cd7e..000000000000
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/* linux/arch/arm/mach-msm/board-mahimahi.c
2 *
3 * Copyright (C) 2009 Google, Inc.
4 * Copyright (C) 2009 HTC Corporation.
5 * Author: Dima Zavin <dima@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/delay.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/input.h>
22#include <linux/io.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <linux/memblock.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/setup.h>
31
32#include <mach/hardware.h>
33
34#include "board-mahimahi.h"
35#include "devices.h"
36#include "proc_comm.h"
37#include "common.h"
38
39static uint debug_uart;
40
41module_param_named(debug_uart, debug_uart, uint, 0);
42
43static struct platform_device *devices[] __initdata = {
44#if !defined(CONFIG_MSM_SERIAL_DEBUGGER)
45 &msm_device_uart1,
46#endif
47 &msm_device_uart_dm1,
48 &msm_device_nand,
49};
50
51static void __init mahimahi_init(void)
52{
53 platform_add_devices(devices, ARRAY_SIZE(devices));
54}
55
56static void __init mahimahi_fixup(struct tag *tags, char **cmdline)
57{
58 memblock_add(PHYS_OFFSET, 219*SZ_1M);
59 memblock_add(MSM_HIGHMEM_BASE, MSM_HIGHMEM_SIZE);
60}
61
62static void __init mahimahi_map_io(void)
63{
64 msm_map_common_io();
65 msm_clock_init();
66}
67
68static void __init mahimahi_init_late(void)
69{
70 smd_debugfs_init();
71}
72
73void msm_timer_init(void);
74
75MACHINE_START(MAHIMAHI, "mahimahi")
76 .atag_offset = 0x100,
77 .fixup = mahimahi_fixup,
78 .map_io = mahimahi_map_io,
79 .init_irq = msm_init_irq,
80 .init_machine = mahimahi_init,
81 .init_late = mahimahi_init_late,
82 .init_time = msm_timer_init,
83MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 245884319d2e..8f5ecdc4f3ce 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -124,7 +124,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
124static struct platform_device *devices[] __initdata = { 124static struct platform_device *devices[] __initdata = {
125 &msm_clock_7x30, 125 &msm_clock_7x30,
126 &msm_device_gpio_7x30, 126 &msm_device_gpio_7x30,
127#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) 127#if defined(CONFIG_SERIAL_MSM)
128 &msm_device_uart2, 128 &msm_device_uart2,
129#endif 129#endif
130 &msm_device_smd, 130 &msm_device_smd,
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 2c25050209ce..722ad63b7edc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -94,7 +94,7 @@ static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
94 } 94 }
95 95
96static struct msm_gpio_chip msm_gpio_banks[] = { 96static struct msm_gpio_chip msm_gpio_banks[] = {
97#if defined(CONFIG_MSM_DEBUG_UART1) 97#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9a00000)
98 /* H2W pins <-> UART1 */ 98 /* H2W pins <-> UART1 */
99 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40), 99 TROUT_GPIO_BANK("MISC2", 0x00, TROUT_GPIO_MISC2_BASE, 0x40),
100#else 100#else
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index f72b07de2152..ba3edd3a46cb 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -88,7 +88,7 @@ static void __init trout_map_io(void)
88 msm_map_common_io(); 88 msm_map_common_io();
89 iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc)); 89 iotable_init(trout_io_desc, ARRAY_SIZE(trout_io_desc));
90 90
91#ifdef CONFIG_MSM_DEBUG_UART3 91#if defined(CONFIG_DEBUG_MSM_UART) && (CONFIG_DEBUG_UART_PHYS == 0xa9c00000)
92 /* route UART3 to the "H2W" extended usb connector */ 92 /* route UART3 to the "H2W" extended usb connector */
93 writeb(0x80, TROUT_CPLD_BASE + 0x00); 93 writeb(0x80, TROUT_CPLD_BASE + 0x00);
94#endif 94#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 34e09474636d..b042dca1f633 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -57,8 +57,7 @@ static struct map_desc msm_io_desc[] __initdata = {
57 .length = MSM_SHARED_RAM_SIZE, 57 .length = MSM_SHARED_RAM_SIZE,
58 .type = MT_DEVICE, 58 .type = MT_DEVICE,
59 }, 59 },
60#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 60#if defined(CONFIG_DEBUG_MSM_UART)
61 defined(CONFIG_DEBUG_MSM_UART3)
62 { 61 {
63 /* Must be last: virtual and pfn filled in by debug_ll_addr() */ 62 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
64 .length = SZ_4K, 63 .length = SZ_4K,
@@ -76,8 +75,7 @@ void __init msm_map_common_io(void)
76 * pages are peripheral interface or not. 75 * pages are peripheral interface or not.
77 */ 76 */
78 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); 77 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
79#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ 78#if defined(CONFIG_DEBUG_MSM_UART)
80 defined(CONFIG_DEBUG_MSM_UART3)
81#ifdef CONFIG_MMU 79#ifdef CONFIG_MMU
82 debug_ll_addr(&msm_io_desc[size - 1].pfn, 80 debug_ll_addr(&msm_io_desc[size - 1].pfn,
83 &msm_io_desc[size - 1].virtual); 81 &msm_io_desc[size - 1].virtual);
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index bf852d7ae951..7a050f9c37ff 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -544,7 +544,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
544 MAX_MODULE_SOFTRESET_WAIT, c); 544 MAX_MODULE_SOFTRESET_WAIT, c);
545 545
546 if (c == MAX_MODULE_SOFTRESET_WAIT) 546 if (c == MAX_MODULE_SOFTRESET_WAIT)
547 pr_warning("dss_core: waiting for reset to finish failed\n"); 547 pr_warn("dss_core: waiting for reset to finish failed\n");
548 else 548 else
549 pr_debug("dss_core: softreset done\n"); 549 pr_debug("dss_core: softreset done\n");
550 550
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index f78b4a161959..f3897d82e53e 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -67,8 +67,8 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
67 MAX_MODULE_SOFTRESET_WAIT, c); 67 MAX_MODULE_SOFTRESET_WAIT, c);
68 68
69 if (c == MAX_MODULE_SOFTRESET_WAIT) 69 if (c == MAX_MODULE_SOFTRESET_WAIT)
70 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 70 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
71 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 71 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
72 else 72 else
73 pr_debug("%s: %s: softreset in %d usec\n", __func__, 73 pr_debug("%s: %s: softreset in %d usec\n", __func__,
74 oh->name, c); 74 oh->name, c);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b456b4471f35..b9d8e47ffe8e 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -99,7 +99,7 @@ int omap_i2c_reset(struct omap_hwmod *oh)
99 MAX_MODULE_SOFTRESET_WAIT, c); 99 MAX_MODULE_SOFTRESET_WAIT, c);
100 100
101 if (c == MAX_MODULE_SOFTRESET_WAIT) 101 if (c == MAX_MODULE_SOFTRESET_WAIT)
102 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 102 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
103 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 103 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
104 else 104 else
105 pr_debug("%s: %s: softreset in %d usec\n", __func__, 105 pr_debug("%s: %s: softreset in %d usec\n", __func__,
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index 828e0db3d943..8bdf182422bd 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -76,8 +76,8 @@ int omap_msdi_reset(struct omap_hwmod *oh)
76 MAX_MODULE_SOFTRESET_WAIT, c); 76 MAX_MODULE_SOFTRESET_WAIT, c);
77 77
78 if (c == MAX_MODULE_SOFTRESET_WAIT) 78 if (c == MAX_MODULE_SOFTRESET_WAIT)
79 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 79 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
80 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 80 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
81 else 81 else
82 pr_debug("%s: %s: softreset in %d usec\n", __func__, 82 pr_debug("%s: %s: softreset in %d usec\n", __func__,
83 oh->name, c); 83 oh->name, c);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ac8a249779f2..78064b0d4db5 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -814,7 +814,7 @@ int __init omap_mux_late_init(void)
814 "hwmod_io", omap_mux_late_init); 814 "hwmod_io", omap_mux_late_init);
815 815
816 if (ret) 816 if (ret)
817 pr_warning("mux: Failed to setup hwmod io irq %d\n", ret); 817 pr_warn("mux: Failed to setup hwmod io irq %d\n", ret);
818 818
819 return 0; 819 return 0;
820} 820}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e91a4e7519a..faa65833a0d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -769,8 +769,8 @@ static int _init_main_clk(struct omap_hwmod *oh)
769 769
770 oh->_clk = clk_get(NULL, oh->main_clk); 770 oh->_clk = clk_get(NULL, oh->main_clk);
771 if (IS_ERR(oh->_clk)) { 771 if (IS_ERR(oh->_clk)) {
772 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", 772 pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
773 oh->name, oh->main_clk); 773 oh->name, oh->main_clk);
774 return -EINVAL; 774 return -EINVAL;
775 } 775 }
776 /* 776 /*
@@ -814,8 +814,8 @@ static int _init_interface_clks(struct omap_hwmod *oh)
814 814
815 c = clk_get(NULL, os->clk); 815 c = clk_get(NULL, os->clk);
816 if (IS_ERR(c)) { 816 if (IS_ERR(c)) {
817 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", 817 pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
818 oh->name, os->clk); 818 oh->name, os->clk);
819 ret = -EINVAL; 819 ret = -EINVAL;
820 continue; 820 continue;
821 } 821 }
@@ -851,8 +851,8 @@ static int _init_opt_clks(struct omap_hwmod *oh)
851 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { 851 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
852 c = clk_get(NULL, oc->clk); 852 c = clk_get(NULL, oc->clk);
853 if (IS_ERR(c)) { 853 if (IS_ERR(c)) {
854 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", 854 pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
855 oh->name, oc->clk); 855 oh->name, oc->clk);
856 ret = -EINVAL; 856 ret = -EINVAL;
857 continue; 857 continue;
858 } 858 }
@@ -1576,7 +1576,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
1576 1576
1577 oh->clkdm = clkdm_lookup(oh->clkdm_name); 1577 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1578 if (!oh->clkdm) { 1578 if (!oh->clkdm) {
1579 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", 1579 pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n",
1580 oh->name, oh->clkdm_name); 1580 oh->name, oh->clkdm_name);
1581 return 0; 1581 return 0;
1582 } 1582 }
@@ -1616,7 +1616,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
1616 if (!ret) 1616 if (!ret)
1617 oh->_state = _HWMOD_STATE_CLKS_INITED; 1617 oh->_state = _HWMOD_STATE_CLKS_INITED;
1618 else 1618 else
1619 pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); 1619 pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
1620 1620
1621 return ret; 1621 return ret;
1622} 1622}
@@ -1739,7 +1739,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1739 _disable_clocks(oh); 1739 _disable_clocks(oh);
1740 1740
1741 if (ret == -EBUSY) 1741 if (ret == -EBUSY)
1742 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); 1742 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1743 1743
1744 if (!ret) { 1744 if (!ret) {
1745 /* 1745 /*
@@ -1953,8 +1953,8 @@ static int _ocp_softreset(struct omap_hwmod *oh)
1953 1953
1954 c = _wait_softreset_complete(oh); 1954 c = _wait_softreset_complete(oh);
1955 if (c == MAX_MODULE_SOFTRESET_WAIT) { 1955 if (c == MAX_MODULE_SOFTRESET_WAIT) {
1956 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", 1956 pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1957 oh->name, MAX_MODULE_SOFTRESET_WAIT); 1957 oh->name, MAX_MODULE_SOFTRESET_WAIT);
1958 ret = -ETIMEDOUT; 1958 ret = -ETIMEDOUT;
1959 goto dis_opt_clks; 1959 goto dis_opt_clks;
1960 } else { 1960 } else {
@@ -2618,8 +2618,8 @@ static int __init _setup_reset(struct omap_hwmod *oh)
2618 if (oh->rst_lines_cnt == 0) { 2618 if (oh->rst_lines_cnt == 0) {
2619 r = _enable(oh); 2619 r = _enable(oh);
2620 if (r) { 2620 if (r) {
2621 pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", 2621 pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2622 oh->name, oh->_state); 2622 oh->name, oh->_state);
2623 return -EINVAL; 2623 return -EINVAL;
2624 } 2624 }
2625 } 2625 }
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 05a8c8b07449..b3d3d30ffba0 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -244,8 +244,8 @@ static void __init nokia_n900_legacy_init(void)
244 /* set IBE to 1 */ 244 /* set IBE to 1 */
245 rx51_secure_update_aux_cr(BIT(6), 0); 245 rx51_secure_update_aux_cr(BIT(6), 0);
246 } else { 246 } else {
247 pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n"); 247 pr_warn("RX-51: Not enabling ARM errata 430973 workaround\n");
248 pr_warning("Thumb binaries may crash randomly without this workaround\n"); 248 pr_warn("Thumb binaries may crash randomly without this workaround\n");
249 } 249 }
250 250
251 pr_info("RX-51: Registring OMAP3 HWRNG device\n"); 251 pr_info("RX-51: Registring OMAP3 HWRNG device\n");
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3f80929a5f7e..175564c88a30 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -465,7 +465,7 @@ int __init omap3_pm_init(void)
465 int ret; 465 int ret;
466 466
467 if (!omap3_has_io_chain_ctrl()) 467 if (!omap3_has_io_chain_ctrl())
468 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); 468 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
469 469
470 pm_errata_configure(); 470 pm_errata_configure();
471 471
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 7a42e1960c3b..d3a588cf3a6e 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -20,8 +20,8 @@ static int sr_class3_enable(struct omap_sr *sr)
20 unsigned long volt = voltdm_get_voltage(sr->voltdm); 20 unsigned long volt = voltdm_get_voltage(sr->voltdm);
21 21
22 if (!volt) { 22 if (!volt) {
23 pr_warning("%s: Curr voltage unknown. Cannot enable %s\n", 23 pr_warn("%s: Curr voltage unknown. Cannot enable %s\n",
24 __func__, sr->name); 24 __func__, sr->name);
25 return -ENODATA; 25 return -ENODATA;
26 } 26 }
27 27
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 1b91ef0c182a..d7cff2632d1e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -154,7 +154,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
154 154
155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data)); 155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
156 if (IS_ERR(pdev)) 156 if (IS_ERR(pdev))
157 pr_warning("%s: Could not build omap_device for %s: %s.\n\n", 157 pr_warn("%s: Could not build omap_device for %s: %s\n",
158 __func__, name, oh->name); 158 __func__, name, oh->name);
159exit: 159exit:
160 i++; 160 i++;
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index a4628a9e760c..be9ef834fa81 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -198,7 +198,7 @@ int omap_vc_bypass_scale(struct voltagedomain *voltdm,
198 loop_cnt++; 198 loop_cnt++;
199 199
200 if (retries_cnt > 10) { 200 if (retries_cnt > 10) {
201 pr_warning("%s: Retry count exceeded\n", __func__); 201 pr_warn("%s: Retry count exceeded\n", __func__);
202 return -ETIMEDOUT; 202 return -ETIMEDOUT;
203 } 203 }
204 204
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 3ac8fe1d8213..3783b8625f0f 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -55,7 +55,7 @@ static LIST_HEAD(voltdm_list);
55unsigned long voltdm_get_voltage(struct voltagedomain *voltdm) 55unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
56{ 56{
57 if (!voltdm || IS_ERR(voltdm)) { 57 if (!voltdm || IS_ERR(voltdm)) {
58 pr_warning("%s: VDD specified does not exist!\n", __func__); 58 pr_warn("%s: VDD specified does not exist!\n", __func__);
59 return 0; 59 return 0;
60 } 60 }
61 61
@@ -77,7 +77,7 @@ int voltdm_scale(struct voltagedomain *voltdm,
77 unsigned long volt = 0; 77 unsigned long volt = 0;
78 78
79 if (!voltdm || IS_ERR(voltdm)) { 79 if (!voltdm || IS_ERR(voltdm)) {
80 pr_warning("%s: VDD specified does not exist!\n", __func__); 80 pr_warn("%s: VDD specified does not exist!\n", __func__);
81 return -EINVAL; 81 return -EINVAL;
82 } 82 }
83 83
@@ -96,8 +96,8 @@ int voltdm_scale(struct voltagedomain *voltdm,
96 } 96 }
97 97
98 if (!volt) { 98 if (!volt) {
99 pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n", 99 pr_warn("%s: not scaling. OPP voltage for %lu, not found.\n",
100 __func__, target_volt); 100 __func__, target_volt);
101 return -EINVAL; 101 return -EINVAL;
102 } 102 }
103 103
@@ -122,7 +122,7 @@ void voltdm_reset(struct voltagedomain *voltdm)
122 unsigned long target_volt; 122 unsigned long target_volt;
123 123
124 if (!voltdm || IS_ERR(voltdm)) { 124 if (!voltdm || IS_ERR(voltdm)) {
125 pr_warning("%s: VDD specified does not exist!\n", __func__); 125 pr_warn("%s: VDD specified does not exist!\n", __func__);
126 return; 126 return;
127 } 127 }
128 128
@@ -152,7 +152,7 @@ void omap_voltage_get_volttable(struct voltagedomain *voltdm,
152 struct omap_volt_data **volt_data) 152 struct omap_volt_data **volt_data)
153{ 153{
154 if (!voltdm || IS_ERR(voltdm)) { 154 if (!voltdm || IS_ERR(voltdm)) {
155 pr_warning("%s: VDD specified does not exist!\n", __func__); 155 pr_warn("%s: VDD specified does not exist!\n", __func__);
156 return; 156 return;
157 } 157 }
158 158
@@ -180,12 +180,12 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
180 int i; 180 int i;
181 181
182 if (!voltdm || IS_ERR(voltdm)) { 182 if (!voltdm || IS_ERR(voltdm)) {
183 pr_warning("%s: VDD specified does not exist!\n", __func__); 183 pr_warn("%s: VDD specified does not exist!\n", __func__);
184 return ERR_PTR(-EINVAL); 184 return ERR_PTR(-EINVAL);
185 } 185 }
186 186
187 if (!voltdm->volt_data) { 187 if (!voltdm->volt_data) {
188 pr_warning("%s: voltage table does not exist for vdd_%s\n", 188 pr_warn("%s: voltage table does not exist for vdd_%s\n",
189 __func__, voltdm->name); 189 __func__, voltdm->name);
190 return ERR_PTR(-ENODATA); 190 return ERR_PTR(-ENODATA);
191 } 191 }
@@ -214,7 +214,7 @@ int omap_voltage_register_pmic(struct voltagedomain *voltdm,
214 struct omap_voltdm_pmic *pmic) 214 struct omap_voltdm_pmic *pmic)
215{ 215{
216 if (!voltdm || IS_ERR(voltdm)) { 216 if (!voltdm || IS_ERR(voltdm)) {
217 pr_warning("%s: VDD specified does not exist!\n", __func__); 217 pr_warn("%s: VDD specified does not exist!\n", __func__);
218 return -EINVAL; 218 return -EINVAL;
219 } 219 }
220 220
@@ -237,7 +237,7 @@ void omap_change_voltscale_method(struct voltagedomain *voltdm,
237 int voltscale_method) 237 int voltscale_method)
238{ 238{
239 if (!voltdm || IS_ERR(voltdm)) { 239 if (!voltdm || IS_ERR(voltdm)) {
240 pr_warning("%s: VDD specified does not exist!\n", __func__); 240 pr_warn("%s: VDD specified does not exist!\n", __func__);
241 return; 241 return;
242 } 242 }
243 243
@@ -279,7 +279,7 @@ int __init omap_voltage_late_init(void)
279 279
280 sys_ck = clk_get(NULL, voltdm->sys_clk.name); 280 sys_ck = clk_get(NULL, voltdm->sys_clk.name);
281 if (IS_ERR(sys_ck)) { 281 if (IS_ERR(sys_ck)) {
282 pr_warning("%s: Could not get sys clk.\n", __func__); 282 pr_warn("%s: Could not get sys clk.\n", __func__);
283 return -EINVAL; 283 return -EINVAL;
284 } 284 }
285 voltdm->sys_clk.rate = clk_get_rate(sys_ck); 285 voltdm->sys_clk.rate = clk_get_rate(sys_ck);
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 97d6607d447a..ff0a68cf7439 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -93,8 +93,8 @@ int omap2_wd_timer_reset(struct omap_hwmod *oh)
93 udelay(oh->class->sysc->srst_udelay); 93 udelay(oh->class->sysc->srst_udelay);
94 94
95 if (c == MAX_MODULE_SOFTRESET_WAIT) 95 if (c == MAX_MODULE_SOFTRESET_WAIT)
96 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 96 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
97 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 97 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
98 else 98 else
99 pr_debug("%s: %s: softreset in %d usec\n", __func__, 99 pr_debug("%s: %s: softreset in %d usec\n", __func__,
100 oh->name, c); 100 oh->name, c);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 56edeab17b68..09d2a26985da 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -550,7 +550,7 @@ static int __init dns323_identify_rev(void)
550 break; 550 break;
551 } 551 }
552 if (i >= 1000) { 552 if (i >= 1000) {
553 pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n"); 553 pr_warn("DNS-323: Timeout accessing PHY, assuming rev B1\n");
554 return DNS323_REV_B1; 554 return DNS323_REV_B1;
555 } 555 }
556 writel((3 << 21) /* phy ID reg */ | 556 writel((3 << 21) /* phy ID reg */ |
@@ -562,7 +562,7 @@ static int __init dns323_identify_rev(void)
562 break; 562 break;
563 } 563 }
564 if (i >= 1000) { 564 if (i >= 1000) {
565 pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n"); 565 pr_warn("DNS-323: Timeout reading PHY, assuming rev B1\n");
566 return DNS323_REV_B1; 566 return DNS323_REV_B1;
567 } 567 }
568 pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff); 568 pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
@@ -577,8 +577,8 @@ static int __init dns323_identify_rev(void)
577 case 0x0e10: /* MV88E1118 */ 577 case 0x0e10: /* MV88E1118 */
578 return DNS323_REV_C1; 578 return DNS323_REV_C1;
579 default: 579 default:
580 pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n", 580 pr_warn("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
581 reg & 0xffff); 581 reg & 0xffff);
582 } 582 }
583 return DNS323_REV_B1; 583 return DNS323_REV_B1;
584} 584}
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 6208d125c1b9..12086745c9fd 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -349,7 +349,7 @@ static void __init tsp2_init(void)
349 gpio_free(TSP2_RTC_GPIO); 349 gpio_free(TSP2_RTC_GPIO);
350 } 350 }
351 if (tsp2_i2c_rtc.irq == 0) 351 if (tsp2_i2c_rtc.irq == 0)
352 pr_warning("tsp2_init: failed to get RTC IRQ\n"); 352 pr_warn("tsp2_init: failed to get RTC IRQ\n");
353 i2c_register_board_info(0, &tsp2_i2c_rtc, 1); 353 i2c_register_board_info(0, &tsp2_i2c_rtc, 1);
354 354
355 /* register Terastation Pro II specific power-off method */ 355 /* register Terastation Pro II specific power-off method */
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9136797addb2..c725b7cb9875 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -314,7 +314,7 @@ static void __init qnap_ts209_init(void)
314 gpio_free(TS209_RTC_GPIO); 314 gpio_free(TS209_RTC_GPIO);
315 } 315 }
316 if (qnap_ts209_i2c_rtc.irq == 0) 316 if (qnap_ts209_i2c_rtc.irq == 0)
317 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); 317 pr_warn("qnap_ts209_init: failed to get RTC IRQ\n");
318 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); 318 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
319 319
320 /* register tsx09 specific power-off method */ 320 /* register tsx09 specific power-off method */
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 5c079d312015..cf2ab531cabc 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -302,7 +302,7 @@ static void __init qnap_ts409_init(void)
302 gpio_free(TS409_RTC_GPIO); 302 gpio_free(TS409_RTC_GPIO);
303 } 303 }
304 if (qnap_ts409_i2c_rtc.irq == 0) 304 if (qnap_ts409_i2c_rtc.irq == 0)
305 pr_warning("qnap_ts409_init: failed to get RTC IRQ\n"); 305 pr_warn("qnap_ts409_init: failed to get RTC IRQ\n");
306 i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1); 306 i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
307 platform_device_register(&ts409_leds); 307 platform_device_register(&ts409_leds);
308 308
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index db16dae441e2..1b704d35cf5b 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -403,8 +403,8 @@ static void ts78xx_fpga_supports(void)
403 /* enable devices if magic matches */ 403 /* enable devices if magic matches */
404 switch ((ts78xx_fpga.id >> 8) & 0xffffff) { 404 switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
405 case TS7800_FPGA_MAGIC: 405 case TS7800_FPGA_MAGIC:
406 pr_warning("unrecognised FPGA revision 0x%.2x\n", 406 pr_warn("unrecognised FPGA revision 0x%.2x\n",
407 ts78xx_fpga.id & 0xff); 407 ts78xx_fpga.id & 0xff);
408 ts78xx_fpga.supports.ts_rtc.present = 1; 408 ts78xx_fpga.supports.ts_rtc.present = 1;
409 ts78xx_fpga.supports.ts_nand.present = 1; 409 ts78xx_fpga.supports.ts_nand.present = 1;
410 ts78xx_fpga.supports.ts_rng.present = 1; 410 ts78xx_fpga.supports.ts_rng.present = 1;
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index ad5316ae524e..9eb22297cbe1 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -32,7 +32,6 @@ config CPU_S3C2410
32 select S3C2410_DMA if S3C24XX_DMA 32 select S3C2410_DMA if S3C24XX_DMA
33 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ 33 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
34 select S3C2410_PM if PM 34 select S3C2410_PM if PM
35 select SAMSUNG_WDT_RESET
36 help 35 help
37 Support for S3C2410 and S3C2410A family from the S3C24XX line 36 Support for S3C2410 and S3C2410A family from the S3C24XX line
38 of Samsung Mobile CPUs. 37 of Samsung Mobile CPUs.
@@ -76,7 +75,6 @@ config CPU_S3C2442
76config CPU_S3C244X 75config CPU_S3C244X
77 def_bool y 76 def_bool y
78 depends on CPU_S3C2440 || CPU_S3C2442 77 depends on CPU_S3C2440 || CPU_S3C2442
79 select SAMSUNG_WDT_RESET
80 78
81config CPU_S3C2443 79config CPU_S3C2443
82 bool "SAMSUNG S3C2443" 80 bool "SAMSUNG S3C2443"
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 44fa95df9262..bf50328107bd 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -51,7 +51,6 @@
51#include <plat/devs.h> 51#include <plat/devs.h>
52#include <plat/cpu-freq.h> 52#include <plat/cpu-freq.h>
53#include <plat/pwm-core.h> 53#include <plat/pwm-core.h>
54#include <plat/watchdog-reset.h>
55 54
56#include "common.h" 55#include "common.h"
57 56
@@ -513,7 +512,6 @@ struct platform_device s3c2443_device_dma = {
513void __init s3c2410_init_clocks(int xtal) 512void __init s3c2410_init_clocks(int xtal)
514{ 513{
515 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); 514 s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
516 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
517} 515}
518#endif 516#endif
519 517
@@ -535,7 +533,6 @@ void __init s3c2416_init_clocks(int xtal)
535void __init s3c2440_init_clocks(int xtal) 533void __init s3c2440_init_clocks(int xtal)
536{ 534{
537 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); 535 s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
538 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
539} 536}
540#endif 537#endif
541 538
@@ -543,7 +540,6 @@ void __init s3c2440_init_clocks(int xtal)
543void __init s3c2442_init_clocks(int xtal) 540void __init s3c2442_init_clocks(int xtal)
544{ 541{
545 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR); 542 s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
546 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
547} 543}
548#endif 544#endif
549 545
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ac3ff12a0601..c7ac7e61a22e 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -22,7 +22,6 @@ extern int s3c2410a_init(void);
22extern void s3c2410_map_io(void); 22extern void s3c2410_map_io(void);
23extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); 23extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
24extern void s3c2410_init_clocks(int xtal); 24extern void s3c2410_init_clocks(int xtal);
25extern void s3c2410_restart(enum reboot_mode mode, const char *cmd);
26extern void s3c2410_init_irq(void); 25extern void s3c2410_init_irq(void);
27#else 26#else
28#define s3c2410_init_clocks NULL 27#define s3c2410_init_clocks NULL
@@ -38,7 +37,6 @@ extern void s3c2412_map_io(void);
38extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); 37extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
39extern void s3c2412_init_clocks(int xtal); 38extern void s3c2412_init_clocks(int xtal);
40extern int s3c2412_baseclk_add(void); 39extern int s3c2412_baseclk_add(void);
41extern void s3c2412_restart(enum reboot_mode mode, const char *cmd);
42extern void s3c2412_init_irq(void); 40extern void s3c2412_init_irq(void);
43#else 41#else
44#define s3c2412_init_clocks NULL 42#define s3c2412_init_clocks NULL
@@ -53,7 +51,6 @@ extern void s3c2416_map_io(void);
53extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no); 51extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
54extern void s3c2416_init_clocks(int xtal); 52extern void s3c2416_init_clocks(int xtal);
55extern int s3c2416_baseclk_add(void); 53extern int s3c2416_baseclk_add(void);
56extern void s3c2416_restart(enum reboot_mode mode, const char *cmd);
57extern void s3c2416_init_irq(void); 54extern void s3c2416_init_irq(void);
58 55
59extern struct syscore_ops s3c2416_irq_syscore_ops; 56extern struct syscore_ops s3c2416_irq_syscore_ops;
@@ -67,7 +64,6 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
67#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) 64#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
68extern void s3c244x_map_io(void); 65extern void s3c244x_map_io(void);
69extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); 66extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
70extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
71#else 67#else
72#define s3c244x_init_uarts NULL 68#define s3c244x_init_uarts NULL
73#endif 69#endif
@@ -98,7 +94,6 @@ extern void s3c2443_map_io(void);
98extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); 94extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
99extern void s3c2443_init_clocks(int xtal); 95extern void s3c2443_init_clocks(int xtal);
100extern int s3c2443_baseclk_add(void); 96extern int s3c2443_baseclk_add(void);
101extern void s3c2443_restart(enum reboot_mode mode, const char *cmd);
102extern void s3c2443_init_irq(void); 97extern void s3c2443_init_irq(void);
103#else 98#else
104#define s3c2443_init_clocks NULL 99#define s3c2443_init_clocks NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
index c3feff3c0488..ffe37bdb9f59 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
@@ -42,8 +42,6 @@
42#define S3C2443_URSTCON S3C2443_CLKREG(0x88) 42#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C) 43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
44 44
45#define S3C2443_SWRST_RESET (0x533c2443)
46
47#define S3C2443_PLLCON_OFF (1<<24) 45#define S3C2443_PLLCON_OFF (1<<24)
48 46
49#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7) 47#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 5157e250dd13..3e63777a109f 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -247,5 +247,4 @@ MACHINE_START(AML_M5900, "AML_M5900")
247 .init_irq = s3c2410_init_irq, 247 .init_irq = s3c2410_init_irq,
248 .init_machine = amlm5900_init, 248 .init_machine = amlm5900_init,
249 .init_time = amlm5900_init_time, 249 .init_time = amlm5900_init_time,
250 .restart = s3c2410_restart,
251MACHINE_END 250MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index e053581cab0b..d03df0df01fa 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -430,5 +430,4 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
430 .init_machine = anubis_init, 430 .init_machine = anubis_init,
431 .init_irq = s3c2440_init_irq, 431 .init_irq = s3c2440_init_irq,
432 .init_time = anubis_init_time, 432 .init_time = anubis_init_time,
433 .restart = s3c244x_restart,
434MACHINE_END 433MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index 9db768f448a5..9ae170fef2a7 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -218,5 +218,4 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
218 .init_machine = at2440evb_init, 218 .init_machine = at2440evb_init,
219 .init_irq = s3c2440_init_irq, 219 .init_irq = s3c2440_init_irq,
220 .init_time = at2440evb_init_time, 220 .init_time = at2440evb_init_time,
221 .restart = s3c244x_restart,
222MACHINE_END 221MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index f9112b801a33..ed07cf392d4b 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -591,5 +591,4 @@ MACHINE_START(BAST, "Simtec-BAST")
591 .init_irq = s3c2410_init_irq, 591 .init_irq = s3c2410_init_irq,
592 .init_machine = bast_init, 592 .init_machine = bast_init,
593 .init_time = bast_init_time, 593 .init_time = bast_init_time,
594 .restart = s3c2410_restart,
595MACHINE_END 594MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index fc3a08d0cb3f..6d1e0b9c5b27 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -597,5 +597,4 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
597 .init_irq = s3c2442_init_irq, 597 .init_irq = s3c2442_init_irq,
598 .init_machine = gta02_machine_init, 598 .init_machine = gta02_machine_init,
599 .init_time = gta02_init_time, 599 .init_time = gta02_init_time,
600 .restart = s3c244x_restart,
601MACHINE_END 600MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index c9a99bbad545..d35ddc1d9991 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -747,5 +747,4 @@ MACHINE_START(H1940, "IPAQ-H1940")
747 .init_irq = s3c2410_init_irq, 747 .init_irq = s3c2410_init_irq,
748 .init_machine = h1940_init, 748 .init_machine = h1940_init,
749 .init_time = h1940_init_time, 749 .init_time = h1940_init_time,
750 .restart = s3c2410_restart,
751MACHINE_END 750MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 7804d3c6991b..7d99fe8f6157 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -670,5 +670,4 @@ MACHINE_START(JIVE, "JIVE")
670 .map_io = jive_map_io, 670 .map_io = jive_map_io,
671 .init_machine = jive_machine_init, 671 .init_machine = jive_machine_init,
672 .init_time = jive_init_time, 672 .init_time = jive_init_time,
673 .restart = s3c2412_restart,
674MACHINE_END 673MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 5cc40ec1d254..a8521684a7f5 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -695,5 +695,4 @@ MACHINE_START(MINI2440, "MINI2440")
695 .init_machine = mini2440_init, 695 .init_machine = mini2440_init,
696 .init_irq = s3c2440_init_irq, 696 .init_irq = s3c2440_init_irq,
697 .init_time = mini2440_init_time, 697 .init_time = mini2440_init_time,
698 .restart = s3c244x_restart,
699MACHINE_END 698MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 3ac2a54348d6..171c1f11fd22 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -599,7 +599,6 @@ MACHINE_START(N30, "Acer-N30")
599 .init_machine = n30_init, 599 .init_machine = n30_init,
600 .init_irq = s3c2410_init_irq, 600 .init_irq = s3c2410_init_irq,
601 .map_io = n30_map_io, 601 .map_io = n30_map_io,
602 .restart = s3c2410_restart,
603MACHINE_END 602MACHINE_END
604 603
605MACHINE_START(N35, "Acer-N35") 604MACHINE_START(N35, "Acer-N35")
@@ -610,5 +609,4 @@ MACHINE_START(N35, "Acer-N35")
610 .init_machine = n30_init, 609 .init_machine = n30_init,
611 .init_irq = s3c2410_init_irq, 610 .init_irq = s3c2410_init_irq,
612 .map_io = n30_map_io, 611 .map_io = n30_map_io,
613 .restart = s3c2410_restart,
614MACHINE_END 612MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index c82c281ce351..2a61d13dcd6c 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -159,5 +159,4 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
159 .init_machine = nexcoder_init, 159 .init_machine = nexcoder_init,
160 .init_irq = s3c2440_init_irq, 160 .init_irq = s3c2440_init_irq,
161 .init_time = nexcoder_init_time, 161 .init_time = nexcoder_init_time,
162 .restart = s3c244x_restart,
163MACHINE_END 162MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 189147b80eca..2f6fdc326835 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -412,5 +412,4 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
412 .init_irq = s3c2440_init_irq, 412 .init_irq = s3c2440_init_irq,
413 .init_machine = osiris_init, 413 .init_machine = osiris_init,
414 .init_time = osiris_init_time, 414 .init_time = osiris_init_time,
415 .restart = s3c244x_restart,
416MACHINE_END 415MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 45833001186d..345a484b93cc 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -122,5 +122,4 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
122 .init_machine = otom11_init, 122 .init_machine = otom11_init,
123 .init_irq = s3c2410_init_irq, 123 .init_irq = s3c2410_init_irq,
124 .init_time = otom11_init_time, 124 .init_time = otom11_init_time,
125 .restart = s3c2410_restart,
126MACHINE_END 125MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 228c9094519d..984516e8307a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -352,5 +352,4 @@ MACHINE_START(QT2410, "QT2410")
352 .init_irq = s3c2410_init_irq, 352 .init_irq = s3c2410_init_irq,
353 .init_machine = qt2410_machine_init, 353 .init_machine = qt2410_machine_init,
354 .init_time = qt2410_init_time, 354 .init_time = qt2410_init_time,
355 .restart = s3c2410_restart,
356MACHINE_END 355MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index e2c6541909c1..c3f2682d0c62 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -812,5 +812,4 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
812 .init_irq = s3c2442_init_irq, 812 .init_irq = s3c2442_init_irq,
813 .init_machine = rx1950_init_machine, 813 .init_machine = rx1950_init_machine,
814 .init_time = rx1950_init_time, 814 .init_time = rx1950_init_time,
815 .restart = s3c244x_restart,
816MACHINE_END 815MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 6e749ec3a2ea..cf55196f89ca 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -215,5 +215,4 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
215 .init_irq = s3c2440_init_irq, 215 .init_irq = s3c2440_init_irq,
216 .init_machine = rx3715_init_machine, 216 .init_machine = rx3715_init_machine,
217 .init_time = rx3715_init_time, 217 .init_time = rx3715_init_time,
218 .restart = s3c244x_restart,
219MACHINE_END 218MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index e4dcb9aa2ca2..f886478b88c5 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -51,5 +51,4 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
51 .map_io = s3c2416_dt_map_io, 51 .map_io = s3c2416_dt_map_io,
52 .init_irq = irqchip_init, 52 .init_irq = irqchip_init,
53 .init_machine = s3c2416_dt_machine_init, 53 .init_machine = s3c2416_dt_machine_init,
54 .restart = s3c2416_restart,
55MACHINE_END 54MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index 419fadd6e446..27dd6605e395 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -124,5 +124,4 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
124 .init_irq = s3c2410_init_irq, 124 .init_irq = s3c2410_init_irq,
125 .init_machine = smdk2410_init, 125 .init_machine = smdk2410_init,
126 .init_time = smdk2410_init_time, 126 .init_time = smdk2410_init_time,
127 .restart = s3c2410_restart,
128MACHINE_END 127MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 10726bf84920..586e4a3b8d5d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -138,7 +138,6 @@ MACHINE_START(S3C2413, "S3C2413")
138 .map_io = smdk2413_map_io, 138 .map_io = smdk2413_map_io,
139 .init_machine = smdk2413_machine_init, 139 .init_machine = smdk2413_machine_init,
140 .init_time = samsung_timer_init, 140 .init_time = samsung_timer_init,
141 .restart = s3c2412_restart,
142MACHINE_END 141MACHINE_END
143 142
144MACHINE_START(SMDK2412, "SMDK2412") 143MACHINE_START(SMDK2412, "SMDK2412")
@@ -150,7 +149,6 @@ MACHINE_START(SMDK2412, "SMDK2412")
150 .map_io = smdk2413_map_io, 149 .map_io = smdk2413_map_io,
151 .init_machine = smdk2413_machine_init, 150 .init_machine = smdk2413_machine_init,
152 .init_time = samsung_timer_init, 151 .init_time = samsung_timer_init,
153 .restart = s3c2412_restart,
154MACHINE_END 152MACHINE_END
155 153
156MACHINE_START(SMDK2413, "SMDK2413") 154MACHINE_START(SMDK2413, "SMDK2413")
@@ -162,5 +160,4 @@ MACHINE_START(SMDK2413, "SMDK2413")
162 .map_io = smdk2413_map_io, 160 .map_io = smdk2413_map_io,
163 .init_machine = smdk2413_machine_init, 161 .init_machine = smdk2413_machine_init,
164 .init_time = smdk2413_init_time, 162 .init_time = smdk2413_init_time,
165 .restart = s3c2412_restart,
166MACHINE_END 163MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 24189e8e8560..86394f72d29e 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -262,5 +262,4 @@ MACHINE_START(SMDK2416, "SMDK2416")
262 .map_io = smdk2416_map_io, 262 .map_io = smdk2416_map_io,
263 .init_machine = smdk2416_machine_init, 263 .init_machine = smdk2416_machine_init,
264 .init_time = smdk2416_init_time, 264 .init_time = smdk2416_init_time,
265 .restart = s3c2416_restart,
266MACHINE_END 265MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 5fb89c0ae17a..9bb96bfbb420 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -185,5 +185,4 @@ MACHINE_START(S3C2440, "SMDK2440")
185 .map_io = smdk2440_map_io, 185 .map_io = smdk2440_map_io,
186 .init_machine = smdk2440_machine_init, 186 .init_machine = smdk2440_machine_init,
187 .init_time = smdk2440_init_time, 187 .init_time = smdk2440_init_time,
188 .restart = s3c244x_restart,
189MACHINE_END 188MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 0ed77614dcfe..87fe5c5b8073 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -150,5 +150,4 @@ MACHINE_START(SMDK2443, "SMDK2443")
150 .map_io = smdk2443_map_io, 150 .map_io = smdk2443_map_io,
151 .init_machine = smdk2443_machine_init, 151 .init_machine = smdk2443_machine_init,
152 .init_time = smdk2443_init_time, 152 .init_time = smdk2443_init_time,
153 .restart = s3c2443_restart,
154MACHINE_END 153MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index c616ca2d409e..2deb62f92fb2 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -157,5 +157,4 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
157 .init_irq = s3c2410_init_irq, 157 .init_irq = s3c2410_init_irq,
158 .init_machine = tct_hammer_init, 158 .init_machine = tct_hammer_init,
159 .init_time = tct_hammer_init_time, 159 .init_time = tct_hammer_init_time,
160 .restart = s3c2410_restart,
161MACHINE_END 160MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index f88c584c3001..89f32bd3f01b 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -340,5 +340,4 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
340 .init_machine = vr1000_init, 340 .init_machine = vr1000_init,
341 .init_irq = s3c2410_init_irq, 341 .init_irq = s3c2410_init_irq,
342 .init_time = vr1000_init_time, 342 .init_time = vr1000_init_time,
343 .restart = s3c2410_restart,
344MACHINE_END 343MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 9d4f64750698..b4460d5f7011 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -165,5 +165,4 @@ MACHINE_START(VSTMS, "VSTMS")
165 .init_machine = vstms_init, 165 .init_machine = vstms_init,
166 .map_io = vstms_map_io, 166 .map_io = vstms_map_io,
167 .init_time = vstms_init_time, 167 .init_time = vstms_init_time,
168 .restart = s3c2412_restart,
169MACHINE_END 168MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 5ffe828cd659..2a6985a4a0ff 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -42,7 +42,6 @@
42#include <plat/cpu.h> 42#include <plat/cpu.h>
43#include <plat/devs.h> 43#include <plat/devs.h>
44#include <plat/pm.h> 44#include <plat/pm.h>
45#include <plat/watchdog-reset.h>
46 45
47#include <plat/gpio-core.h> 46#include <plat/gpio-core.h>
48#include <plat/gpio-cfg.h> 47#include <plat/gpio-cfg.h>
@@ -135,15 +134,3 @@ int __init s3c2410a_init(void)
135 s3c2410_dev.bus = &s3c2410a_subsys; 134 s3c2410_dev.bus = &s3c2410a_subsys;
136 return s3c2410_init(); 135 return s3c2410_init();
137} 136}
138
139void s3c2410_restart(enum reboot_mode mode, const char *cmd)
140{
141 if (mode == REBOOT_SOFT) {
142 soft_restart(0);
143 }
144
145 samsung_wdt_reset();
146
147 /* we'll take a jump through zero as a poor second */
148 soft_restart(0);
149}
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 569f3f5a6c71..ecf2c77ab88b 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -48,9 +48,6 @@
48#include "regs-dsc.h" 48#include "regs-dsc.h"
49#include "s3c2412-power.h" 49#include "s3c2412-power.h"
50 50
51#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
52#define S3C2412_SWRST_RESET (0x533C2412)
53
54#ifndef CONFIG_CPU_S3C2412_ONLY 51#ifndef CONFIG_CPU_S3C2412_ONLY
55void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; 52void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
56 53
@@ -128,26 +125,6 @@ static void s3c2412_idle(void)
128 cpu_do_idle(); 125 cpu_do_idle();
129} 126}
130 127
131void s3c2412_restart(enum reboot_mode mode, const char *cmd)
132{
133 if (mode == REBOOT_SOFT)
134 soft_restart(0);
135
136 /* errata "Watch-dog/Software Reset Problem" specifies that
137 * this reset must be done with the SYSCLK sourced from
138 * EXTCLK instead of FOUT to avoid a glitch in the reset
139 * mechanism.
140 *
141 * See the watchdog section of the S3C2412 manual for more
142 * information on this fix.
143 */
144
145 __raw_writel(0x00, S3C2412_CLKSRC);
146 __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
147
148 mdelay(1);
149}
150
151/* s3c2412_map_io 128/* s3c2412_map_io
152 * 129 *
153 * register the standard cpu IO areas, and any passed in from the 130 * register the standard cpu IO areas, and any passed in from the
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 9fe260ae11e1..bfd4da86deb8 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -81,14 +81,6 @@ static struct device s3c2416_dev = {
81 .bus = &s3c2416_subsys, 81 .bus = &s3c2416_subsys,
82}; 82};
83 83
84void s3c2416_restart(enum reboot_mode mode, const char *cmd)
85{
86 if (mode == REBOOT_SOFT)
87 soft_restart(0);
88
89 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
90}
91
92int __init s3c2416_init(void) 84int __init s3c2416_init(void)
93{ 85{
94 printk(KERN_INFO "S3C2416: Initializing architecture\n"); 86 printk(KERN_INFO "S3C2416: Initializing architecture\n");
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index c7a804d0348e..87b6b89d8ee7 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -61,14 +61,6 @@ static struct device s3c2443_dev = {
61 .bus = &s3c2443_subsys, 61 .bus = &s3c2443_subsys,
62}; 62};
63 63
64void s3c2443_restart(enum reboot_mode mode, const char *cmd)
65{
66 if (mode == REBOOT_SOFT)
67 soft_restart(0);
68
69 __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
70}
71
72int __init s3c2443_init(void) 64int __init s3c2443_init(void)
73{ 65{
74 printk("S3C2443: Initialising architecture\n"); 66 printk("S3C2443: Initialising architecture\n");
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index d1c3e65785a1..177f97802745 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -42,7 +42,6 @@
42#include <plat/cpu.h> 42#include <plat/cpu.h>
43#include <plat/pm.h> 43#include <plat/pm.h>
44#include <plat/nand-core.h> 44#include <plat/nand-core.h>
45#include <plat/watchdog-reset.h>
46 45
47#include "common.h" 46#include "common.h"
48#include "regs-dsc.h" 47#include "regs-dsc.h"
@@ -137,14 +136,3 @@ struct syscore_ops s3c244x_pm_syscore_ops = {
137 .suspend = s3c244x_suspend, 136 .suspend = s3c244x_suspend,
138 .resume = s3c244x_resume, 137 .resume = s3c244x_resume,
139}; 138};
140
141void s3c244x_restart(enum reboot_mode mode, const char *cmd)
142{
143 if (mode == REBOOT_SOFT)
144 soft_restart(0);
145
146 samsung_wdt_reset();
147
148 /* we'll take a jump through zero as a poor second */
149 soft_restart(0);
150}
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 123163dd2ab0..21b4b13c5ab7 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -24,9 +24,8 @@
24 24
25#include <plat/pm-common.h> 25#include <plat/pm-common.h>
26 26
27#include <mach/regs-clock.h>
28
29#include "common.h" 27#include "common.h"
28#include "regs-clock.h"
30 29
31static struct sleep_save s5pv210_core_save[] = { 30static struct sleep_save s5pv210_core_save[] = {
32 /* Clock ETC */ 31 /* Clock ETC */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h
index b14ffcd7f6cc..4640f0f03c12 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/regs-clock.h
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h 1/*
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 3 * http://www.samsung.com/
5 * 4 *
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
index 53feff33d129..43eb1eaea0c9 100644
--- a/arch/arm/mach-s5pv210/s5pv210.c
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -18,9 +18,9 @@
18#include <asm/system_misc.h> 18#include <asm/system_misc.h>
19 19
20#include <plat/map-base.h> 20#include <plat/map-base.h>
21#include <mach/regs-clock.h>
22 21
23#include "common.h" 22#include "common.h"
23#include "regs-clock.h"
24 24
25static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname, 25static int __init s5pv210_fdt_map_sys(unsigned long node, const char *uname,
26 int depth, void *data) 26 int depth, void *data)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1e6c51c7c2d5..efc49dabbf2f 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,30 @@
1config ARCH_SHMOBILE 1config ARCH_SHMOBILE
2 bool 2 bool
3 3
4config PM_RCAR
5 bool
6
7config PM_RMOBILE
8 bool
9
10config ARCH_RCAR_GEN1
11 bool
12 select PM_RCAR if PM || SMP
13 select RENESAS_INTC_IRQPIN
14 select SYS_SUPPORTS_SH_TMU
15
16config ARCH_RCAR_GEN2
17 bool
18 select PM_RCAR if PM || SMP
19 select RENESAS_IRQC
20 select SYS_SUPPORTS_SH_CMT
21
22config ARCH_RMOBILE
23 bool
24 select PM_RMOBILE if PM && !ARCH_SHMOBILE_MULTI
25 select SYS_SUPPORTS_SH_CMT
26 select SYS_SUPPORTS_SH_TMU
27
4menuconfig ARCH_SHMOBILE_MULTI 28menuconfig ARCH_SHMOBILE_MULTI
5 bool "Renesas ARM SoCs" if ARCH_MULTI_V7 29 bool "Renesas ARM SoCs" if ARCH_MULTI_V7
6 depends on MMU 30 depends on MMU
@@ -28,18 +52,15 @@ config ARCH_R7S72100
28 52
29config ARCH_R8A7779 53config ARCH_R8A7779
30 bool "R-Car H1 (R8A77790)" 54 bool "R-Car H1 (R8A77790)"
31 select RENESAS_INTC_IRQPIN 55 select ARCH_RCAR_GEN1
32 select SYS_SUPPORTS_SH_TMU
33 56
34config ARCH_R8A7790 57config ARCH_R8A7790
35 bool "R-Car H2 (R8A77900)" 58 bool "R-Car H2 (R8A77900)"
36 select RENESAS_IRQC 59 select ARCH_RCAR_GEN2
37 select SYS_SUPPORTS_SH_CMT
38 60
39config ARCH_R8A7791 61config ARCH_R8A7791
40 bool "R-Car M2 (R8A77910)" 62 bool "R-Car M2-W (R8A77910)"
41 select RENESAS_IRQC 63 select ARCH_RCAR_GEN2
42 select SYS_SUPPORTS_SH_CMT
43 64
44comment "Renesas ARM SoCs Board Type" 65comment "Renesas ARM SoCs Board Type"
45 66
@@ -71,84 +92,60 @@ comment "Renesas ARM SoCs System Type"
71 92
72config ARCH_SH7372 93config ARCH_SH7372
73 bool "SH-Mobile AP4 (SH7372)" 94 bool "SH-Mobile AP4 (SH7372)"
95 select ARCH_RMOBILE
74 select ARCH_WANT_OPTIONAL_GPIOLIB 96 select ARCH_WANT_OPTIONAL_GPIOLIB
75 select ARM_CPU_SUSPEND if PM || CPU_IDLE 97 select ARM_CPU_SUSPEND if PM || CPU_IDLE
76 select CPU_V7
77 select SH_CLK_CPG
78 select SH_INTC 98 select SH_INTC
79 select SYS_SUPPORTS_SH_CMT
80 select SYS_SUPPORTS_SH_TMU
81 99
82config ARCH_SH73A0 100config ARCH_SH73A0
83 bool "SH-Mobile AG5 (R8A73A00)" 101 bool "SH-Mobile AG5 (R8A73A00)"
102 select ARCH_RMOBILE
84 select ARCH_WANT_OPTIONAL_GPIOLIB 103 select ARCH_WANT_OPTIONAL_GPIOLIB
85 select ARM_GIC 104 select ARM_GIC
86 select CPU_V7
87 select I2C 105 select I2C
88 select SH_CLK_CPG
89 select SH_INTC 106 select SH_INTC
90 select RENESAS_INTC_IRQPIN 107 select RENESAS_INTC_IRQPIN
91 select SYS_SUPPORTS_SH_CMT
92 select SYS_SUPPORTS_SH_TMU
93 108
94config ARCH_R8A73A4 109config ARCH_R8A73A4
95 bool "R-Mobile APE6 (R8A73A40)" 110 bool "R-Mobile APE6 (R8A73A40)"
111 select ARCH_RMOBILE
96 select ARCH_WANT_OPTIONAL_GPIOLIB 112 select ARCH_WANT_OPTIONAL_GPIOLIB
97 select ARM_GIC 113 select ARM_GIC
98 select CPU_V7
99 select SH_CLK_CPG
100 select RENESAS_IRQC 114 select RENESAS_IRQC
101 select SYS_SUPPORTS_SH_CMT
102 select SYS_SUPPORTS_SH_TMU
103 115
104config ARCH_R8A7740 116config ARCH_R8A7740
105 bool "R-Mobile A1 (R8A77400)" 117 bool "R-Mobile A1 (R8A77400)"
118 select ARCH_RMOBILE
106 select ARCH_WANT_OPTIONAL_GPIOLIB 119 select ARCH_WANT_OPTIONAL_GPIOLIB
107 select ARM_GIC 120 select ARM_GIC
108 select CPU_V7
109 select SH_CLK_CPG
110 select RENESAS_INTC_IRQPIN 121 select RENESAS_INTC_IRQPIN
111 select SYS_SUPPORTS_SH_CMT
112 select SYS_SUPPORTS_SH_TMU
113 122
114config ARCH_R8A7778 123config ARCH_R8A7778
115 bool "R-Car M1A (R8A77781)" 124 bool "R-Car M1A (R8A77781)"
125 select ARCH_RCAR_GEN1
116 select ARCH_WANT_OPTIONAL_GPIOLIB 126 select ARCH_WANT_OPTIONAL_GPIOLIB
117 select CPU_V7
118 select SH_CLK_CPG
119 select ARM_GIC 127 select ARM_GIC
120 select SYS_SUPPORTS_SH_TMU
121 select RENESAS_INTC_IRQPIN
122 128
123config ARCH_R8A7779 129config ARCH_R8A7779
124 bool "R-Car H1 (R8A77790)" 130 bool "R-Car H1 (R8A77790)"
131 select ARCH_RCAR_GEN1
125 select ARCH_WANT_OPTIONAL_GPIOLIB 132 select ARCH_WANT_OPTIONAL_GPIOLIB
126 select ARM_GIC 133 select ARM_GIC
127 select CPU_V7
128 select SH_CLK_CPG
129 select RENESAS_INTC_IRQPIN
130 select SYS_SUPPORTS_SH_TMU
131 134
132config ARCH_R8A7790 135config ARCH_R8A7790
133 bool "R-Car H2 (R8A77900)" 136 bool "R-Car H2 (R8A77900)"
137 select ARCH_RCAR_GEN2
134 select ARCH_WANT_OPTIONAL_GPIOLIB 138 select ARCH_WANT_OPTIONAL_GPIOLIB
135 select ARM_GIC 139 select ARM_GIC
136 select CPU_V7
137 select MIGHT_HAVE_PCI 140 select MIGHT_HAVE_PCI
138 select SH_CLK_CPG
139 select RENESAS_IRQC
140 select SYS_SUPPORTS_SH_CMT
141 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 141 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
142 142
143config ARCH_R8A7791 143config ARCH_R8A7791
144 bool "R-Car M2 (R8A77910)" 144 bool "R-Car M2-W (R8A77910)"
145 select ARCH_RCAR_GEN2
145 select ARCH_WANT_OPTIONAL_GPIOLIB 146 select ARCH_WANT_OPTIONAL_GPIOLIB
146 select ARM_GIC 147 select ARM_GIC
147 select CPU_V7
148 select MIGHT_HAVE_PCI 148 select MIGHT_HAVE_PCI
149 select SH_CLK_CPG
150 select RENESAS_IRQC
151 select SYS_SUPPORTS_SH_CMT
152 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 149 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
153 150
154config ARCH_R7S72100 151config ARCH_R7S72100
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe3878a1a69a..7b259ce60beb 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -8,15 +8,14 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/incl
8obj-y := timer.o console.o 8obj-y := timer.o console.o
9 9
10# CPU objects 10# CPU objects
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o pm-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o 12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o
13obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o 13obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
14obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o 14obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
15obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o 15obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
16obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o 16obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o
17obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o 17obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o pm-r8a7790.o
18obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o setup-rcar-gen2.o 18obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o pm-r8a7791.o
19obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o setup-rcar-gen2.o
20obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o 19obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
21obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o 20obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
22 21
@@ -36,8 +35,9 @@ endif
36 35
37# CPU reset vector handling objects 36# CPU reset vector handling objects
38cpu-y := platsmp.o headsmp.o 37cpu-y := platsmp.o headsmp.o
39cpu-$(CONFIG_ARCH_R8A7790) += platsmp-apmu.o 38
40cpu-$(CONFIG_ARCH_R8A7791) += platsmp-apmu.o 39# Shared SoC family objects
40obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
41 41
42# SMP objects 42# SMP objects
43smp-y := $(cpu-y) 43smp-y := $(cpu-y)
@@ -51,15 +51,11 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
51obj-$(CONFIG_SUSPEND) += suspend.o 51obj-$(CONFIG_SUSPEND) += suspend.o
52obj-$(CONFIG_CPU_IDLE) += cpuidle.o 52obj-$(CONFIG_CPU_IDLE) += cpuidle.o
53obj-$(CONFIG_CPU_FREQ) += cpufreq.o 53obj-$(CONFIG_CPU_FREQ) += cpufreq.o
54obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o pm-rmobile.o 54obj-$(CONFIG_PM_RCAR) += pm-rcar.o
55obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o 55obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
56obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o
57obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o pm-rcar.o
58obj-$(CONFIG_ARCH_R8A7790) += pm-r8a7790.o pm-rcar.o $(cpu-y)
59obj-$(CONFIG_ARCH_R8A7791) += pm-r8a7791.o pm-rcar.o $(cpu-y)
60 56
61# IRQ objects 57# special sh7372 handling for IRQ objects and low level sleep code
62obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 58obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
63 59
64# Board objects 60# Board objects
65ifdef CONFIG_ARCH_SHMOBILE_MULTI 61ifdef CONFIG_ARCH_SHMOBILE_MULTI
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 6dbaad611a92..e70983534403 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1231,6 +1231,10 @@ clock_error:
1231#define GPIO_PORT8CR IOMEM(0xe6050008) 1231#define GPIO_PORT8CR IOMEM(0xe6050008)
1232static void __init eva_init(void) 1232static void __init eva_init(void)
1233{ 1233{
1234 static struct pm_domain_device domain_devices[] __initdata = {
1235 { "A4LC", &lcdc0_device },
1236 { "A4LC", &hdmi_lcdc_device },
1237 };
1234 struct platform_device *usb = NULL; 1238 struct platform_device *usb = NULL;
1235 1239
1236 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 1240 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -1316,8 +1320,8 @@ static void __init eva_init(void)
1316 platform_add_devices(eva_devices, 1320 platform_add_devices(eva_devices,
1317 ARRAY_SIZE(eva_devices)); 1321 ARRAY_SIZE(eva_devices));
1318 1322
1319 rmobile_add_device_to_domain("A4LC", &lcdc0_device); 1323 rmobile_add_devices_to_domains(domain_devices,
1320 rmobile_add_device_to_domain("A4LC", &hdmi_lcdc_device); 1324 ARRAY_SIZE(domain_devices));
1321 if (usb) 1325 if (usb)
1322 rmobile_add_device_to_domain("A3SP", usb); 1326 rmobile_add_device_to_domain("A3SP", usb);
1323 1327
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 79f448e93abb..d47b2623267b 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1420,7 +1420,7 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
1420#define USCCR1 IOMEM(0xE6058144) 1420#define USCCR1 IOMEM(0xE6058144)
1421static void __init mackerel_init(void) 1421static void __init mackerel_init(void)
1422{ 1422{
1423 struct pm_domain_device domain_devices[] = { 1423 static struct pm_domain_device domain_devices[] __initdata = {
1424 { "A4LC", &lcdc_device, }, 1424 { "A4LC", &lcdc_device, },
1425 { "A4LC", &hdmi_lcdc_device, }, 1425 { "A4LC", &hdmi_lcdc_device, },
1426 { "A4LC", &meram_device, }, 1426 { "A4LC", &meram_device, },
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index a0d44d537fa0..3d507149a6c4 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -34,23 +34,21 @@ static int r8a7740_pd_a3sp_suspend(void)
34 34
35static struct rmobile_pm_domain r8a7740_pm_domains[] = { 35static struct rmobile_pm_domain r8a7740_pm_domains[] = {
36 { 36 {
37 .genpd.name = "A4LC",
38 .bit_shift = 1,
39 }, {
37 .genpd.name = "A4S", 40 .genpd.name = "A4S",
38 .bit_shift = 10, 41 .bit_shift = 10,
39 .gov = &pm_domain_always_on_gov, 42 .gov = &pm_domain_always_on_gov,
40 .no_debug = true, 43 .no_debug = true,
41 .suspend = r8a7740_pd_a4s_suspend, 44 .suspend = r8a7740_pd_a4s_suspend,
42 }, 45 }, {
43 {
44 .genpd.name = "A3SP", 46 .genpd.name = "A3SP",
45 .bit_shift = 11, 47 .bit_shift = 11,
46 .gov = &pm_domain_always_on_gov, 48 .gov = &pm_domain_always_on_gov,
47 .no_debug = true, 49 .no_debug = true,
48 .suspend = r8a7740_pd_a3sp_suspend, 50 .suspend = r8a7740_pd_a3sp_suspend,
49 }, 51 },
50 {
51 .genpd.name = "A4LC",
52 .bit_shift = 1,
53 },
54}; 52};
55 53
56void __init r8a7740_init_pm_domains(void) 54void __init r8a7740_init_pm_domains(void)
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
index 34b8a5674f85..00022ee56f80 100644
--- a/arch/arm/mach-shmobile/pm-rcar.c
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -31,8 +31,6 @@
31#define SYSCISR_RETRIES 1000 31#define SYSCISR_RETRIES 1000
32#define SYSCISR_DELAY_US 1 32#define SYSCISR_DELAY_US 1
33 33
34#if defined(CONFIG_PM) || defined(CONFIG_SMP)
35
36static void __iomem *rcar_sysc_base; 34static void __iomem *rcar_sysc_base;
37static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */ 35static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
38 36
@@ -137,5 +135,3 @@ void __iomem *rcar_sysc_init(phys_addr_t base)
137 135
138 return rcar_sysc_base; 136 return rcar_sysc_base;
139} 137}
140
141#endif /* CONFIG_PM || CONFIG_SMP */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index ebdd16e94a84..a88079af7914 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -27,7 +27,6 @@
27#define PSTR_RETRIES 100 27#define PSTR_RETRIES 100
28#define PSTR_DELAY_US 10 28#define PSTR_DELAY_US 10
29 29
30#ifdef CONFIG_PM
31static int rmobile_pd_power_down(struct generic_pm_domain *genpd) 30static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
32{ 31{
33 struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd); 32 struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
@@ -151,4 +150,3 @@ void rmobile_add_devices_to_domains(struct pm_domain_device data[],
151 rmobile_add_device_to_domain_td(data[j].domain_name, 150 rmobile_add_device_to_domain_td(data[j].domain_name,
152 data[j].pdev, &latencies); 151 data[j].pdev, &latencies);
153} 152}
154#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h
index 690553a06887..8f66b343162b 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.h
+++ b/arch/arm/mach-shmobile/pm-rmobile.h
@@ -36,7 +36,7 @@ struct pm_domain_device {
36 struct platform_device *pdev; 36 struct platform_device *pdev;
37}; 37};
38 38
39#ifdef CONFIG_PM 39#ifdef CONFIG_PM_RMOBILE
40extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num); 40extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);
41extern void rmobile_add_device_to_domain_td(const char *domain_name, 41extern void rmobile_add_device_to_domain_td(const char *domain_name,
42 struct platform_device *pdev, 42 struct platform_device *pdev,
@@ -58,6 +58,6 @@ extern void rmobile_add_devices_to_domains(struct pm_domain_device data[],
58 58
59static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[], 59static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],
60 int size) {} 60 int size) {}
61#endif /* CONFIG_PM */ 61#endif /* CONFIG_PM_RMOBILE */
62 62
63#endif /* PM_RMOBILE_H */ 63#endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 3d5eacaba3e6..30df532fcaa0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -747,6 +747,19 @@ static void r8a7740_i2c_workaround(struct platform_device *pdev)
747 747
748void __init r8a7740_add_standard_devices(void) 748void __init r8a7740_add_standard_devices(void)
749{ 749{
750 static struct pm_domain_device domain_devices[] __initdata = {
751 { "A3SP", &scif0_device },
752 { "A3SP", &scif1_device },
753 { "A3SP", &scif2_device },
754 { "A3SP", &scif3_device },
755 { "A3SP", &scif4_device },
756 { "A3SP", &scif5_device },
757 { "A3SP", &scif6_device },
758 { "A3SP", &scif7_device },
759 { "A3SP", &scif8_device },
760 { "A3SP", &i2c1_device },
761 };
762
750 /* I2C work-around */ 763 /* I2C work-around */
751 r8a7740_i2c_workaround(&i2c0_device); 764 r8a7740_i2c_workaround(&i2c0_device);
752 r8a7740_i2c_workaround(&i2c1_device); 765 r8a7740_i2c_workaround(&i2c1_device);
@@ -762,17 +775,8 @@ void __init r8a7740_add_standard_devices(void)
762 ARRAY_SIZE(r8a7740_late_devices)); 775 ARRAY_SIZE(r8a7740_late_devices));
763 776
764 /* add devices to PM domain */ 777 /* add devices to PM domain */
765 778 rmobile_add_devices_to_domains(domain_devices,
766 rmobile_add_device_to_domain("A3SP", &scif0_device); 779 ARRAY_SIZE(domain_devices));
767 rmobile_add_device_to_domain("A3SP", &scif1_device);
768 rmobile_add_device_to_domain("A3SP", &scif2_device);
769 rmobile_add_device_to_domain("A3SP", &scif3_device);
770 rmobile_add_device_to_domain("A3SP", &scif4_device);
771 rmobile_add_device_to_domain("A3SP", &scif5_device);
772 rmobile_add_device_to_domain("A3SP", &scif6_device);
773 rmobile_add_device_to_domain("A3SP", &scif7_device);
774 rmobile_add_device_to_domain("A3SP", &scif8_device);
775 rmobile_add_device_to_domain("A3SP", &i2c1_device);
776} 780}
777 781
778void __init r8a7740_add_early_devices(void) 782void __init r8a7740_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 9cdfcdfd38fc..a04fa5fd00fd 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -927,7 +927,7 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
927 927
928void __init sh7372_add_standard_devices(void) 928void __init sh7372_add_standard_devices(void)
929{ 929{
930 struct pm_domain_device domain_devices[] = { 930 static struct pm_domain_device domain_devices[] __initdata = {
931 { "A3RV", &vpu_device, }, 931 { "A3RV", &vpu_device, },
932 { "A4MP", &spu0_device, }, 932 { "A4MP", &spu0_device, },
933 { "A4MP", &spu1_device, }, 933 { "A4MP", &spu1_device, },
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 42d4753683ce..d7598aeed803 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,81 +12,9 @@
12 12
13#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
14#include <linux/clocksource.h> 14#include <linux/clocksource.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/init.h> 15#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/io.h>
22#include <linux/reboot.h>
23 16
24#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/system_misc.h>
27
28#define SUN4I_WATCHDOG_CTRL_REG 0x00
29#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
30#define SUN4I_WATCHDOG_MODE_REG 0x04
31#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
32#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
33
34#define SUN6I_WATCHDOG1_IRQ_REG 0x00
35#define SUN6I_WATCHDOG1_CTRL_REG 0x10
36#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
37#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
38#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
39#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
40#define SUN6I_WATCHDOG1_MODE_REG 0x18
41#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
42
43static void __iomem *wdt_base;
44
45static void sun4i_restart(enum reboot_mode mode, const char *cmd)
46{
47 if (!wdt_base)
48 return;
49
50 /* Enable timer and set reset bit in the watchdog */
51 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
52 wdt_base + SUN4I_WATCHDOG_MODE_REG);
53
54 /*
55 * Restart the watchdog. The default (and lowest) interval
56 * value for the watchdog is 0.5s.
57 */
58 writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
59
60 while (1) {
61 mdelay(5);
62 writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
63 wdt_base + SUN4I_WATCHDOG_MODE_REG);
64 }
65}
66
67static struct of_device_id sunxi_restart_ids[] = {
68 { .compatible = "allwinner,sun4i-a10-wdt" },
69 { /*sentinel*/ }
70};
71
72static void sunxi_setup_restart(void)
73{
74 struct device_node *np;
75
76 np = of_find_matching_node(NULL, sunxi_restart_ids);
77 if (WARN(!np, "unable to setup watchdog restart"))
78 return;
79
80 wdt_base = of_iomap(np, 0);
81 WARN(!wdt_base, "failed to map watchdog base address");
82}
83
84static void __init sunxi_dt_init(void)
85{
86 sunxi_setup_restart();
87
88 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
89}
90 18
91static const char * const sunxi_board_dt_compat[] = { 19static const char * const sunxi_board_dt_compat[] = {
92 "allwinner,sun4i-a10", 20 "allwinner,sun4i-a10",
@@ -96,9 +24,7 @@ static const char * const sunxi_board_dt_compat[] = {
96}; 24};
97 25
98DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") 26DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
99 .init_machine = sunxi_dt_init,
100 .dt_compat = sunxi_board_dt_compat, 27 .dt_compat = sunxi_board_dt_compat,
101 .restart = sun4i_restart,
102MACHINE_END 28MACHINE_END
103 29
104static const char * const sun6i_board_dt_compat[] = { 30static const char * const sun6i_board_dt_compat[] = {
@@ -126,9 +52,7 @@ static const char * const sun7i_board_dt_compat[] = {
126}; 52};
127 53
128DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") 54DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
129 .init_machine = sunxi_dt_init,
130 .dt_compat = sun7i_board_dt_compat, 55 .dt_compat = sun7i_board_dt_compat,
131 .restart = sun4i_restart,
132MACHINE_END 56MACHINE_END
133 57
134static const char * const sun8i_board_dt_compat[] = { 58static const char * const sun8i_board_dt_compat[] = {
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c2baa8ede543..24770e5a5081 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -64,7 +64,9 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
64 64
65static struct omap_system_dma_plat_info *p; 65static struct omap_system_dma_plat_info *p;
66static struct omap_dma_dev_attr *d; 66static struct omap_dma_dev_attr *d;
67 67static void omap_clear_dma(int lch);
68static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
69 unsigned char write_prio);
68static int enable_1510_mode; 70static int enable_1510_mode;
69static u32 errata; 71static u32 errata;
70 72
@@ -284,66 +286,6 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
284} 286}
285EXPORT_SYMBOL(omap_set_dma_transfer_params); 287EXPORT_SYMBOL(omap_set_dma_transfer_params);
286 288
287void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
288{
289 BUG_ON(omap_dma_in_1510_mode());
290
291 if (dma_omap1()) {
292 u16 w;
293
294 w = p->dma_read(CCR2, lch);
295 w &= ~0x03;
296
297 switch (mode) {
298 case OMAP_DMA_CONSTANT_FILL:
299 w |= 0x01;
300 break;
301 case OMAP_DMA_TRANSPARENT_COPY:
302 w |= 0x02;
303 break;
304 case OMAP_DMA_COLOR_DIS:
305 break;
306 default:
307 BUG();
308 }
309 p->dma_write(w, CCR2, lch);
310
311 w = p->dma_read(LCH_CTRL, lch);
312 w &= ~0x0f;
313 /* Default is channel type 2D */
314 if (mode) {
315 p->dma_write(color, COLOR, lch);
316 w |= 1; /* Channel type G */
317 }
318 p->dma_write(w, LCH_CTRL, lch);
319 }
320
321 if (dma_omap2plus()) {
322 u32 val;
323
324 val = p->dma_read(CCR, lch);
325 val &= ~((1 << 17) | (1 << 16));
326
327 switch (mode) {
328 case OMAP_DMA_CONSTANT_FILL:
329 val |= 1 << 16;
330 break;
331 case OMAP_DMA_TRANSPARENT_COPY:
332 val |= 1 << 17;
333 break;
334 case OMAP_DMA_COLOR_DIS:
335 break;
336 default:
337 BUG();
338 }
339 p->dma_write(val, CCR, lch);
340
341 color &= 0xffffff;
342 p->dma_write(color, COLOR, lch);
343 }
344}
345EXPORT_SYMBOL(omap_set_dma_color_mode);
346
347void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 289void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
348{ 290{
349 if (dma_omap2plus()) { 291 if (dma_omap2plus()) {
@@ -417,16 +359,6 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
417} 359}
418EXPORT_SYMBOL(omap_set_dma_params); 360EXPORT_SYMBOL(omap_set_dma_params);
419 361
420void omap_set_dma_src_index(int lch, int eidx, int fidx)
421{
422 if (dma_omap2plus())
423 return;
424
425 p->dma_write(eidx, CSEI, lch);
426 p->dma_write(fidx, CSFI, lch);
427}
428EXPORT_SYMBOL(omap_set_dma_src_index);
429
430void omap_set_dma_src_data_pack(int lch, int enable) 362void omap_set_dma_src_data_pack(int lch, int enable)
431{ 363{
432 u32 l; 364 u32 l;
@@ -510,16 +442,6 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
510} 442}
511EXPORT_SYMBOL(omap_set_dma_dest_params); 443EXPORT_SYMBOL(omap_set_dma_dest_params);
512 444
513void omap_set_dma_dest_index(int lch, int eidx, int fidx)
514{
515 if (dma_omap2plus())
516 return;
517
518 p->dma_write(eidx, CDEI, lch);
519 p->dma_write(fidx, CDFI, lch);
520}
521EXPORT_SYMBOL(omap_set_dma_dest_index);
522
523void omap_set_dma_dest_data_pack(int lch, int enable) 445void omap_set_dma_dest_data_pack(int lch, int enable)
524{ 446{
525 u32 l; 447 u32 l;
@@ -843,7 +765,7 @@ EXPORT_SYMBOL(omap_dma_set_global_params);
843 * Both of the above can be set with one of the following values : 765 * Both of the above can be set with one of the following values :
844 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW 766 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
845 */ 767 */
846int 768static int
847omap_dma_set_prio_lch(int lch, unsigned char read_prio, 769omap_dma_set_prio_lch(int lch, unsigned char read_prio,
848 unsigned char write_prio) 770 unsigned char write_prio)
849{ 771{
@@ -864,13 +786,13 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
864 786
865 return 0; 787 return 0;
866} 788}
867EXPORT_SYMBOL(omap_dma_set_prio_lch); 789
868 790
869/* 791/*
870 * Clears any DMA state so the DMA engine is ready to restart with new buffers 792 * Clears any DMA state so the DMA engine is ready to restart with new buffers
871 * through omap_start_dma(). Any buffers in flight are discarded. 793 * through omap_start_dma(). Any buffers in flight are discarded.
872 */ 794 */
873void omap_clear_dma(int lch) 795static void omap_clear_dma(int lch)
874{ 796{
875 unsigned long flags; 797 unsigned long flags;
876 798
@@ -878,7 +800,6 @@ void omap_clear_dma(int lch)
878 p->clear_dma(lch); 800 p->clear_dma(lch);
879 local_irq_restore(flags); 801 local_irq_restore(flags);
880} 802}
881EXPORT_SYMBOL(omap_clear_dma);
882 803
883void omap_start_dma(int lch) 804void omap_start_dma(int lch)
884{ 805{
@@ -1167,652 +1088,6 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
1167} 1088}
1168EXPORT_SYMBOL(omap_dma_link_lch); 1089EXPORT_SYMBOL(omap_dma_link_lch);
1169 1090
1170/*
1171 * Once the DMA queue is stopped, we can destroy it.
1172 */
1173void omap_dma_unlink_lch(int lch_head, int lch_queue)
1174{
1175 if (omap_dma_in_1510_mode()) {
1176 if (lch_head == lch_queue) {
1177 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1178 CCR, lch_head);
1179 return;
1180 }
1181 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1182 BUG();
1183 return;
1184 }
1185
1186 if (dma_chan[lch_head].next_lch != lch_queue ||
1187 dma_chan[lch_head].next_lch == -1) {
1188 pr_err("omap_dma: trying to unlink non linked channels\n");
1189 dump_stack();
1190 }
1191
1192 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1193 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1194 pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
1195 dump_stack();
1196 }
1197
1198 dma_chan[lch_head].next_lch = -1;
1199}
1200EXPORT_SYMBOL(omap_dma_unlink_lch);
1201
1202#ifndef CONFIG_ARCH_OMAP1
1203/* Create chain of DMA channesls */
1204static void create_dma_lch_chain(int lch_head, int lch_queue)
1205{
1206 u32 l;
1207
1208 /* Check if this is the first link in chain */
1209 if (dma_chan[lch_head].next_linked_ch == -1) {
1210 dma_chan[lch_head].next_linked_ch = lch_queue;
1211 dma_chan[lch_head].prev_linked_ch = lch_queue;
1212 dma_chan[lch_queue].next_linked_ch = lch_head;
1213 dma_chan[lch_queue].prev_linked_ch = lch_head;
1214 }
1215
1216 /* a link exists, link the new channel in circular chain */
1217 else {
1218 dma_chan[lch_queue].next_linked_ch =
1219 dma_chan[lch_head].next_linked_ch;
1220 dma_chan[lch_queue].prev_linked_ch = lch_head;
1221 dma_chan[lch_head].next_linked_ch = lch_queue;
1222 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1223 lch_queue;
1224 }
1225
1226 l = p->dma_read(CLNK_CTRL, lch_head);
1227 l &= ~(0x1f);
1228 l |= lch_queue;
1229 p->dma_write(l, CLNK_CTRL, lch_head);
1230
1231 l = p->dma_read(CLNK_CTRL, lch_queue);
1232 l &= ~(0x1f);
1233 l |= (dma_chan[lch_queue].next_linked_ch);
1234 p->dma_write(l, CLNK_CTRL, lch_queue);
1235}
1236
1237/**
1238 * @brief omap_request_dma_chain : Request a chain of DMA channels
1239 *
1240 * @param dev_id - Device id using the dma channel
1241 * @param dev_name - Device name
1242 * @param callback - Call back function
1243 * @chain_id -
1244 * @no_of_chans - Number of channels requested
1245 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1246 * OMAP_DMA_DYNAMIC_CHAIN
1247 * @params - Channel parameters
1248 *
1249 * @return - Success : 0
1250 * Failure: -EINVAL/-ENOMEM
1251 */
1252int omap_request_dma_chain(int dev_id, const char *dev_name,
1253 void (*callback) (int lch, u16 ch_status,
1254 void *data),
1255 int *chain_id, int no_of_chans, int chain_mode,
1256 struct omap_dma_channel_params params)
1257{
1258 int *channels;
1259 int i, err;
1260
1261 /* Is the chain mode valid ? */
1262 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1263 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1264 printk(KERN_ERR "Invalid chain mode requested\n");
1265 return -EINVAL;
1266 }
1267
1268 if (unlikely((no_of_chans < 1
1269 || no_of_chans > dma_lch_count))) {
1270 printk(KERN_ERR "Invalid Number of channels requested\n");
1271 return -EINVAL;
1272 }
1273
1274 /*
1275 * Allocate a queue to maintain the status of the channels
1276 * in the chain
1277 */
1278 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1279 if (channels == NULL) {
1280 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1281 return -ENOMEM;
1282 }
1283
1284 /* request and reserve DMA channels for the chain */
1285 for (i = 0; i < no_of_chans; i++) {
1286 err = omap_request_dma(dev_id, dev_name,
1287 callback, NULL, &channels[i]);
1288 if (err < 0) {
1289 int j;
1290 for (j = 0; j < i; j++)
1291 omap_free_dma(channels[j]);
1292 kfree(channels);
1293 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1294 return err;
1295 }
1296 dma_chan[channels[i]].prev_linked_ch = -1;
1297 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1298
1299 /*
1300 * Allowing client drivers to set common parameters now,
1301 * so that later only relevant (src_start, dest_start
1302 * and element count) can be set
1303 */
1304 omap_set_dma_params(channels[i], &params);
1305 }
1306
1307 *chain_id = channels[0];
1308 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1309 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1310 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1311 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1312
1313 for (i = 0; i < no_of_chans; i++)
1314 dma_chan[channels[i]].chain_id = *chain_id;
1315
1316 /* Reset the Queue pointers */
1317 OMAP_DMA_CHAIN_QINIT(*chain_id);
1318
1319 /* Set up the chain */
1320 if (no_of_chans == 1)
1321 create_dma_lch_chain(channels[0], channels[0]);
1322 else {
1323 for (i = 0; i < (no_of_chans - 1); i++)
1324 create_dma_lch_chain(channels[i], channels[i + 1]);
1325 }
1326
1327 return 0;
1328}
1329EXPORT_SYMBOL(omap_request_dma_chain);
1330
1331/**
1332 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1333 * params after setting it. Dont do this while dma is running!!
1334 *
1335 * @param chain_id - Chained logical channel id.
1336 * @param params
1337 *
1338 * @return - Success : 0
1339 * Failure : -EINVAL
1340 */
1341int omap_modify_dma_chain_params(int chain_id,
1342 struct omap_dma_channel_params params)
1343{
1344 int *channels;
1345 u32 i;
1346
1347 /* Check for input params */
1348 if (unlikely((chain_id < 0
1349 || chain_id >= dma_lch_count))) {
1350 printk(KERN_ERR "Invalid chain id\n");
1351 return -EINVAL;
1352 }
1353
1354 /* Check if the chain exists */
1355 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1356 printk(KERN_ERR "Chain doesn't exists\n");
1357 return -EINVAL;
1358 }
1359 channels = dma_linked_lch[chain_id].linked_dmach_q;
1360
1361 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1362 /*
1363 * Allowing client drivers to set common parameters now,
1364 * so that later only relevant (src_start, dest_start
1365 * and element count) can be set
1366 */
1367 omap_set_dma_params(channels[i], &params);
1368 }
1369
1370 return 0;
1371}
1372EXPORT_SYMBOL(omap_modify_dma_chain_params);
1373
1374/**
1375 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1376 *
1377 * @param chain_id
1378 *
1379 * @return - Success : 0
1380 * Failure : -EINVAL
1381 */
1382int omap_free_dma_chain(int chain_id)
1383{
1384 int *channels;
1385 u32 i;
1386
1387 /* Check for input params */
1388 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1389 printk(KERN_ERR "Invalid chain id\n");
1390 return -EINVAL;
1391 }
1392
1393 /* Check if the chain exists */
1394 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1395 printk(KERN_ERR "Chain doesn't exists\n");
1396 return -EINVAL;
1397 }
1398
1399 channels = dma_linked_lch[chain_id].linked_dmach_q;
1400 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1401 dma_chan[channels[i]].next_linked_ch = -1;
1402 dma_chan[channels[i]].prev_linked_ch = -1;
1403 dma_chan[channels[i]].chain_id = -1;
1404 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1405 omap_free_dma(channels[i]);
1406 }
1407
1408 kfree(channels);
1409
1410 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1411 dma_linked_lch[chain_id].chain_mode = -1;
1412 dma_linked_lch[chain_id].chain_state = -1;
1413
1414 return (0);
1415}
1416EXPORT_SYMBOL(omap_free_dma_chain);
1417
1418/**
1419 * @brief omap_dma_chain_status - Check if the chain is in
1420 * active / inactive state.
1421 * @param chain_id
1422 *
1423 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1424 * Failure : -EINVAL
1425 */
1426int omap_dma_chain_status(int chain_id)
1427{
1428 /* Check for input params */
1429 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1430 printk(KERN_ERR "Invalid chain id\n");
1431 return -EINVAL;
1432 }
1433
1434 /* Check if the chain exists */
1435 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1436 printk(KERN_ERR "Chain doesn't exists\n");
1437 return -EINVAL;
1438 }
1439 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1440 dma_linked_lch[chain_id].q_count);
1441
1442 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1443 return OMAP_DMA_CHAIN_INACTIVE;
1444
1445 return OMAP_DMA_CHAIN_ACTIVE;
1446}
1447EXPORT_SYMBOL(omap_dma_chain_status);
1448
1449/**
1450 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1451 * set the params and start the transfer.
1452 *
1453 * @param chain_id
1454 * @param src_start - buffer start address
1455 * @param dest_start - Dest address
1456 * @param elem_count
1457 * @param frame_count
1458 * @param callbk_data - channel callback parameter data.
1459 *
1460 * @return - Success : 0
1461 * Failure: -EINVAL/-EBUSY
1462 */
1463int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1464 int elem_count, int frame_count, void *callbk_data)
1465{
1466 int *channels;
1467 u32 l, lch;
1468 int start_dma = 0;
1469
1470 /*
1471 * if buffer size is less than 1 then there is
1472 * no use of starting the chain
1473 */
1474 if (elem_count < 1) {
1475 printk(KERN_ERR "Invalid buffer size\n");
1476 return -EINVAL;
1477 }
1478
1479 /* Check for input params */
1480 if (unlikely((chain_id < 0
1481 || chain_id >= dma_lch_count))) {
1482 printk(KERN_ERR "Invalid chain id\n");
1483 return -EINVAL;
1484 }
1485
1486 /* Check if the chain exists */
1487 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1488 printk(KERN_ERR "Chain doesn't exist\n");
1489 return -EINVAL;
1490 }
1491
1492 /* Check if all the channels in chain are in use */
1493 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1494 return -EBUSY;
1495
1496 /* Frame count may be negative in case of indexed transfers */
1497 channels = dma_linked_lch[chain_id].linked_dmach_q;
1498
1499 /* Get a free channel */
1500 lch = channels[dma_linked_lch[chain_id].q_tail];
1501
1502 /* Store the callback data */
1503 dma_chan[lch].data = callbk_data;
1504
1505 /* Increment the q_tail */
1506 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1507
1508 /* Set the params to the free channel */
1509 if (src_start != 0)
1510 p->dma_write(src_start, CSSA, lch);
1511 if (dest_start != 0)
1512 p->dma_write(dest_start, CDSA, lch);
1513
1514 /* Write the buffer size */
1515 p->dma_write(elem_count, CEN, lch);
1516 p->dma_write(frame_count, CFN, lch);
1517
1518 /*
1519 * If the chain is dynamically linked,
1520 * then we may have to start the chain if its not active
1521 */
1522 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1523
1524 /*
1525 * In Dynamic chain, if the chain is not started,
1526 * queue the channel
1527 */
1528 if (dma_linked_lch[chain_id].chain_state ==
1529 DMA_CHAIN_NOTSTARTED) {
1530 /* Enable the link in previous channel */
1531 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1532 DMA_CH_QUEUED)
1533 enable_lnk(dma_chan[lch].prev_linked_ch);
1534 dma_chan[lch].state = DMA_CH_QUEUED;
1535 }
1536
1537 /*
1538 * Chain is already started, make sure its active,
1539 * if not then start the chain
1540 */
1541 else {
1542 start_dma = 1;
1543
1544 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1545 DMA_CH_STARTED) {
1546 enable_lnk(dma_chan[lch].prev_linked_ch);
1547 dma_chan[lch].state = DMA_CH_QUEUED;
1548 start_dma = 0;
1549 if (0 == ((1 << 7) & p->dma_read(
1550 CCR, dma_chan[lch].prev_linked_ch))) {
1551 disable_lnk(dma_chan[lch].
1552 prev_linked_ch);
1553 pr_debug("\n prev ch is stopped\n");
1554 start_dma = 1;
1555 }
1556 }
1557
1558 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1559 == DMA_CH_QUEUED) {
1560 enable_lnk(dma_chan[lch].prev_linked_ch);
1561 dma_chan[lch].state = DMA_CH_QUEUED;
1562 start_dma = 0;
1563 }
1564 omap_enable_channel_irq(lch);
1565
1566 l = p->dma_read(CCR, lch);
1567
1568 if ((0 == (l & (1 << 24))))
1569 l &= ~(1 << 25);
1570 else
1571 l |= (1 << 25);
1572 if (start_dma == 1) {
1573 if (0 == (l & (1 << 7))) {
1574 l |= (1 << 7);
1575 dma_chan[lch].state = DMA_CH_STARTED;
1576 pr_debug("starting %d\n", lch);
1577 p->dma_write(l, CCR, lch);
1578 } else
1579 start_dma = 0;
1580 } else {
1581 if (0 == (l & (1 << 7)))
1582 p->dma_write(l, CCR, lch);
1583 }
1584 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1585 }
1586 }
1587
1588 return 0;
1589}
1590EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1591
1592/**
1593 * @brief omap_start_dma_chain_transfers - Start the chain
1594 *
1595 * @param chain_id
1596 *
1597 * @return - Success : 0
1598 * Failure : -EINVAL/-EBUSY
1599 */
1600int omap_start_dma_chain_transfers(int chain_id)
1601{
1602 int *channels;
1603 u32 l, i;
1604
1605 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1606 printk(KERN_ERR "Invalid chain id\n");
1607 return -EINVAL;
1608 }
1609
1610 channels = dma_linked_lch[chain_id].linked_dmach_q;
1611
1612 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1613 printk(KERN_ERR "Chain is already started\n");
1614 return -EBUSY;
1615 }
1616
1617 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1618 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1619 i++) {
1620 enable_lnk(channels[i]);
1621 omap_enable_channel_irq(channels[i]);
1622 }
1623 } else {
1624 omap_enable_channel_irq(channels[0]);
1625 }
1626
1627 l = p->dma_read(CCR, channels[0]);
1628 l |= (1 << 7);
1629 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1630 dma_chan[channels[0]].state = DMA_CH_STARTED;
1631
1632 if ((0 == (l & (1 << 24))))
1633 l &= ~(1 << 25);
1634 else
1635 l |= (1 << 25);
1636 p->dma_write(l, CCR, channels[0]);
1637
1638 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1639
1640 return 0;
1641}
1642EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1643
1644/**
1645 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1646 *
1647 * @param chain_id
1648 *
1649 * @return - Success : 0
1650 * Failure : EINVAL
1651 */
1652int omap_stop_dma_chain_transfers(int chain_id)
1653{
1654 int *channels;
1655 u32 l, i;
1656 u32 sys_cf = 0;
1657
1658 /* Check for input params */
1659 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1660 printk(KERN_ERR "Invalid chain id\n");
1661 return -EINVAL;
1662 }
1663
1664 /* Check if the chain exists */
1665 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1666 printk(KERN_ERR "Chain doesn't exists\n");
1667 return -EINVAL;
1668 }
1669 channels = dma_linked_lch[chain_id].linked_dmach_q;
1670
1671 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1672 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1673 l = sys_cf;
1674 /* Middle mode reg set no Standby */
1675 l &= ~((1 << 12)|(1 << 13));
1676 p->dma_write(l, OCP_SYSCONFIG, 0);
1677 }
1678
1679 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1680
1681 /* Stop the Channel transmission */
1682 l = p->dma_read(CCR, channels[i]);
1683 l &= ~(1 << 7);
1684 p->dma_write(l, CCR, channels[i]);
1685
1686 /* Disable the link in all the channels */
1687 disable_lnk(channels[i]);
1688 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1689
1690 }
1691 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1692
1693 /* Reset the Queue pointers */
1694 OMAP_DMA_CHAIN_QINIT(chain_id);
1695
1696 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1697 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1698
1699 return 0;
1700}
1701EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1702
1703/* Get the index of the ongoing DMA in chain */
1704/**
1705 * @brief omap_get_dma_chain_index - Get the element and frame index
1706 * of the ongoing DMA in chain
1707 *
1708 * @param chain_id
1709 * @param ei - Element index
1710 * @param fi - Frame index
1711 *
1712 * @return - Success : 0
1713 * Failure : -EINVAL
1714 */
1715int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1716{
1717 int lch;
1718 int *channels;
1719
1720 /* Check for input params */
1721 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1722 printk(KERN_ERR "Invalid chain id\n");
1723 return -EINVAL;
1724 }
1725
1726 /* Check if the chain exists */
1727 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1728 printk(KERN_ERR "Chain doesn't exists\n");
1729 return -EINVAL;
1730 }
1731 if ((!ei) || (!fi))
1732 return -EINVAL;
1733
1734 channels = dma_linked_lch[chain_id].linked_dmach_q;
1735
1736 /* Get the current channel */
1737 lch = channels[dma_linked_lch[chain_id].q_head];
1738
1739 *ei = p->dma_read(CCEN, lch);
1740 *fi = p->dma_read(CCFN, lch);
1741
1742 return 0;
1743}
1744EXPORT_SYMBOL(omap_get_dma_chain_index);
1745
1746/**
1747 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1748 * ongoing DMA in chain
1749 *
1750 * @param chain_id
1751 *
1752 * @return - Success : Destination position
1753 * Failure : -EINVAL
1754 */
1755int omap_get_dma_chain_dst_pos(int chain_id)
1756{
1757 int lch;
1758 int *channels;
1759
1760 /* Check for input params */
1761 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1762 printk(KERN_ERR "Invalid chain id\n");
1763 return -EINVAL;
1764 }
1765
1766 /* Check if the chain exists */
1767 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1768 printk(KERN_ERR "Chain doesn't exists\n");
1769 return -EINVAL;
1770 }
1771
1772 channels = dma_linked_lch[chain_id].linked_dmach_q;
1773
1774 /* Get the current channel */
1775 lch = channels[dma_linked_lch[chain_id].q_head];
1776
1777 return p->dma_read(CDAC, lch);
1778}
1779EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1780
1781/**
1782 * @brief omap_get_dma_chain_src_pos - Get the source position
1783 * of the ongoing DMA in chain
1784 * @param chain_id
1785 *
1786 * @return - Success : Destination position
1787 * Failure : -EINVAL
1788 */
1789int omap_get_dma_chain_src_pos(int chain_id)
1790{
1791 int lch;
1792 int *channels;
1793
1794 /* Check for input params */
1795 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1796 printk(KERN_ERR "Invalid chain id\n");
1797 return -EINVAL;
1798 }
1799
1800 /* Check if the chain exists */
1801 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1802 printk(KERN_ERR "Chain doesn't exists\n");
1803 return -EINVAL;
1804 }
1805
1806 channels = dma_linked_lch[chain_id].linked_dmach_q;
1807
1808 /* Get the current channel */
1809 lch = channels[dma_linked_lch[chain_id].q_head];
1810
1811 return p->dma_read(CSAC, lch);
1812}
1813EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1814#endif /* ifndef CONFIG_ARCH_OMAP1 */
1815
1816/*----------------------------------------------------------------------------*/ 1091/*----------------------------------------------------------------------------*/
1817 1092
1818#ifdef CONFIG_ARCH_OMAP1 1093#ifdef CONFIG_ARCH_OMAP1
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index a8d7ea14f183..8bdbc45c6dad 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -178,12 +178,6 @@ static irqreturn_t ch2_irq(int irq, void *handle)
178 return IRQ_NONE; 178 return IRQ_NONE;
179} 179}
180 180
181static struct irqaction tc_irqaction = {
182 .name = "tc_clkevt",
183 .flags = IRQF_TIMER,
184 .handler = ch2_irq,
185};
186
187static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx) 181static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
188{ 182{
189 int ret; 183 int ret;
@@ -198,15 +192,16 @@ static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
198 192
199 clkevt.regs = tc->regs; 193 clkevt.regs = tc->regs;
200 clkevt.clk = t2_clk; 194 clkevt.clk = t2_clk;
201 tc_irqaction.dev_id = &clkevt;
202 195
203 timer_clock = clk32k_divisor_idx; 196 timer_clock = clk32k_divisor_idx;
204 197
205 clkevt.clkevt.cpumask = cpumask_of(0); 198 clkevt.clkevt.cpumask = cpumask_of(0);
206 199
207 ret = setup_irq(irq, &tc_irqaction); 200 ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
208 if (ret) 201 if (ret) {
202 clk_disable_unprepare(t2_clk);
209 return ret; 203 return ret;
204 }
210 205
211 clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff); 206 clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
212 207
@@ -279,7 +274,7 @@ static int __init tcb_clksrc_init(void)
279 int i; 274 int i;
280 int ret; 275 int ret;
281 276
282 tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name); 277 tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
283 if (!tc) { 278 if (!tc) {
284 pr_debug("can't alloc TC for clocksource\n"); 279 pr_debug("can't alloc TC for clocksource\n");
285 return -ENODEV; 280 return -ENODEV;
diff --git a/drivers/misc/atmel_tclib.c b/drivers/misc/atmel_tclib.c
index c8d8e38d0d8a..0ca05c3ec8d6 100644
--- a/drivers/misc/atmel_tclib.c
+++ b/drivers/misc/atmel_tclib.c
@@ -35,60 +35,31 @@ static LIST_HEAD(tc_list);
35/** 35/**
36 * atmel_tc_alloc - allocate a specified TC block 36 * atmel_tc_alloc - allocate a specified TC block
37 * @block: which block to allocate 37 * @block: which block to allocate
38 * @name: name to be associated with the iomem resource
39 * 38 *
40 * Caller allocates a block. If it is available, a pointer to a 39 * Caller allocates a block. If it is available, a pointer to a
41 * pre-initialized struct atmel_tc is returned. The caller can access 40 * pre-initialized struct atmel_tc is returned. The caller can access
42 * the registers directly through the "regs" field. 41 * the registers directly through the "regs" field.
43 */ 42 */
44struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name) 43struct atmel_tc *atmel_tc_alloc(unsigned block)
45{ 44{
46 struct atmel_tc *tc; 45 struct atmel_tc *tc;
47 struct platform_device *pdev = NULL; 46 struct platform_device *pdev = NULL;
48 struct resource *r;
49 size_t size;
50 47
51 spin_lock(&tc_list_lock); 48 spin_lock(&tc_list_lock);
52 list_for_each_entry(tc, &tc_list, node) { 49 list_for_each_entry(tc, &tc_list, node) {
53 if (tc->pdev->dev.of_node) { 50 if (tc->allocated)
54 if (of_alias_get_id(tc->pdev->dev.of_node, "tcb") 51 continue;
55 == block) { 52
56 pdev = tc->pdev; 53 if ((tc->pdev->dev.of_node && tc->id == block) ||
57 break; 54 (tc->pdev->id == block)) {
58 }
59 } else if (tc->pdev->id == block) {
60 pdev = tc->pdev; 55 pdev = tc->pdev;
56 tc->allocated = true;
61 break; 57 break;
62 } 58 }
63 } 59 }
64
65 if (!pdev || tc->iomem)
66 goto fail;
67
68 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
69 if (!r)
70 goto fail;
71
72 size = resource_size(r);
73 r = request_mem_region(r->start, size, name);
74 if (!r)
75 goto fail;
76
77 tc->regs = ioremap(r->start, size);
78 if (!tc->regs)
79 goto fail_ioremap;
80
81 tc->iomem = r;
82
83out:
84 spin_unlock(&tc_list_lock); 60 spin_unlock(&tc_list_lock);
85 return tc;
86 61
87fail_ioremap: 62 return pdev ? tc : NULL;
88 release_mem_region(r->start, size);
89fail:
90 tc = NULL;
91 goto out;
92} 63}
93EXPORT_SYMBOL_GPL(atmel_tc_alloc); 64EXPORT_SYMBOL_GPL(atmel_tc_alloc);
94 65
@@ -96,19 +67,14 @@ EXPORT_SYMBOL_GPL(atmel_tc_alloc);
96 * atmel_tc_free - release a specified TC block 67 * atmel_tc_free - release a specified TC block
97 * @tc: Timer/counter block that was returned by atmel_tc_alloc() 68 * @tc: Timer/counter block that was returned by atmel_tc_alloc()
98 * 69 *
99 * This reverses the effect of atmel_tc_alloc(), unmapping the I/O 70 * This reverses the effect of atmel_tc_alloc(), invalidating the resource
100 * registers, invalidating the resource returned by that routine and 71 * returned by that routine and making the TC available to other drivers.
101 * making the TC available to other drivers.
102 */ 72 */
103void atmel_tc_free(struct atmel_tc *tc) 73void atmel_tc_free(struct atmel_tc *tc)
104{ 74{
105 spin_lock(&tc_list_lock); 75 spin_lock(&tc_list_lock);
106 if (tc->regs) { 76 if (tc->allocated)
107 iounmap(tc->regs); 77 tc->allocated = false;
108 release_mem_region(tc->iomem->start, resource_size(tc->iomem));
109 tc->regs = NULL;
110 tc->iomem = NULL;
111 }
112 spin_unlock(&tc_list_lock); 78 spin_unlock(&tc_list_lock);
113} 79}
114EXPORT_SYMBOL_GPL(atmel_tc_free); 80EXPORT_SYMBOL_GPL(atmel_tc_free);
@@ -142,25 +108,27 @@ static int __init tc_probe(struct platform_device *pdev)
142 struct atmel_tc *tc; 108 struct atmel_tc *tc;
143 struct clk *clk; 109 struct clk *clk;
144 int irq; 110 int irq;
145 111 struct resource *r;
146 if (!platform_get_resource(pdev, IORESOURCE_MEM, 0)) 112 unsigned int i;
147 return -EINVAL;
148 113
149 irq = platform_get_irq(pdev, 0); 114 irq = platform_get_irq(pdev, 0);
150 if (irq < 0) 115 if (irq < 0)
151 return -EINVAL; 116 return -EINVAL;
152 117
153 tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL); 118 tc = devm_kzalloc(&pdev->dev, sizeof(struct atmel_tc), GFP_KERNEL);
154 if (!tc) 119 if (!tc)
155 return -ENOMEM; 120 return -ENOMEM;
156 121
157 tc->pdev = pdev; 122 tc->pdev = pdev;
158 123
159 clk = clk_get(&pdev->dev, "t0_clk"); 124 clk = devm_clk_get(&pdev->dev, "t0_clk");
160 if (IS_ERR(clk)) { 125 if (IS_ERR(clk))
161 kfree(tc); 126 return PTR_ERR(clk);
162 return -EINVAL; 127
163 } 128 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
129 tc->regs = devm_ioremap_resource(&pdev->dev, r);
130 if (IS_ERR(tc->regs))
131 return PTR_ERR(tc->regs);
164 132
165 /* Now take SoC information if available */ 133 /* Now take SoC information if available */
166 if (pdev->dev.of_node) { 134 if (pdev->dev.of_node) {
@@ -168,13 +136,17 @@ static int __init tc_probe(struct platform_device *pdev)
168 match = of_match_node(atmel_tcb_dt_ids, pdev->dev.of_node); 136 match = of_match_node(atmel_tcb_dt_ids, pdev->dev.of_node);
169 if (match) 137 if (match)
170 tc->tcb_config = match->data; 138 tc->tcb_config = match->data;
139
140 tc->id = of_alias_get_id(tc->pdev->dev.of_node, "tcb");
141 } else {
142 tc->id = pdev->id;
171 } 143 }
172 144
173 tc->clk[0] = clk; 145 tc->clk[0] = clk;
174 tc->clk[1] = clk_get(&pdev->dev, "t1_clk"); 146 tc->clk[1] = devm_clk_get(&pdev->dev, "t1_clk");
175 if (IS_ERR(tc->clk[1])) 147 if (IS_ERR(tc->clk[1]))
176 tc->clk[1] = clk; 148 tc->clk[1] = clk;
177 tc->clk[2] = clk_get(&pdev->dev, "t2_clk"); 149 tc->clk[2] = devm_clk_get(&pdev->dev, "t2_clk");
178 if (IS_ERR(tc->clk[2])) 150 if (IS_ERR(tc->clk[2]))
179 tc->clk[2] = clk; 151 tc->clk[2] = clk;
180 152
@@ -186,18 +158,33 @@ static int __init tc_probe(struct platform_device *pdev)
186 if (tc->irq[2] < 0) 158 if (tc->irq[2] < 0)
187 tc->irq[2] = irq; 159 tc->irq[2] = irq;
188 160
161 for (i = 0; i < 3; i++)
162 writel(ATMEL_TC_ALL_IRQ, tc->regs + ATMEL_TC_REG(i, IDR));
163
189 spin_lock(&tc_list_lock); 164 spin_lock(&tc_list_lock);
190 list_add_tail(&tc->node, &tc_list); 165 list_add_tail(&tc->node, &tc_list);
191 spin_unlock(&tc_list_lock); 166 spin_unlock(&tc_list_lock);
192 167
168 platform_set_drvdata(pdev, tc);
169
193 return 0; 170 return 0;
194} 171}
195 172
173static void tc_shutdown(struct platform_device *pdev)
174{
175 int i;
176 struct atmel_tc *tc = platform_get_drvdata(pdev);
177
178 for (i = 0; i < 3; i++)
179 writel(ATMEL_TC_ALL_IRQ, tc->regs + ATMEL_TC_REG(i, IDR));
180}
181
196static struct platform_driver tc_driver = { 182static struct platform_driver tc_driver = {
197 .driver = { 183 .driver = {
198 .name = "atmel_tcb", 184 .name = "atmel_tcb",
199 .of_match_table = of_match_ptr(atmel_tcb_dt_ids), 185 .of_match_table = of_match_ptr(atmel_tcb_dt_ids),
200 }, 186 },
187 .shutdown = tc_shutdown,
201}; 188};
202 189
203static int __init tc_init(void) 190static int __init tc_init(void)
diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c
index f3dcd02390f1..d56e5b717431 100644
--- a/drivers/pwm/pwm-atmel-tcb.c
+++ b/drivers/pwm/pwm-atmel-tcb.c
@@ -379,7 +379,7 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev)
379 return err; 379 return err;
380 } 380 }
381 381
382 tc = atmel_tc_alloc(tcblock, "tcb-pwm"); 382 tc = atmel_tc_alloc(tcblock);
383 if (tc == NULL) { 383 if (tc == NULL) {
384 dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n"); 384 dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n");
385 return -ENOMEM; 385 return -ENOMEM;
diff --git a/include/linux/atmel_tc.h b/include/linux/atmel_tc.h
index 89a931babecf..b87c1c7c242a 100644
--- a/include/linux/atmel_tc.h
+++ b/include/linux/atmel_tc.h
@@ -44,12 +44,13 @@ struct atmel_tcb_config {
44/** 44/**
45 * struct atmel_tc - information about a Timer/Counter Block 45 * struct atmel_tc - information about a Timer/Counter Block
46 * @pdev: physical device 46 * @pdev: physical device
47 * @iomem: resource associated with the I/O register
48 * @regs: mapping through which the I/O registers can be accessed 47 * @regs: mapping through which the I/O registers can be accessed
48 * @id: block id
49 * @tcb_config: configuration data from SoC 49 * @tcb_config: configuration data from SoC
50 * @irq: irq for each of the three channels 50 * @irq: irq for each of the three channels
51 * @clk: internal clock source for each of the three channels 51 * @clk: internal clock source for each of the three channels
52 * @node: list node, for tclib internal use 52 * @node: list node, for tclib internal use
53 * @allocated: if already used, for tclib internal use
53 * 54 *
54 * On some platforms, each TC channel has its own clocks and IRQs, 55 * On some platforms, each TC channel has its own clocks and IRQs,
55 * while on others, all TC channels share the same clock and IRQ. 56 * while on others, all TC channels share the same clock and IRQ.
@@ -61,15 +62,16 @@ struct atmel_tcb_config {
61 */ 62 */
62struct atmel_tc { 63struct atmel_tc {
63 struct platform_device *pdev; 64 struct platform_device *pdev;
64 struct resource *iomem;
65 void __iomem *regs; 65 void __iomem *regs;
66 int id;
66 const struct atmel_tcb_config *tcb_config; 67 const struct atmel_tcb_config *tcb_config;
67 int irq[3]; 68 int irq[3];
68 struct clk *clk[3]; 69 struct clk *clk[3];
69 struct list_head node; 70 struct list_head node;
71 bool allocated;
70}; 72};
71 73
72extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name); 74extern struct atmel_tc *atmel_tc_alloc(unsigned block);
73extern void atmel_tc_free(struct atmel_tc *tc); 75extern void atmel_tc_free(struct atmel_tc *tc);
74 76
75/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */ 77/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
@@ -258,5 +260,10 @@ extern const u8 atmel_tc_divisors[5];
258#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */ 260#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
259#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */ 261#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
260#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */ 262#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
263#define ATMEL_TC_ALL_IRQ (ATMEL_TC_COVFS | ATMEL_TC_LOVRS | \
264 ATMEL_TC_CPAS | ATMEL_TC_CPBS | \
265 ATMEL_TC_CPCS | ATMEL_TC_LDRAS | \
266 ATMEL_TC_LDRBS | ATMEL_TC_ETRGS) \
267 /* all IRQs */
261 268
262#endif 269#endif
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 6f06f8bc612c..e5a70132a240 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -306,15 +306,12 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
306 int elem_count, int frame_count, 306 int elem_count, int frame_count,
307 int sync_mode, 307 int sync_mode,
308 int dma_trigger, int src_or_dst_synch); 308 int dma_trigger, int src_or_dst_synch);
309extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
310 u32 color);
311extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); 309extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
312extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); 310extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
313 311
314extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 312extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
315 unsigned long src_start, 313 unsigned long src_start,
316 int src_ei, int src_fi); 314 int src_ei, int src_fi);
317extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
318extern void omap_set_dma_src_data_pack(int lch, int enable); 315extern void omap_set_dma_src_data_pack(int lch, int enable);
319extern void omap_set_dma_src_burst_mode(int lch, 316extern void omap_set_dma_src_burst_mode(int lch,
320 enum omap_dma_burst_mode burst_mode); 317 enum omap_dma_burst_mode burst_mode);
@@ -322,7 +319,6 @@ extern void omap_set_dma_src_burst_mode(int lch,
322extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 319extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
323 unsigned long dest_start, 320 unsigned long dest_start,
324 int dst_ei, int dst_fi); 321 int dst_ei, int dst_fi);
325extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
326extern void omap_set_dma_dest_data_pack(int lch, int enable); 322extern void omap_set_dma_dest_data_pack(int lch, int enable);
327extern void omap_set_dma_dest_burst_mode(int lch, 323extern void omap_set_dma_dest_burst_mode(int lch,
328 enum omap_dma_burst_mode burst_mode); 324 enum omap_dma_burst_mode burst_mode);
@@ -331,52 +327,19 @@ extern void omap_set_dma_params(int lch,
331 struct omap_dma_channel_params *params); 327 struct omap_dma_channel_params *params);
332 328
333extern void omap_dma_link_lch(int lch_head, int lch_queue); 329extern void omap_dma_link_lch(int lch_head, int lch_queue);
334extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
335 330
336extern int omap_set_dma_callback(int lch, 331extern int omap_set_dma_callback(int lch,
337 void (*callback)(int lch, u16 ch_status, void *data), 332 void (*callback)(int lch, u16 ch_status, void *data),
338 void *data); 333 void *data);
339extern dma_addr_t omap_get_dma_src_pos(int lch); 334extern dma_addr_t omap_get_dma_src_pos(int lch);
340extern dma_addr_t omap_get_dma_dst_pos(int lch); 335extern dma_addr_t omap_get_dma_dst_pos(int lch);
341extern void omap_clear_dma(int lch);
342extern int omap_get_dma_active_status(int lch); 336extern int omap_get_dma_active_status(int lch);
343extern int omap_dma_running(void); 337extern int omap_dma_running(void);
344extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 338extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
345 int tparams); 339 int tparams);
346extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
347 unsigned char write_prio);
348extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
349extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
350extern int omap_get_dma_index(int lch, int *ei, int *fi);
351
352void omap_dma_global_context_save(void); 340void omap_dma_global_context_save(void);
353void omap_dma_global_context_restore(void); 341void omap_dma_global_context_restore(void);
354 342
355extern void omap_dma_disable_irq(int lch);
356
357/* Chaining APIs */
358#ifndef CONFIG_ARCH_OMAP1
359extern int omap_request_dma_chain(int dev_id, const char *dev_name,
360 void (*callback) (int lch, u16 ch_status,
361 void *data),
362 int *chain_id, int no_of_chans,
363 int chain_mode,
364 struct omap_dma_channel_params params);
365extern int omap_free_dma_chain(int chain_id);
366extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
367 int dest_start, int elem_count,
368 int frame_count, void *callbk_data);
369extern int omap_start_dma_chain_transfers(int chain_id);
370extern int omap_stop_dma_chain_transfers(int chain_id);
371extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
372extern int omap_get_dma_chain_dst_pos(int chain_id);
373extern int omap_get_dma_chain_src_pos(int chain_id);
374
375extern int omap_modify_dma_chain_params(int chain_id,
376 struct omap_dma_channel_params params);
377extern int omap_dma_chain_status(int chain_id);
378#endif
379
380#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP) 343#if defined(CONFIG_ARCH_OMAP1) && IS_ENABLED(CONFIG_FB_OMAP)
381#include <mach/lcd_dma.h> 344#include <mach/lcd_dma.h>
382#else 345#else