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authorRichard Kuo <rkuo@codeaurora.org>2012-11-30 15:53:56 -0500
committerRichard Kuo <rkuo@codeaurora.org>2013-04-30 20:40:24 -0400
commit20f704b69af63bffbc8e70bcf21990318a8912f5 (patch)
tree0c789768307de83e64e5d66b5d4d919d1fb57621
parent0357d2f2a8cde3069d800eb63c1ee41fed31e1b1 (diff)
Hexagon: fix initial page table setup prior to jump to VA
Use the exact number of pages needed to be mapped pre-VA-jump, then map 896MB afterwards, which the arch mem init will fix up. Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
-rw-r--r--arch/hexagon/kernel/head.S85
1 files changed, 73 insertions, 12 deletions
diff --git a/arch/hexagon/kernel/head.S b/arch/hexagon/kernel/head.S
index 477320c455f7..8e88d246ca69 100644
--- a/arch/hexagon/kernel/head.S
+++ b/arch/hexagon/kernel/head.S
@@ -25,6 +25,9 @@
25#include <asm/mem-layout.h> 25#include <asm/mem-layout.h>
26#include <asm/vm_mmu.h> 26#include <asm/vm_mmu.h>
27#include <asm/page.h> 27#include <asm/page.h>
28#include <asm/hexagon_vm.h>
29
30#define SEGTABLE_ENTRIES #0x0e0
28 31
29 __INIT 32 __INIT
30ENTRY(stext) 33ENTRY(stext)
@@ -63,27 +66,73 @@ ENTRY(stext)
63 | __HEXAGON_C_WB_L2 << 6 \ 66 | __HEXAGON_C_WB_L2 << 6 \
64 | __HVM_PDE_S_4MB) 67 | __HVM_PDE_S_4MB)
65 68
66 r1 = pc 69 /*
67 r2.H = #0xffc0 70 * Get number of VA=PA entries; only really needed for jump
68 r2.L = #0x0000 71 * to hyperspace; gets blown away immediately after
69 r1 = and(r1,r2) /* round PC to 4MB boundary */ 72 */
73
74 {
75 r1.l = #LO(_end);
76 r2.l = #LO(stext);
77 r3 = #1;
78 }
79 {
80 r1.h = #HI(_end);
81 r2.h = #HI(stext);
82 r3 = asl(r3, #22);
83 }
84 {
85 r1 = sub(r1, r2);
86 r3 = add(r3, #-1);
87 } /* r1 = _end - stext */
88 r1 = add(r1, r3); /* + (4M-1) */
89 r26 = lsr(r1, #22); /* / 4M = # of entries */
90
91 r1 = r25;
92 r2.h = #0xffc0;
93 r2.l = #0x0000; /* round back down to 4MB boundary */
94 r1 = and(r1,r2);
70 r2 = lsr(r1, #22) /* 4MB page number */ 95 r2 = lsr(r1, #22) /* 4MB page number */
71 r2 = asl(r2, #2) /* times sizeof(PTE) (4bytes) */ 96 r2 = asl(r2, #2) /* times sizeof(PTE) (4bytes) */
72 r0 = add(r0,r2) /* r0 = address of correct PTE */ 97 r0 = add(r0,r2) /* r0 = address of correct PTE */
73 r2 = #PTE_BITS 98 r2 = #PTE_BITS
74 r1 = add(r1,r2) /* r1 = 4MB PTE for the first entry */ 99 r1 = add(r1,r2) /* r1 = 4MB PTE for the first entry */
75 r2.h = #0x0040 100 r2.h = #0x0040
76 r2.l = #0x0000 /* 4MB */ 101 r2.l = #0x0000 /* 4MB increments */
77 memw(r0 ++ #4) = r1 102 loop0(1f,r26);
78 r1 = add(r1, r2) 1031:
79 memw(r0 ++ #4) = r1 104 memw(r0 ++ #4) = r1
105 { r1 = add(r1, r2); } :endloop0
80 106
81 r0 = r24 107 /* Also need to overwrite the initial 0xc0000000 entries */
108 /* PAGE_OFFSET >> (4MB shift - 4 bytes per entry shift) */
109 R1.H = #HI(PAGE_OFFSET >> (22 - 2))
110 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
111
112 r0 = add(r1, r24); /* advance to 0xc0000000 entry */
113 r1 = r25;
114 r2.h = #0xffc0;
115 r2.l = #0x0000; /* round back down to 4MB boundary */
116 r1 = and(r1,r2); /* for huge page */
117 r2 = #PTE_BITS
118 r1 = add(r1,r2);
119 r2.h = #0x0040
120 r2.l = #0x0000 /* 4MB increments */
121
122 loop0(1f,SEGTABLE_ENTRIES);
1231:
124 memw(r0 ++ #4) = r1;
125 { r1 = add(r1,r2); } :endloop0
126
127 r0 = r24;
82 128
83 /* 129 /*
84 * The subroutine wrapper around the virtual instruction touches 130 * The subroutine wrapper around the virtual instruction touches
85 * no memory, so we should be able to use it even here. 131 * no memory, so we should be able to use it even here.
132 * Note that in this version, R1 and R2 get "clobbered"; see
133 * vm_ops.S
86 */ 134 */
135 r1 = #VM_TRANS_TYPE_TABLE
87 call __vmnewmap; 136 call __vmnewmap;
88 137
89 /* Jump into virtual address range. */ 138 /* Jump into virtual address range. */
@@ -97,17 +146,29 @@ ENTRY(stext)
97__head_s_vaddr_target: 146__head_s_vaddr_target:
98 /* 147 /*
99 * Tear down VA=PA translation now that we are running 148 * Tear down VA=PA translation now that we are running
100 * in the desgnated kernel segments. 149 * in kernel virtual space.
101 */ 150 */
102 r0 = #__HVM_PDE_S_INVALID 151 r0 = #__HVM_PDE_S_INVALID
103 r1 = r24 152
104 loop0(1f,#0x100) 153 r1.h = #0xffc0;
154 r1.l = #0x0000;
155 r2 = r25; /* phys_offset */
156 r2 = and(r1,r2);
157
158 r1.l = #lo(swapper_pg_dir)
159 r1.h = #hi(swapper_pg_dir)
160 r2 = lsr(r2, #22) /* 4MB page number */
161 r2 = asl(r2, #2) /* times sizeof(PTE) (4bytes) */
162 r1 = add(r1,r2);
163 loop0(1f,r26)
164
1051: 1651:
106 { 166 {
107 memw(R1 ++ #4) = R0 167 memw(R1 ++ #4) = R0
108 }:endloop0 168 }:endloop0
109 169
110 r0 = r24 170 r0 = r24
171 r1 = #VM_TRANS_TYPE_TABLE
111 call __vmnewmap 172 call __vmnewmap
112 173
113 /* Go ahead and install the trap0 return so angel calls work */ 174 /* Go ahead and install the trap0 return so angel calls work */
@@ -150,7 +211,7 @@ __head_s_vaddr_target:
150 r2 = sub(r2,r0); 211 r2 = sub(r2,r0);
151 call memset; 212 call memset;
152 213
153 /* Set PHYS_OFFSET; should still be in R25 */ 214 /* Set PHYS_OFFSET; should be in R25 */
154#ifdef CONFIG_HEXAGON_PHYS_OFFSET 215#ifdef CONFIG_HEXAGON_PHYS_OFFSET
155 r0.l = #LO(__phys_offset); 216 r0.l = #LO(__phys_offset);
156 r0.h = #HI(__phys_offset); 217 r0.h = #HI(__phys_offset);