diff options
author | Qiao Zhou <zhouqiao@marvell.com> | 2013-10-10 21:07:01 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2013-10-13 11:02:18 -0400 |
commit | 20a90b0ebca434421c30de5ca6b1979ca02e52bf (patch) | |
tree | ace57803f241315da7fb019a4ba7e1b6abdbf0dc | |
parent | 174b537ac2b8fe1bac31039185b80f873716c5a1 (diff) |
dma: mmp_tdma: add multiple burst size support for 910-squ
add multiple burst size support for 910-squ.
Signed-off-by: Qiao Zhou <zhouqiao@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r-- | drivers/dma/mmp_tdma.c | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c index ea5c3d26dd35..8f3e865053d4 100644 --- a/drivers/dma/mmp_tdma.c +++ b/drivers/dma/mmp_tdma.c | |||
@@ -62,6 +62,11 @@ | |||
62 | #define TDCR_BURSTSZ_16B (0x3 << 6) | 62 | #define TDCR_BURSTSZ_16B (0x3 << 6) |
63 | #define TDCR_BURSTSZ_32B (0x6 << 6) | 63 | #define TDCR_BURSTSZ_32B (0x6 << 6) |
64 | #define TDCR_BURSTSZ_64B (0x7 << 6) | 64 | #define TDCR_BURSTSZ_64B (0x7 << 6) |
65 | #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) | ||
66 | #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) | ||
67 | #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) | ||
68 | #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) | ||
69 | #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) | ||
65 | #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) | 70 | #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) |
66 | #define TDCR_BURSTSZ_128B (0x5 << 6) | 71 | #define TDCR_BURSTSZ_128B (0x5 << 6) |
67 | #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ | 72 | #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ |
@@ -228,8 +233,31 @@ static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) | |||
228 | return -EINVAL; | 233 | return -EINVAL; |
229 | } | 234 | } |
230 | } else if (tdmac->type == PXA910_SQU) { | 235 | } else if (tdmac->type == PXA910_SQU) { |
231 | tdcr |= TDCR_BURSTSZ_SQU_32B; | ||
232 | tdcr |= TDCR_SSPMOD; | 236 | tdcr |= TDCR_SSPMOD; |
237 | |||
238 | switch (tdmac->burst_sz) { | ||
239 | case 1: | ||
240 | tdcr |= TDCR_BURSTSZ_SQU_1B; | ||
241 | break; | ||
242 | case 2: | ||
243 | tdcr |= TDCR_BURSTSZ_SQU_2B; | ||
244 | break; | ||
245 | case 4: | ||
246 | tdcr |= TDCR_BURSTSZ_SQU_4B; | ||
247 | break; | ||
248 | case 8: | ||
249 | tdcr |= TDCR_BURSTSZ_SQU_8B; | ||
250 | break; | ||
251 | case 16: | ||
252 | tdcr |= TDCR_BURSTSZ_SQU_16B; | ||
253 | break; | ||
254 | case 32: | ||
255 | tdcr |= TDCR_BURSTSZ_SQU_32B; | ||
256 | break; | ||
257 | default: | ||
258 | dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); | ||
259 | return -EINVAL; | ||
260 | } | ||
233 | } | 261 | } |
234 | 262 | ||
235 | writel(tdcr, tdmac->reg_base + TDCR); | 263 | writel(tdcr, tdmac->reg_base + TDCR); |