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authorLinus Torvalds <torvalds@linux-foundation.org>2014-05-12 22:07:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-05-12 22:07:02 -0400
commit200d963bf49c3399a5f044d53b5b4a8f133a776c (patch)
treec8ff3f50f3f4494f7a113baa3bf2686ecf999ec7
parent7e338c9991ecee9c2ac7a4cee2c2e11ecb563d02 (diff)
parent3b27dcec920075b6f1f5f8014e32e764fcbb96f8 (diff)
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "Seems like we've had more fixes than usual this release cycle, but there's nothing in particular that we're doing differently. Perhaps it's just one of those cycles where more people are finding more regressions (and/or that the latency of when people actually test what's been in the tree for a while is catching up so that we get the bug reports now). The bigger changes here are are for TI and Marvell platforms: * Timing changes for GPMC (generic localbus) on OMAP causing some largeish DTS deltas. * Fixes to window allocation on PCI for mvebu touching drivers/ stuff. Patches have acks from subsystem maintainers where needed. * A fix from Thomas for a botched DT conversion in drivers/edma. There's a handful of other fixes for the above platforms as well as sunxi, at91, i.MX. I also included a MAINTAINER update for Broadcom, and a trivial move of a binding doc. I know you said you'd be offline this week, but I might as well post it for when you return. :)" I'm not quite offline yet. Doing a few pulls in the last hour before my internet goes away.. * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (31 commits) MAINTAINERS: update Broadcom ARM tree location and add an SoC family ARM: dts: i.MX53: Fix ipu register space size ARM: dts: kirkwood: fix mislocated pcie-controller nodes ARM: sunxi: Enable GMAC in sunxi_defconfig ARM: common: edma: Fix xbar mapping ARM: sun7i: Fix i2c4 base address ARM: Kirkwood: T5325: Fix double probe of Codec ARM: mvebu: enable the SATA interface on Armada 375 DB ARM: mvebu: specify I2C bus frequency on Armada 370 DB ARM: mvebu: use qsgmii phy-mode for Armada XP GP interfaces ARM: mvebu: fix NOR bus-width in Armada XP OpenBlocks AX3 Device Tree ARM: mvebu: fix NOR bus-width in Armada XP DB Device Tree ARM: mvebu: fix NOR bus-width in Armada XP GP Device Tree ARM: dts: AM3517: Disable absent IPs inherited from OMAP3 ARM: dts: OMAP2: Fix interrupts for OMAP2420 mailbox ARM: dts: OMAP5: Add mailbox dt node to fix boot warning ARM: OMAP5: Switch to THUMB mode if needed on secondary CPU ARM: dts: am437x-gp-evm: Do not reset gpio5 ARM: dts: omap3-igep0020: use SMSC9221 timings PCI: mvebu: split PCIe BARs into multiple MBus windows when needed ...
-rw-r--r--Documentation/devicetree/bindings/clock/at91-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/dma/ti-edma.txt4
-rw-r--r--MAINTAINERS5
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi2
-rw-r--r--arch/arm/boot/dts/am3517.dtsi16
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts5
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts1
-rw-r--r--arch/arm/boot/dts/armada-375-db.dts5
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts2
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts10
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts2
-rw-r--r--arch/arm/boot/dts/at91-sama5d3_xplained.dts4
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi2
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi2
-rw-r--r--arch/arm/boot/dts/imx53.dtsi2
-rw-r--r--arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts18
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310-common.dtsi18
-rw-r--r--arch/arm/boot/dts/kirkwood-t5325.dts5
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi19
-rw-r--r--arch/arm/boot/dts/omap2.dtsi7
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi8
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi7
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x30.dtsi66
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts4
-rw-r--r--arch/arm/boot/dts/omap3-sb-t35.dtsi37
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts13
-rw-r--r--arch/arm/boot/dts/omap3.dtsi2
-rw-r--r--arch/arm/boot/dts/omap5.dtsi7
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3_mci2.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3_tcb1.dtsi2
-rw-r--r--arch/arm/boot/dts/sama5d3_uart.dtsi2
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi14
-rw-r--r--arch/arm/common/edma.c48
-rw-r--r--arch/arm/configs/sunxi_defconfig2
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S8
-rw-r--r--arch/arm/mach-orion5x/common.h2
-rw-r--r--drivers/bus/mvebu-mbus.c22
-rw-r--r--drivers/memory/mvebu-devbus.c15
-rw-r--r--drivers/pci/host/pci-mvebu.c92
-rw-r--r--include/dt-bindings/clock/at91.h (renamed from include/dt-bindings/clk/at91.h)0
42 files changed, 281 insertions, 207 deletions
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index cd5e23912888..6794cdc96d8f 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -62,7 +62,7 @@ Required properties for PMC node:
62- interrupt-controller : tell that the PMC is an interrupt controller. 62- interrupt-controller : tell that the PMC is an interrupt controller.
63- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, 63- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
64 and reflect the bit position in the PMC_ER/DR/SR registers. 64 and reflect the bit position in the PMC_ER/DR/SR registers.
65 You can use the dt macros defined in dt-bindings/clk/at91.h. 65 You can use the dt macros defined in dt-bindings/clock/at91.h.
66 0 (AT91_PMC_MOSCS) -> main oscillator ready 66 0 (AT91_PMC_MOSCS) -> main oscillator ready
67 1 (AT91_PMC_LOCKA) -> PLL A ready 67 1 (AT91_PMC_LOCKA) -> PLL A ready
68 2 (AT91_PMC_LOCKB) -> PLL B ready 68 2 (AT91_PMC_LOCKB) -> PLL B ready
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
index 9fbbdb783a72..68ff2137bae7 100644
--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -29,6 +29,6 @@ edma: edma@49000000 {
29 dma-channels = <64>; 29 dma-channels = <64>;
30 ti,edma-regions = <4>; 30 ti,edma-regions = <4>;
31 ti,edma-slots = <256>; 31 ti,edma-slots = <256>;
32 ti,edma-xbar-event-map = <1 12 32 ti,edma-xbar-event-map = /bits/ 16 <1 12
33 2 13>; 33 2 13>;
34}; 34};
diff --git a/MAINTAINERS b/MAINTAINERS
index 764075dd8d61..c596b74b29d5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1893,14 +1893,15 @@ L: netdev@vger.kernel.org
1893S: Supported 1893S: Supported
1894F: drivers/net/ethernet/broadcom/bnx2x/ 1894F: drivers/net/ethernet/broadcom/bnx2x/
1895 1895
1896BROADCOM BCM281XX/BCM11XXX ARM ARCHITECTURE 1896BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
1897M: Christian Daudt <bcm@fixthebug.org> 1897M: Christian Daudt <bcm@fixthebug.org>
1898M: Matt Porter <mporter@linaro.org> 1898M: Matt Porter <mporter@linaro.org>
1899L: bcm-kernel-feedback-list@broadcom.com 1899L: bcm-kernel-feedback-list@broadcom.com
1900T: git git://git.github.com/broadcom/bcm11351 1900T: git git://github.com/broadcom/mach-bcm
1901S: Maintained 1901S: Maintained
1902F: arch/arm/mach-bcm/ 1902F: arch/arm/mach-bcm/
1903F: arch/arm/boot/dts/bcm113* 1903F: arch/arm/boot/dts/bcm113*
1904F: arch/arm/boot/dts/bcm216*
1904F: arch/arm/boot/dts/bcm281* 1905F: arch/arm/boot/dts/bcm281*
1905F: arch/arm/configs/bcm_defconfig 1906F: arch/arm/configs/bcm_defconfig
1906F: drivers/mmc/host/sdhci_bcm_kona.c 1907F: drivers/mmc/host/sdhci_bcm_kona.c
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index cb6811e5ae5a..7ad75b4e0663 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -144,7 +144,7 @@
144 compatible = "ti,edma3"; 144 compatible = "ti,edma3";
145 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; 145 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
146 reg = <0x49000000 0x10000>, 146 reg = <0x49000000 0x10000>,
147 <0x44e10f90 0x10>; 147 <0x44e10f90 0x40>;
148 interrupts = <12 13 14>; 148 interrupts = <12 13 14>;
149 #dma-cells = <1>; 149 #dma-cells = <1>;
150 dma-channels = <64>; 150 dma-channels = <64>;
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 788391f91684..5a452fdd7c5d 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -62,5 +62,21 @@
62 }; 62 };
63}; 63};
64 64
65&iva {
66 status = "disabled";
67};
68
69&mailbox {
70 status = "disabled";
71};
72
73&mmu_isp {
74 status = "disabled";
75};
76
77&smartreflex_mpu_iva {
78 status = "disabled";
79};
80
65/include/ "am35xx-clocks.dtsi" 81/include/ "am35xx-clocks.dtsi"
66/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 82/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index df8798e8bd25..a055f7f0f14a 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -117,6 +117,11 @@
117 status = "okay"; 117 status = "okay";
118}; 118};
119 119
120&gpio5 {
121 status = "okay";
122 ti,no-reset-on-init;
123};
124
120&mmc1 { 125&mmc1 {
121 status = "okay"; 126 status = "okay";
122 vmmc-supply = <&vmmcsd_fixed>; 127 vmmc-supply = <&vmmcsd_fixed>;
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 82f238a9063f..3383c4b66803 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -67,6 +67,7 @@
67 i2c@11000 { 67 i2c@11000 {
68 pinctrl-0 = <&i2c0_pins>; 68 pinctrl-0 = <&i2c0_pins>;
69 pinctrl-names = "default"; 69 pinctrl-names = "default";
70 clock-frequency = <100000>;
70 status = "okay"; 71 status = "okay";
71 audio_codec: audio-codec@4a { 72 audio_codec: audio-codec@4a {
72 compatible = "cirrus,cs42l51"; 73 compatible = "cirrus,cs42l51";
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 9378d3136b41..0451124e8ebf 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -79,6 +79,11 @@
79 }; 79 };
80 }; 80 };
81 81
82 sata@a0000 {
83 status = "okay";
84 nr-ports = <2>;
85 };
86
82 nand: nand@d0000 { 87 nand: nand@d0000 {
83 pinctrl-0 = <&nand_pins>; 88 pinctrl-0 = <&nand_pins>;
84 pinctrl-names = "default"; 89 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 448373c4b0e5..90f0bf6f9271 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -49,7 +49,7 @@
49 /* Device Bus parameters are required */ 49 /* Device Bus parameters are required */
50 50
51 /* Read parameters */ 51 /* Read parameters */
52 devbus,bus-width = <8>; 52 devbus,bus-width = <16>;
53 devbus,turn-off-ps = <60000>; 53 devbus,turn-off-ps = <60000>;
54 devbus,badr-skew-ps = <0>; 54 devbus,badr-skew-ps = <0>;
55 devbus,acc-first-ps = <124000>; 55 devbus,acc-first-ps = <124000>;
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 61bda687f782..0c756421ae6a 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -59,7 +59,7 @@
59 /* Device Bus parameters are required */ 59 /* Device Bus parameters are required */
60 60
61 /* Read parameters */ 61 /* Read parameters */
62 devbus,bus-width = <8>; 62 devbus,bus-width = <16>;
63 devbus,turn-off-ps = <60000>; 63 devbus,turn-off-ps = <60000>;
64 devbus,badr-skew-ps = <0>; 64 devbus,badr-skew-ps = <0>;
65 devbus,acc-first-ps = <124000>; 65 devbus,acc-first-ps = <124000>;
@@ -146,22 +146,22 @@
146 ethernet@70000 { 146 ethernet@70000 {
147 status = "okay"; 147 status = "okay";
148 phy = <&phy0>; 148 phy = <&phy0>;
149 phy-mode = "rgmii-id"; 149 phy-mode = "qsgmii";
150 }; 150 };
151 ethernet@74000 { 151 ethernet@74000 {
152 status = "okay"; 152 status = "okay";
153 phy = <&phy1>; 153 phy = <&phy1>;
154 phy-mode = "rgmii-id"; 154 phy-mode = "qsgmii";
155 }; 155 };
156 ethernet@30000 { 156 ethernet@30000 {
157 status = "okay"; 157 status = "okay";
158 phy = <&phy2>; 158 phy = <&phy2>;
159 phy-mode = "rgmii-id"; 159 phy-mode = "qsgmii";
160 }; 160 };
161 ethernet@34000 { 161 ethernet@34000 {
162 status = "okay"; 162 status = "okay";
163 phy = <&phy3>; 163 phy = <&phy3>;
164 phy-mode = "rgmii-id"; 164 phy-mode = "qsgmii";
165 }; 165 };
166 166
167 /* Front-side USB slot */ 167 /* Front-side USB slot */
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 985948ce67b3..5d42feb31049 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -39,7 +39,7 @@
39 /* Device Bus parameters are required */ 39 /* Device Bus parameters are required */
40 40
41 /* Read parameters */ 41 /* Read parameters */
42 devbus,bus-width = <8>; 42 devbus,bus-width = <16>;
43 devbus,turn-off-ps = <60000>; 43 devbus,turn-off-ps = <60000>;
44 devbus,badr-skew-ps = <0>; 44 devbus,badr-skew-ps = <0>;
45 devbus,acc-first-ps = <124000>; 45 devbus,acc-first-ps = <124000>;
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index ce1375595e5f..4537259ce529 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -34,7 +34,7 @@
34 }; 34 };
35 35
36 spi0: spi@f0004000 { 36 spi0: spi@f0004000 {
37 cs-gpios = <&pioD 13 0>; 37 cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
38 status = "okay"; 38 status = "okay";
39 }; 39 };
40 40
@@ -79,7 +79,7 @@
79 }; 79 };
80 80
81 spi1: spi@f8008000 { 81 spi1: spi@f8008000 {
82 cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioD 16 0>; 82 cs-gpios = <&pioC 25 0>;
83 status = "okay"; 83 status = "okay";
84 }; 84 };
85 85
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index e21dda0e8986..3be973e9889a 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -10,7 +10,7 @@
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/clk/at91.h> 13#include <dt-bindings/clock/at91.h>
14 14
15/ { 15/ {
16 model = "Atmel AT91SAM9261 family SoC"; 16 model = "Atmel AT91SAM9261 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 63e1784d272c..92a52faebef7 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -8,7 +8,7 @@
8 8
9#include "skeleton.dtsi" 9#include "skeleton.dtsi"
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/clk/at91.h> 11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14 14
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 9c2bff2252d0..6a1bf4ff83d5 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -115,7 +115,7 @@
115 #address-cells = <1>; 115 #address-cells = <1>;
116 #size-cells = <0>; 116 #size-cells = <0>;
117 compatible = "fsl,imx53-ipu"; 117 compatible = "fsl,imx53-ipu";
118 reg = <0x18000000 0x080000000>; 118 reg = <0x18000000 0x08000000>;
119 interrupts = <11 10>; 119 interrupts = <11 10>;
120 clocks = <&clks IMX5_CLK_IPU_GATE>, 120 clocks = <&clks IMX5_CLK_IPU_GATE>,
121 <&clks IMX5_CLK_IPU_DI0_GATE>, 121 <&clks IMX5_CLK_IPU_DI0_GATE>,
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 32c6fb4a1162..b939f4f52d16 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -30,6 +30,16 @@
30 bootargs = "console=ttyS0,115200n8 earlyprintk"; 30 bootargs = "console=ttyS0,115200n8 earlyprintk";
31 }; 31 };
32 32
33 mbus {
34 pcie-controller {
35 status = "okay";
36
37 pcie@1,0 {
38 status = "okay";
39 };
40 };
41 };
42
33 ocp@f1000000 { 43 ocp@f1000000 {
34 pinctrl@10000 { 44 pinctrl@10000 {
35 pmx_usb_led: pmx-usb-led { 45 pmx_usb_led: pmx-usb-led {
@@ -73,14 +83,6 @@
73 ehci@50000 { 83 ehci@50000 {
74 status = "okay"; 84 status = "okay";
75 }; 85 };
76
77 pcie-controller {
78 status = "okay";
79
80 pcie@1,0 {
81 status = "okay";
82 };
83 };
84 }; 86 };
85 87
86 gpio-leds { 88 gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
index aa78c2d11fe7..e2cc85cc3b87 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -4,6 +4,16 @@
4/ { 4/ {
5 model = "ZyXEL NSA310"; 5 model = "ZyXEL NSA310";
6 6
7 mbus {
8 pcie-controller {
9 status = "okay";
10
11 pcie@1,0 {
12 status = "okay";
13 };
14 };
15 };
16
7 ocp@f1000000 { 17 ocp@f1000000 {
8 pinctrl: pinctrl@10000 { 18 pinctrl: pinctrl@10000 {
9 19
@@ -26,14 +36,6 @@
26 status = "okay"; 36 status = "okay";
27 nr-ports = <2>; 37 nr-ports = <2>;
28 }; 38 };
29
30 pcie-controller {
31 status = "okay";
32
33 pcie@1,0 {
34 status = "okay";
35 };
36 };
37 }; 39 };
38 40
39 gpio_poweroff { 41 gpio_poweroff {
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts
index 7d1c7677a18f..0bd70d928c69 100644
--- a/arch/arm/boot/dts/kirkwood-t5325.dts
+++ b/arch/arm/boot/dts/kirkwood-t5325.dts
@@ -127,11 +127,6 @@
127 127
128 i2c@11000 { 128 i2c@11000 {
129 status = "okay"; 129 status = "okay";
130
131 alc5621: alc5621@1a {
132 compatible = "realtek,alc5621";
133 reg = <0x1a>;
134 };
135 }; 130 };
136 131
137 serial@12000 { 132 serial@12000 {
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index f577b7df9a29..521c587acaee 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -24,11 +24,10 @@
24 compatible = "smsc,lan9221", "smsc,lan9115"; 24 compatible = "smsc,lan9221", "smsc,lan9115";
25 bank-width = <2>; 25 bank-width = <2>;
26 gpmc,mux-add-data; 26 gpmc,mux-add-data;
27 gpmc,cs-on-ns = <0>; 27 gpmc,cs-on-ns = <1>;
28 gpmc,cs-rd-off-ns = <186>; 28 gpmc,cs-rd-off-ns = <180>;
29 gpmc,cs-wr-off-ns = <186>; 29 gpmc,cs-wr-off-ns = <180>;
30 gpmc,adv-on-ns = <12>; 30 gpmc,adv-rd-off-ns = <18>;
31 gpmc,adv-rd-off-ns = <48>;
32 gpmc,adv-wr-off-ns = <48>; 31 gpmc,adv-wr-off-ns = <48>;
33 gpmc,oe-on-ns = <54>; 32 gpmc,oe-on-ns = <54>;
34 gpmc,oe-off-ns = <168>; 33 gpmc,oe-off-ns = <168>;
@@ -36,12 +35,10 @@
36 gpmc,we-off-ns = <168>; 35 gpmc,we-off-ns = <168>;
37 gpmc,rd-cycle-ns = <186>; 36 gpmc,rd-cycle-ns = <186>;
38 gpmc,wr-cycle-ns = <186>; 37 gpmc,wr-cycle-ns = <186>;
39 gpmc,access-ns = <114>; 38 gpmc,access-ns = <144>;
40 gpmc,page-burst-access-ns = <6>; 39 gpmc,page-burst-access-ns = <24>;
41 gpmc,bus-turnaround-ns = <12>; 40 gpmc,bus-turnaround-ns = <90>;
42 gpmc,cycle2cycle-delay-ns = <18>; 41 gpmc,cycle2cycle-delay-ns = <90>;
43 gpmc,wr-data-mux-bus-ns = <90>;
44 gpmc,wr-access-ns = <186>;
45 gpmc,cycle2cycle-samecsen; 42 gpmc,cycle2cycle-samecsen;
46 gpmc,cycle2cycle-diffcsen; 43 gpmc,cycle2cycle-diffcsen;
47 vddvario-supply = <&vddvario>; 44 vddvario-supply = <&vddvario>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 22f35ea142c1..8f8c07da4ac1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -71,13 +71,6 @@
71 interrupts = <58>; 71 interrupts = <58>;
72 }; 72 };
73 73
74 mailbox: mailbox@48094000 {
75 compatible = "ti,omap2-mailbox";
76 ti,hwmods = "mailbox";
77 reg = <0x48094000 0x200>;
78 interrupts = <26>;
79 };
80
81 intc: interrupt-controller@1 { 74 intc: interrupt-controller@1 {
82 compatible = "ti,omap2-intc"; 75 compatible = "ti,omap2-intc";
83 interrupt-controller; 76 interrupt-controller;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 85b1fb014c43..2d9979835f24 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -125,6 +125,14 @@
125 dma-names = "tx", "rx"; 125 dma-names = "tx", "rx";
126 }; 126 };
127 127
128 mailbox: mailbox@48094000 {
129 compatible = "ti,omap2-mailbox";
130 reg = <0x48094000 0x200>;
131 interrupts = <26>, <34>;
132 interrupt-names = "dsp", "iva";
133 ti,hwmods = "mailbox";
134 };
135
128 timer1: timer@48028000 { 136 timer1: timer@48028000 {
129 compatible = "ti,omap2420-timer"; 137 compatible = "ti,omap2420-timer";
130 reg = <0x48028000 0x400>; 138 reg = <0x48028000 0x400>;
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d09697dab55e..42d2c61c9e2d 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -216,6 +216,13 @@
216 dma-names = "tx", "rx"; 216 dma-names = "tx", "rx";
217 }; 217 };
218 218
219 mailbox: mailbox@48094000 {
220 compatible = "ti,omap2-mailbox";
221 reg = <0x48094000 0x200>;
222 interrupts = <26>;
223 ti,hwmods = "mailbox";
224 };
225
219 timer1: timer@49018000 { 226 timer1: timer@49018000 {
220 compatible = "ti,omap2420-timer"; 227 compatible = "ti,omap2420-timer";
221 reg = <0x49018000 0x400>; 228 reg = <0x49018000 0x400>;
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index d00055809e31..25ba08331d88 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -10,18 +10,6 @@
10 cpu0-supply = <&vcc>; 10 cpu0-supply = <&vcc>;
11 }; 11 };
12 }; 12 };
13
14 vddvario: regulator-vddvario {
15 compatible = "regulator-fixed";
16 regulator-name = "vddvario";
17 regulator-always-on;
18 };
19
20 vdd33a: regulator-vdd33a {
21 compatible = "regulator-fixed";
22 regulator-name = "vdd33a";
23 regulator-always-on;
24 };
25}; 13};
26 14
27&omap3_pmx_core { 15&omap3_pmx_core {
@@ -35,58 +23,34 @@
35 23
36 hsusb0_pins: pinmux_hsusb0_pins { 24 hsusb0_pins: pinmux_hsusb0_pins {
37 pinctrl-single,pins = < 25 pinctrl-single,pins = <
38 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ 26 OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
39 OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ 27 OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
40 OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ 28 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
41 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ 29 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
42 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ 30 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
43 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ 31 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
44 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ 32 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
45 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ 33 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
46 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ 34 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
47 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ 35 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
48 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ 36 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
49 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ 37 OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
50 >; 38 >;
51 }; 39 };
52}; 40};
53 41
42#include "omap-gpmc-smsc911x.dtsi"
43
54&gpmc { 44&gpmc {
55 ranges = <5 0 0x2c000000 0x01000000>; 45 ranges = <5 0 0x2c000000 0x01000000>;
56 46
57 smsc1: ethernet@5,0 { 47 smsc1: ethernet@gpmc {
58 compatible = "smsc,lan9221", "smsc,lan9115"; 48 compatible = "smsc,lan9221", "smsc,lan9115";
59 pinctrl-names = "default"; 49 pinctrl-names = "default";
60 pinctrl-0 = <&smsc1_pins>; 50 pinctrl-0 = <&smsc1_pins>;
61 interrupt-parent = <&gpio6>; 51 interrupt-parent = <&gpio6>;
62 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 52 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
63 reg = <5 0 0xff>; 53 reg = <5 0 0xff>;
64 bank-width = <2>;
65 gpmc,mux-add-data;
66 gpmc,cs-on-ns = <0>;
67 gpmc,cs-rd-off-ns = <186>;
68 gpmc,cs-wr-off-ns = <186>;
69 gpmc,adv-on-ns = <12>;
70 gpmc,adv-rd-off-ns = <48>;
71 gpmc,adv-wr-off-ns = <48>;
72 gpmc,oe-on-ns = <54>;
73 gpmc,oe-off-ns = <168>;
74 gpmc,we-on-ns = <54>;
75 gpmc,we-off-ns = <168>;
76 gpmc,rd-cycle-ns = <186>;
77 gpmc,wr-cycle-ns = <186>;
78 gpmc,access-ns = <114>;
79 gpmc,page-burst-access-ns = <6>;
80 gpmc,bus-turnaround-ns = <12>;
81 gpmc,cycle2cycle-delay-ns = <18>;
82 gpmc,wr-data-mux-bus-ns = <90>;
83 gpmc,wr-access-ns = <186>;
84 gpmc,cycle2cycle-samecsen;
85 gpmc,cycle2cycle-diffcsen;
86 vddvario-supply = <&vddvario>;
87 vdd33a-supply = <&vdd33a>;
88 reg-io-width = <4>;
89 smsc,save-mac-address;
90 }; 54 };
91}; 55};
92 56
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index b97736d98a64..e2d163bf0619 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -107,7 +107,7 @@
107 >; 107 >;
108 }; 108 };
109 109
110 smsc911x_pins: pinmux_smsc911x_pins { 110 smsc9221_pins: pinmux_smsc9221_pins {
111 pinctrl-single,pins = < 111 pinctrl-single,pins = <
112 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 112 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
113 >; 113 >;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 7abd64f6ae21..b22caaaf774b 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep.dtsi"
13#include "omap-gpmc-smsc911x.dtsi" 13#include "omap-gpmc-smsc9221.dtsi"
14 14
15/ { 15/ {
16 model = "IGEPv2 (TI OMAP AM/DM37x)"; 16 model = "IGEPv2 (TI OMAP AM/DM37x)";
@@ -248,7 +248,7 @@
248 248
249 ethernet@gpmc { 249 ethernet@gpmc {
250 pinctrl-names = "default"; 250 pinctrl-names = "default";
251 pinctrl-0 = <&smsc911x_pins>; 251 pinctrl-0 = <&smsc9221_pins>;
252 reg = <5 0 0xff>; 252 reg = <5 0 0xff>;
253 interrupt-parent = <&gpio6>; 253 interrupt-parent = <&gpio6>;
254 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 254 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index 7909c51b05a5..d59e3de1441e 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,20 +2,6 @@
2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
3 */ 3 */
4 4
5/ {
6 vddvario_sb_t35: regulator-vddvario-sb-t35 {
7 compatible = "regulator-fixed";
8 regulator-name = "vddvario";
9 regulator-always-on;
10 };
11
12 vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
13 compatible = "regulator-fixed";
14 regulator-name = "vdd33a";
15 regulator-always-on;
16 };
17};
18
19&omap3_pmx_core { 5&omap3_pmx_core {
20 smsc2_pins: pinmux_smsc2_pins { 6 smsc2_pins: pinmux_smsc2_pins {
21 pinctrl-single,pins = < 7 pinctrl-single,pins = <
@@ -37,11 +23,10 @@
37 reg = <4 0 0xff>; 23 reg = <4 0 0xff>;
38 bank-width = <2>; 24 bank-width = <2>;
39 gpmc,mux-add-data; 25 gpmc,mux-add-data;
40 gpmc,cs-on-ns = <0>; 26 gpmc,cs-on-ns = <1>;
41 gpmc,cs-rd-off-ns = <186>; 27 gpmc,cs-rd-off-ns = <180>;
42 gpmc,cs-wr-off-ns = <186>; 28 gpmc,cs-wr-off-ns = <180>;
43 gpmc,adv-on-ns = <12>; 29 gpmc,adv-rd-off-ns = <18>;
44 gpmc,adv-rd-off-ns = <48>;
45 gpmc,adv-wr-off-ns = <48>; 30 gpmc,adv-wr-off-ns = <48>;
46 gpmc,oe-on-ns = <54>; 31 gpmc,oe-on-ns = <54>;
47 gpmc,oe-off-ns = <168>; 32 gpmc,oe-off-ns = <168>;
@@ -49,16 +34,14 @@
49 gpmc,we-off-ns = <168>; 34 gpmc,we-off-ns = <168>;
50 gpmc,rd-cycle-ns = <186>; 35 gpmc,rd-cycle-ns = <186>;
51 gpmc,wr-cycle-ns = <186>; 36 gpmc,wr-cycle-ns = <186>;
52 gpmc,access-ns = <114>; 37 gpmc,access-ns = <144>;
53 gpmc,page-burst-access-ns = <6>; 38 gpmc,page-burst-access-ns = <24>;
54 gpmc,bus-turnaround-ns = <12>; 39 gpmc,bus-turnaround-ns = <90>;
55 gpmc,cycle2cycle-delay-ns = <18>; 40 gpmc,cycle2cycle-delay-ns = <90>;
56 gpmc,wr-data-mux-bus-ns = <90>;
57 gpmc,wr-access-ns = <186>;
58 gpmc,cycle2cycle-samecsen; 41 gpmc,cycle2cycle-samecsen;
59 gpmc,cycle2cycle-diffcsen; 42 gpmc,cycle2cycle-diffcsen;
60 vddvario-supply = <&vddvario_sb_t35>; 43 vddvario-supply = <&vddvario>;
61 vdd33a-supply = <&vdd33a_sb_t35>; 44 vdd33a-supply = <&vdd33a>;
62 reg-io-width = <4>; 45 reg-io-width = <4>;
63 smsc,save-mac-address; 46 smsc,save-mac-address;
64 }; 47 };
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 024c9c6c682d..42189b65d393 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -8,6 +8,19 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3517 with CM-T3517"; 9 model = "CompuLab SBC-T3517 with CM-T3517";
10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
11
12 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
13 vddvario: regulator-vddvario-sb-t35 {
14 compatible = "regulator-fixed";
15 regulator-name = "vddvario";
16 regulator-always-on;
17 };
18
19 vdd33a: regulator-vdd33a-sb-t35 {
20 compatible = "regulator-fixed";
21 regulator-name = "vdd33a";
22 regulator-always-on;
23 };
11}; 24};
12 25
13&omap3_pmx_core { 26&omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index acb9019dc437..4231191ade06 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,7 +61,7 @@
61 ti,hwmods = "mpu"; 61 ti,hwmods = "mpu";
62 }; 62 };
63 63
64 iva { 64 iva: iva {
65 compatible = "ti,iva2.2"; 65 compatible = "ti,iva2.2";
66 ti,hwmods = "iva"; 66 ti,hwmods = "iva";
67 67
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index f8c9855ce587..36b4312a5e0d 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -630,6 +630,13 @@
630 status = "disabled"; 630 status = "disabled";
631 }; 631 };
632 632
633 mailbox: mailbox@4a0f4000 {
634 compatible = "ti,omap4-mailbox";
635 reg = <0x4a0f4000 0x200>;
636 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
637 ti,hwmods = "mailbox";
638 };
639
633 timer1: timer@4ae18000 { 640 timer1: timer@4ae18000 {
634 compatible = "ti,omap5430-timer"; 641 compatible = "ti,omap5430-timer";
635 reg = <0x4ae18000 0x80>; 642 reg = <0x4ae18000 0x80>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index eabcfdbb403a..a106b0872910 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -13,7 +13,7 @@
13#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/pinctrl/at91.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/clk/at91.h> 16#include <dt-bindings/clock/at91.h>
17 17
18/ { 18/ {
19 model = "Atmel SAMA5D3 family SoC"; 19 model = "Atmel SAMA5D3 family SoC";
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index b029fe7ef17a..1b02208ea6ff 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -9,7 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h> 12#include <dt-bindings/clock/at91.h>
13 13
14/ { 14/ {
15 ahb { 15 ahb {
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 382b04431f66..02848453ca0c 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -9,7 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h> 12#include <dt-bindings/clock/at91.h>
13 13
14/ { 14/ {
15 aliases { 15 aliases {
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index a9fa75e41652..7a8d4c6115f7 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -9,7 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h> 12#include <dt-bindings/clock/at91.h>
13 13
14/ { 14/ {
15 aliases { 15 aliases {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 32efc105df83..aba1c8a3f388 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -87,7 +87,7 @@
87 87
88 pll4: clk@01c20018 { 88 pll4: clk@01c20018 {
89 #clock-cells = <0>; 89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-a10-pll1-clk"; 90 compatible = "allwinner,sun7i-a20-pll4-clk";
91 reg = <0x01c20018 0x4>; 91 reg = <0x01c20018 0x4>;
92 clocks = <&osc24M>; 92 clocks = <&osc24M>;
93 clock-output-names = "pll4"; 93 clock-output-names = "pll4";
@@ -109,6 +109,14 @@
109 clock-output-names = "pll6_sata", "pll6_other", "pll6"; 109 clock-output-names = "pll6_sata", "pll6_other", "pll6";
110 }; 110 };
111 111
112 pll8: clk@01c20040 {
113 #clock-cells = <0>;
114 compatible = "allwinner,sun7i-a20-pll4-clk";
115 reg = <0x01c20040 0x4>;
116 clocks = <&osc24M>;
117 clock-output-names = "pll8";
118 };
119
112 cpu: cpu@01c20054 { 120 cpu: cpu@01c20054 {
113 #clock-cells = <0>; 121 #clock-cells = <0>;
114 compatible = "allwinner,sun4i-a10-cpu-clk"; 122 compatible = "allwinner,sun4i-a10-cpu-clk";
@@ -805,9 +813,9 @@
805 status = "disabled"; 813 status = "disabled";
806 }; 814 };
807 815
808 i2c4: i2c@01c2bc00 { 816 i2c4: i2c@01c2c000 {
809 compatible = "allwinner,sun4i-i2c"; 817 compatible = "allwinner,sun4i-i2c";
810 reg = <0x01c2bc00 0x400>; 818 reg = <0x01c2c000 0x400>;
811 interrupts = <0 89 4>; 819 interrupts = <0 89 4>;
812 clocks = <&apb1_gates 15>; 820 clocks = <&apb1_gates 15>;
813 clock-frequency = <100000>; 821 clock-frequency = <100000>;
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 41bca32409fc..5339009b3c0c 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1423,55 +1423,38 @@ EXPORT_SYMBOL(edma_clear_event);
1423 1423
1424#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) 1424#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1425 1425
1426static int edma_of_read_u32_to_s16_array(const struct device_node *np, 1426static int edma_xbar_event_map(struct device *dev, struct device_node *node,
1427 const char *propname, s16 *out_values, 1427 struct edma_soc_info *pdata, size_t sz)
1428 size_t sz)
1429{ 1428{
1430 int ret; 1429 const char pname[] = "ti,edma-xbar-event-map";
1431
1432 ret = of_property_read_u16_array(np, propname, out_values, sz);
1433 if (ret)
1434 return ret;
1435
1436 /* Terminate it */
1437 *out_values++ = -1;
1438 *out_values++ = -1;
1439
1440 return 0;
1441}
1442
1443static int edma_xbar_event_map(struct device *dev,
1444 struct device_node *node,
1445 struct edma_soc_info *pdata, int len)
1446{
1447 int ret, i;
1448 struct resource res; 1430 struct resource res;
1449 void __iomem *xbar; 1431 void __iomem *xbar;
1450 const s16 (*xbar_chans)[2]; 1432 s16 (*xbar_chans)[2];
1433 size_t nelm = sz / sizeof(s16);
1451 u32 shift, offset, mux; 1434 u32 shift, offset, mux;
1435 int ret, i;
1452 1436
1453 xbar_chans = devm_kzalloc(dev, 1437 xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
1454 len/sizeof(s16) + 2*sizeof(s16),
1455 GFP_KERNEL);
1456 if (!xbar_chans) 1438 if (!xbar_chans)
1457 return -ENOMEM; 1439 return -ENOMEM;
1458 1440
1459 ret = of_address_to_resource(node, 1, &res); 1441 ret = of_address_to_resource(node, 1, &res);
1460 if (ret) 1442 if (ret)
1461 return -EIO; 1443 return -ENOMEM;
1462 1444
1463 xbar = devm_ioremap(dev, res.start, resource_size(&res)); 1445 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1464 if (!xbar) 1446 if (!xbar)
1465 return -ENOMEM; 1447 return -ENOMEM;
1466 1448
1467 ret = edma_of_read_u32_to_s16_array(node, 1449 ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
1468 "ti,edma-xbar-event-map",
1469 (s16 *)xbar_chans,
1470 len/sizeof(u32));
1471 if (ret) 1450 if (ret)
1472 return -EIO; 1451 return -EIO;
1473 1452
1474 for (i = 0; xbar_chans[i][0] != -1; i++) { 1453 /* Invalidate last entry for the other user of this mess */
1454 nelm >>= 1;
1455 xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
1456
1457 for (i = 0; i < nelm; i++) {
1475 shift = (xbar_chans[i][1] & 0x03) << 3; 1458 shift = (xbar_chans[i][1] & 0x03) << 3;
1476 offset = xbar_chans[i][1] & 0xfffffffc; 1459 offset = xbar_chans[i][1] & 0xfffffffc;
1477 mux = readl(xbar + offset); 1460 mux = readl(xbar + offset);
@@ -1480,8 +1463,7 @@ static int edma_xbar_event_map(struct device *dev,
1480 writel(mux, (xbar + offset)); 1463 writel(mux, (xbar + offset));
1481 } 1464 }
1482 1465
1483 pdata->xbar_chans = xbar_chans; 1466 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
1484
1485 return 0; 1467 return 0;
1486} 1468}
1487 1469
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index b5df4a511b0a..81ba78eaf54a 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -37,7 +37,7 @@ CONFIG_SUN4I_EMAC=y
37# CONFIG_NET_VENDOR_NATSEMI is not set 37# CONFIG_NET_VENDOR_NATSEMI is not set
38# CONFIG_NET_VENDOR_SEEQ is not set 38# CONFIG_NET_VENDOR_SEEQ is not set
39# CONFIG_NET_VENDOR_SMSC is not set 39# CONFIG_NET_VENDOR_SMSC is not set
40# CONFIG_NET_VENDOR_STMICRO is not set 40CONFIG_STMMAC_ETH=y
41# CONFIG_NET_VENDOR_WIZNET is not set 41# CONFIG_NET_VENDOR_WIZNET is not set
42# CONFIG_WLAN is not set 42# CONFIG_WLAN is not set
43CONFIG_SERIAL_8250=y 43CONFIG_SERIAL_8250=y
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e92952c18e..40c5d5f1451c 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Secondary CPU startup routine source file. 2 * Secondary CPU startup routine source file.
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2014 Texas Instruments, Inc.
5 * 5 *
6 * Author: 6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com> 7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
@@ -28,9 +28,13 @@
28 * code. This routine also provides a holding flag into which 28 * code. This routine also provides a holding flag into which
29 * secondary core is held until we're ready for it to initialise. 29 * secondary core is held until we're ready for it to initialise.
30 * The primary core will update this flag using a hardware 30 * The primary core will update this flag using a hardware
31+ * register AuxCoreBoot0. 31 * register AuxCoreBoot0.
32 */ 32 */
33ENTRY(omap5_secondary_startup) 33ENTRY(omap5_secondary_startup)
34.arm
35THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
36THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
37THUMB( .thumb ) @ switch to Thumb now.
34wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 38wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
35 ldr r0, [r2] 39 ldr r0, [r2]
36 mov r0, r0, lsr #5 40 mov r0, r0, lsr #5
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index f565f9944af2..7548db2bfb8a 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -21,7 +21,7 @@ struct mv_sata_platform_data;
21#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f 21#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
22#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01 22#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
23#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs)) 23#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
24#define ORION_MBUS_SRAM_TARGET 0x00 24#define ORION_MBUS_SRAM_TARGET 0x09
25#define ORION_MBUS_SRAM_ATTR 0x00 25#define ORION_MBUS_SRAM_ATTR 0x00
26 26
27/* 27/*
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 293e2e0a0a87..00b73448b22e 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -56,6 +56,7 @@
56#include <linux/of.h> 56#include <linux/of.h>
57#include <linux/of_address.h> 57#include <linux/of_address.h>
58#include <linux/debugfs.h> 58#include <linux/debugfs.h>
59#include <linux/log2.h>
59 60
60/* 61/*
61 * DDR target is the same on all platforms. 62 * DDR target is the same on all platforms.
@@ -222,12 +223,6 @@ static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
222 */ 223 */
223 if ((u64)base < wend && end > wbase) 224 if ((u64)base < wend && end > wbase)
224 return 0; 225 return 0;
225
226 /*
227 * Check if target/attribute conflicts
228 */
229 if (target == wtarget && attr == wattr)
230 return 0;
231 } 226 }
232 227
233 return 1; 228 return 1;
@@ -266,6 +261,17 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
266 mbus->soc->win_cfg_offset(win); 261 mbus->soc->win_cfg_offset(win);
267 u32 ctrl, remap_addr; 262 u32 ctrl, remap_addr;
268 263
264 if (!is_power_of_2(size)) {
265 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
266 return -EINVAL;
267 }
268
269 if ((base & (phys_addr_t)(size - 1)) != 0) {
270 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
271 size);
272 return -EINVAL;
273 }
274
269 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) | 275 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
270 (attr << WIN_CTRL_ATTR_SHIFT) | 276 (attr << WIN_CTRL_ATTR_SHIFT) |
271 (target << WIN_CTRL_TGT_SHIFT) | 277 (target << WIN_CTRL_TGT_SHIFT) |
@@ -413,6 +419,10 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
413 win, (unsigned long long)wbase, 419 win, (unsigned long long)wbase,
414 (unsigned long long)(wbase + wsize), wtarget, wattr); 420 (unsigned long long)(wbase + wsize), wtarget, wattr);
415 421
422 if (!is_power_of_2(wsize) ||
423 ((wbase & (u64)(wsize - 1)) != 0))
424 seq_puts(seq, " (Invalid base/size!!)");
425
416 if (win < mbus->soc->num_remappable_wins) { 426 if (win < mbus->soc->num_remappable_wins) {
417 seq_printf(seq, " (remap %016llx)\n", 427 seq_printf(seq, " (remap %016llx)\n",
418 (unsigned long long)wremap); 428 (unsigned long long)wremap);
diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 110c03627051..b59a17fb7c3e 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -108,8 +108,19 @@ static int devbus_set_timing_params(struct devbus *devbus,
108 node->full_name); 108 node->full_name);
109 return err; 109 return err;
110 } 110 }
111 /* Convert bit width to byte width */ 111
112 r.bus_width /= 8; 112 /*
113 * The bus width is encoded into the register as 0 for 8 bits,
114 * and 1 for 16 bits, so we do the necessary conversion here.
115 */
116 if (r.bus_width == 8)
117 r.bus_width = 0;
118 else if (r.bus_width == 16)
119 r.bus_width = 1;
120 else {
121 dev_err(devbus->dev, "invalid bus width %d\n", r.bus_width);
122 return -EINVAL;
123 }
113 124
114 err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps", 125 err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
115 &r.badr_skew); 126 &r.badr_skew);
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index d3d1cfd51e09..e384e2534594 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -293,6 +293,58 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
293 return PCIBIOS_SUCCESSFUL; 293 return PCIBIOS_SUCCESSFUL;
294} 294}
295 295
296/*
297 * Remove windows, starting from the largest ones to the smallest
298 * ones.
299 */
300static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
301 phys_addr_t base, size_t size)
302{
303 while (size) {
304 size_t sz = 1 << (fls(size) - 1);
305
306 mvebu_mbus_del_window(base, sz);
307 base += sz;
308 size -= sz;
309 }
310}
311
312/*
313 * MBus windows can only have a power of two size, but PCI BARs do not
314 * have this constraint. Therefore, we have to split the PCI BAR into
315 * areas each having a power of two size. We start from the largest
316 * one (i.e highest order bit set in the size).
317 */
318static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
319 unsigned int target, unsigned int attribute,
320 phys_addr_t base, size_t size,
321 phys_addr_t remap)
322{
323 size_t size_mapped = 0;
324
325 while (size) {
326 size_t sz = 1 << (fls(size) - 1);
327 int ret;
328
329 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
330 sz, remap);
331 if (ret) {
332 dev_err(&port->pcie->pdev->dev,
333 "Could not create MBus window at 0x%x, size 0x%x: %d\n",
334 base, sz, ret);
335 mvebu_pcie_del_windows(port, base - size_mapped,
336 size_mapped);
337 return;
338 }
339
340 size -= sz;
341 size_mapped += sz;
342 base += sz;
343 if (remap != MVEBU_MBUS_NO_REMAP)
344 remap += sz;
345 }
346}
347
296static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 348static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
297{ 349{
298 phys_addr_t iobase; 350 phys_addr_t iobase;
@@ -304,8 +356,8 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
304 356
305 /* If a window was configured, remove it */ 357 /* If a window was configured, remove it */
306 if (port->iowin_base) { 358 if (port->iowin_base) {
307 mvebu_mbus_del_window(port->iowin_base, 359 mvebu_pcie_del_windows(port, port->iowin_base,
308 port->iowin_size); 360 port->iowin_size);
309 port->iowin_base = 0; 361 port->iowin_base = 0;
310 port->iowin_size = 0; 362 port->iowin_size = 0;
311 } 363 }
@@ -331,11 +383,11 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
331 port->iowin_base = port->pcie->io.start + iobase; 383 port->iowin_base = port->pcie->io.start + iobase;
332 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | 384 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
333 (port->bridge.iolimitupper << 16)) - 385 (port->bridge.iolimitupper << 16)) -
334 iobase); 386 iobase) + 1;
335 387
336 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr, 388 mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
337 port->iowin_base, port->iowin_size, 389 port->iowin_base, port->iowin_size,
338 iobase); 390 iobase);
339} 391}
340 392
341static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 393static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
@@ -346,8 +398,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
346 398
347 /* If a window was configured, remove it */ 399 /* If a window was configured, remove it */
348 if (port->memwin_base) { 400 if (port->memwin_base) {
349 mvebu_mbus_del_window(port->memwin_base, 401 mvebu_pcie_del_windows(port, port->memwin_base,
350 port->memwin_size); 402 port->memwin_size);
351 port->memwin_base = 0; 403 port->memwin_base = 0;
352 port->memwin_size = 0; 404 port->memwin_size = 0;
353 } 405 }
@@ -364,10 +416,11 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
364 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); 416 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
365 port->memwin_size = 417 port->memwin_size =
366 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - 418 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
367 port->memwin_base; 419 port->memwin_base + 1;
368 420
369 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr, 421 mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
370 port->memwin_base, port->memwin_size); 422 port->memwin_base, port->memwin_size,
423 MVEBU_MBUS_NO_REMAP);
371} 424}
372 425
373/* 426/*
@@ -743,14 +796,21 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
743 796
744 /* 797 /*
745 * On the PCI-to-PCI bridge side, the I/O windows must have at 798 * On the PCI-to-PCI bridge side, the I/O windows must have at
746 * least a 64 KB size and be aligned on their size, and the 799 * least a 64 KB size and the memory windows must have at
747 * memory windows must have at least a 1 MB size and be 800 * least a 1 MB size. Moreover, MBus windows need to have a
748 * aligned on their size 801 * base address aligned on their size, and their size must be
802 * a power of two. This means that if the BAR doesn't have a
803 * power of two size, several MBus windows will actually be
804 * created. We need to ensure that the biggest MBus window
805 * (which will be the first one) is aligned on its size, which
806 * explains the rounddown_pow_of_two() being done here.
749 */ 807 */
750 if (res->flags & IORESOURCE_IO) 808 if (res->flags & IORESOURCE_IO)
751 return round_up(start, max_t(resource_size_t, SZ_64K, size)); 809 return round_up(start, max_t(resource_size_t, SZ_64K,
810 rounddown_pow_of_two(size)));
752 else if (res->flags & IORESOURCE_MEM) 811 else if (res->flags & IORESOURCE_MEM)
753 return round_up(start, max_t(resource_size_t, SZ_1M, size)); 812 return round_up(start, max_t(resource_size_t, SZ_1M,
813 rounddown_pow_of_two(size)));
754 else 814 else
755 return start; 815 return start;
756} 816}
diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clock/at91.h
index 0b4cb999a3f7..0b4cb999a3f7 100644
--- a/include/dt-bindings/clk/at91.h
+++ b/include/dt-bindings/clock/at91.h