Merge branch 'irqchip/keystone' into irqchip/core

4 files changed, 276 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
new file mode 100644
index 000000000000..d9bb106bdd16
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
@@ -0,0 +1,36 @@
+Keystone 2 IRQ controller IP
+
+On Keystone SOCs, DSP cores can send interrupts to ARM
+host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
+The IRQ handler running on HOST OS can identify DSP signal source by
+analyzing SRCCx bits in IPCARx registers. This is one of the component
+used by the IPC mechanism used on Keystone SOCs.
+
+Required Properties:
+- compatible: should be "ti,keystone-irq"
+- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
+                        access device control registers and the offset inside
+                        device control registers range.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+                                         source should be 1.
+- interrupts: interrupt reference to primary interrupt controller
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+Example:
+        kirq0: keystone_irq0@026202a0 {
+                compatible = "ti,keystone-irq";
+                ti,syscon-dev = <&devctrl 0x2a0>;
+                interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        dsp0: dsp0 {
+                compatible = "linux,rproc-user";
+                ...
+                interrupt-parent = <&kirq0>;
+                interrupts = <10 2>;
+        };
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index b8632bf9a7f3..c88896478e70 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -113,3 +113,10 @@ config IRQ_CROSSBAR
           The primary irqchip invokes the crossbar's callback which inturn allocates
           a free irq and configures the IP. Thus the peripheral interrupts are
           routed to one of the free irqchip interrupt lines.
+
+config KEYSTONE_IRQ
+        tristate "Keystone 2 IRQ controller IP"
+        depends on ARCH_KEYSTONE
+        help
+                Support for Texas Instruments Keystone 2 IRQ controller IP which
+                is part of the Keystone 2 IPC mechanism
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 73052ba9ca62..69fc7fc8d1bb 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_XTENSA)			+= irq-xtensa-pic.o
 obj-$(CONFIG_XTENSA_MX)                 += irq-xtensa-mx.o
 obj-$(CONFIG_IRQ_CROSSBAR)              += irq-crossbar.o
 obj-$(CONFIG_BRCMSTB_L2_IRQ)            += irq-brcmstb-l2.o
+obj-$(CONFIG_KEYSTONE_IRQ)              += irq-keystone.o
diff --git a/drivers/irqchip/irq-keystone.c b/drivers/irqchip/irq-keystone.c
new file mode 100644
index 000000000000..608abf9c9283
--- /dev/null
+++ b/drivers/irqchip/irq-keystone.c
@@ -0,0 +1,232 @@
+/*
+ * Texas Instruments Keystone IRQ controller IP driver
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ * Author: Sajesh Kumar Saran <sajesh@ti.com>
+ *         Grygorii Strashko <grygorii.strashko@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/irq.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include "irqchip.h"
+
+
+/* The source ID bits start from 4 to 31 (total 28 bits)*/
+#define BIT_OFS                 4
+#define KEYSTONE_N_IRQ          (32 - BIT_OFS)
+
+struct keystone_irq_device {
+        struct device           *dev;
+        struct irq_chip          chip;
+        u32                      mask;
+        int                      irq;
+        struct irq_domain       *irqd;
+        struct regmap           *devctrl_regs;
+        u32                     devctrl_offset;
+};
+
+static inline u32 keystone_irq_readl(struct keystone_irq_device *kirq)
+{
+        int ret;
+        u32 val = 0;
+
+        ret = regmap_read(kirq->devctrl_regs, kirq->devctrl_offset, &val);
+        if (ret < 0)
+                dev_dbg(kirq->dev, "irq read failed ret(%d)\n", ret);
+        return val;
+}
+
+static inline void
+keystone_irq_writel(struct keystone_irq_device *kirq, u32 value)
+{
+        int ret;
+
+        ret = regmap_write(kirq->devctrl_regs, kirq->devctrl_offset, value);
+        if (ret < 0)
+                dev_dbg(kirq->dev, "irq write failed ret(%d)\n", ret);
+}
+
+static void keystone_irq_setmask(struct irq_data *d)
+{
+        struct keystone_irq_device *kirq = irq_data_get_irq_chip_data(d);
+
+        kirq->mask |= BIT(d->hwirq);
+        dev_dbg(kirq->dev, "mask %lu [%x]\n", d->hwirq, kirq->mask);
+}
+
+static void keystone_irq_unmask(struct irq_data *d)
+{
+        struct keystone_irq_device *kirq = irq_data_get_irq_chip_data(d);
+
+        kirq->mask &= ~BIT(d->hwirq);
+        dev_dbg(kirq->dev, "unmask %lu [%x]\n", d->hwirq, kirq->mask);
+}
+
+static void keystone_irq_ack(struct irq_data *d)
+{
+        /* nothing to do here */
+}
+
+static void keystone_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+        struct keystone_irq_device *kirq = irq_desc_get_handler_data(desc);
+        unsigned long pending;
+        int src, virq;
+
+        dev_dbg(kirq->dev, "start irq %d\n", irq);
+
+        chained_irq_enter(irq_desc_get_chip(desc), desc);
+
+        pending = keystone_irq_readl(kirq);
+        keystone_irq_writel(kirq, pending);
+
+        dev_dbg(kirq->dev, "pending 0x%lx, mask 0x%x\n", pending, kirq->mask);
+
+        pending = (pending >> BIT_OFS) & ~kirq->mask;
+
+        dev_dbg(kirq->dev, "pending after mask 0x%lx\n", pending);
+
+        for (src = 0; src < KEYSTONE_N_IRQ; src++) {
+                if (BIT(src) & pending) {
+                        virq = irq_find_mapping(kirq->irqd, src);
+                        dev_dbg(kirq->dev, "dispatch bit %d, virq %d\n",
+                                src, virq);
+                        if (!virq)
+                                dev_warn(kirq->dev, "sporious irq detected hwirq %d, virq %d\n",
+                                         src, virq);
+                        generic_handle_irq(virq);
+                }
+        }
+
+        chained_irq_exit(irq_desc_get_chip(desc), desc);
+
+        dev_dbg(kirq->dev, "end irq %d\n", irq);
+}