MIPS: detect presence of MAARs

Detect the presence of MAAR using the MRP bit in Config5, and record
that presence using a CPU option bit. A cpu_has_maar macro will then
allow code to conditionalise upon the presence of MAARs.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7330/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 6 insertions, 0 deletions

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index eeb5400ed4ee..e079598ae051 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -35,6 +35,9 @@
 #ifndef cpu_has_rixiex
 #define cpu_has_rixiex          (cpu_data[0].options & MIPS_CPU_RIXIEX)
 #endif
+#ifndef cpu_has_maar
+#define cpu_has_maar            (cpu_data[0].options & MIPS_CPU_MAAR)
+#endif
 
 /*
  * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 7ba2a035ad86..dfdc77ed1839 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -367,6 +367,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_EVA            0x80000000ull /* CPU supports Enhanced Virtual Addressing */
 #define MIPS_CPU_HTW            0x100000000ull /* CPU support Hardware Page Table Walker */
 #define MIPS_CPU_RIXIEX         0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
+#define MIPS_CPU_MAAR           0x400000000ull /* MAAR(I) registers are present */
 
 /*
  * CPU ASE encodings
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 66b8fe97f739..e34b10be782e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -405,6 +405,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 
         if (config5 & MIPS_CONF5_EVA)
                 c->options |= MIPS_CPU_EVA;
+        if (config5 & MIPS_CONF5_MRP)
+                c->options |= MIPS_CPU_MAAR;
 
         return config5 & MIPS_CONF_M;
 }