locking, x86, iommu: Annotate iommu->register_lock as raw

The iommu->register_lock can be taken in atomic context and therefore
must not be preempted on -rt - annotate it.

In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

4 files changed, 42 insertions, 42 deletions

diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index 3dc9befa5aec..be4164b3ebe8 100644
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -800,7 +800,7 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
                 (unsigned long long)iommu->cap,
                 (unsigned long long)iommu->ecap);
 
-        spin_lock_init(&iommu->register_lock);
+        raw_spin_lock_init(&iommu->register_lock);
 
         drhd->iommu = iommu;
         return 0;
@@ -1062,7 +1062,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
         if (!ecap_qis(iommu->ecap))
                 return;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         sts =  dmar_readq(iommu->reg + DMAR_GSTS_REG);
         if (!(sts & DMA_GSTS_QIES))
@@ -1082,7 +1082,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
                       !(sts & DMA_GSTS_QIES), sts);
 end:
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 /*
@@ -1097,7 +1097,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
         qi->free_head = qi->free_tail = 0;
         qi->free_cnt = QI_LENGTH;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         /* write zero to the tail reg */
         writel(0, iommu->reg + DMAR_IQT_REG);
@@ -1110,7 +1110,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
         /* Make sure hardware complete it */
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 /*
@@ -1225,11 +1225,11 @@ void dmar_msi_unmask(struct irq_data *data)
         unsigned long flag;
 
         /* unmask it */
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(0, iommu->reg + DMAR_FECTL_REG);
         /* Read a reg to force flush the post write */
         readl(iommu->reg + DMAR_FECTL_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 void dmar_msi_mask(struct irq_data *data)
@@ -1238,11 +1238,11 @@ void dmar_msi_mask(struct irq_data *data)
         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
 
         /* mask it */
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
         /* Read a reg to force flush the post write */
         readl(iommu->reg + DMAR_FECTL_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 void dmar_msi_write(int irq, struct msi_msg *msg)
@@ -1250,11 +1250,11 @@ void dmar_msi_write(int irq, struct msi_msg *msg)
         struct intel_iommu *iommu = irq_get_handler_data(irq);
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
         writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
         writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 void dmar_msi_read(int irq, struct msi_msg *msg)
@@ -1262,11 +1262,11 @@ void dmar_msi_read(int irq, struct msi_msg *msg)
         struct intel_iommu *iommu = irq_get_handler_data(irq);
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
         msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
         msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
@@ -1303,7 +1303,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
         u32 fault_status;
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
         if (fault_status)
                 printk(KERN_ERR "DRHD: handling fault status reg %x\n",
@@ -1342,7 +1342,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
                 writel(DMA_FRCD_F, iommu->reg + reg +
                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
 
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
+                raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 
                 dmar_fault_do_one(iommu, type, fault_reason,
                                 source_id, guest_addr);
@@ -1350,14 +1350,14 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
                 fault_index++;
                 if (fault_index >= cap_num_fault_regs(iommu->cap))
                         fault_index = 0;
-                spin_lock_irqsave(&iommu->register_lock, flag);
+                raw_spin_lock_irqsave(&iommu->register_lock, flag);
         }
 clear_rest:
         /* clear all the other faults */
         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
         writel(fault_status, iommu->reg + DMAR_FSTS_REG);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         return IRQ_HANDLED;
 }
 
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index c621c98c99da..bf4a63c2477c 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -932,7 +932,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
 
         addr = iommu->root_entry;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 
         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
@@ -941,7 +941,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_RTPS), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
@@ -952,14 +952,14 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
                 return;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 
         /* Make sure hardware complete it */
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (!(val & DMA_GSTS_WBFS)), val);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 /* return value determine if we need a write buffer flush */
@@ -986,14 +986,14 @@ static void __iommu_flush_context(struct intel_iommu *iommu,
         }
         val |= DMA_CCMD_ICC;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 
         /* Make sure hardware complete it */
         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 /* return value determine if we need a write buffer flush */
@@ -1032,7 +1032,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
         if (cap_write_drain(iommu->cap))
                 val |= DMA_TLB_WRITE_DRAIN;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         /* Note: Only uses first TLB reg currently */
         if (val_iva)
                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
@@ -1042,7 +1042,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 
         /* check IOTLB invalidation granularity */
         if (DMA_TLB_IAIG(val) == 0)
@@ -1158,7 +1158,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
         u32 pmen;
         unsigned long flags;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
         pmen = readl(iommu->reg + DMAR_PMEN_REG);
         pmen &= ~DMA_PMEN_EPM;
         writel(pmen, iommu->reg + DMAR_PMEN_REG);
@@ -1167,7 +1167,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
                 readl, !(pmen & DMA_PMEN_PRS), pmen);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 static int iommu_enable_translation(struct intel_iommu *iommu)
@@ -1175,7 +1175,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
         u32 sts;
         unsigned long flags;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
         iommu->gcmd |= DMA_GCMD_TE;
         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
@@ -1183,7 +1183,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_TES), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
         return 0;
 }
 
@@ -1192,7 +1192,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
         u32 sts;
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         iommu->gcmd &= ~DMA_GCMD_TE;
         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
@@ -1200,7 +1200,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (!(sts & DMA_GSTS_TES)), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         return 0;
 }
 
@@ -3320,7 +3320,7 @@ static int iommu_suspend(void)
         for_each_active_iommu(iommu, drhd) {
                 iommu_disable_translation(iommu);
 
-                spin_lock_irqsave(&iommu->register_lock, flag);
+                raw_spin_lock_irqsave(&iommu->register_lock, flag);
 
                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
                         readl(iommu->reg + DMAR_FECTL_REG);
@@ -3331,7 +3331,7 @@ static int iommu_suspend(void)
                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
                         readl(iommu->reg + DMAR_FEUADDR_REG);
 
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
+                raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         }
         return 0;
 
@@ -3358,7 +3358,7 @@ static void iommu_resume(void)
 
         for_each_active_iommu(iommu, drhd) {
 
-                spin_lock_irqsave(&iommu->register_lock, flag);
+                raw_spin_lock_irqsave(&iommu->register_lock, flag);
 
                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
                         iommu->reg + DMAR_FECTL_REG);
@@ -3369,7 +3369,7 @@ static void iommu_resume(void)
                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
                         iommu->reg + DMAR_FEUADDR_REG);
 
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
+                raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         }
 
         for_each_active_iommu(iommu, drhd)
diff --git a/drivers/iommu/intr_remapping.c b/drivers/iommu/intr_remapping.c
index 1a89d4a2cadf..b2443f1a13ef 100644
--- a/drivers/iommu/intr_remapping.c
+++ b/drivers/iommu/intr_remapping.c
@@ -409,7 +409,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 
         addr = virt_to_phys((void *)iommu->ir_table->base);
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
@@ -420,7 +420,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_IRTPS), sts);
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 
         /*
          * global invalidation of interrupt entry cache before enabling
@@ -428,7 +428,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
          */
         qi_global_iec(iommu);
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         /* Enable interrupt-remapping */
         iommu->gcmd |= DMA_GCMD_IRE;
@@ -437,7 +437,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_IRES), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 
@@ -485,7 +485,7 @@ static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
          */
         qi_global_iec(iommu);
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
         if (!(sts & DMA_GSTS_IRES))
@@ -498,7 +498,7 @@ static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
                       readl, !(sts & DMA_GSTS_IRES), sts);
 
 end:
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 int __init intr_remapping_supported(void)
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 9310c699a37d..19728c462399 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -311,7 +311,7 @@ struct intel_iommu {
         u64             cap;
         u64             ecap;
         u32             gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
-        spinlock_t      register_lock; /* protect register handling */
+        raw_spinlock_t  register_lock; /* protect register handling */
         int             seq_id; /* sequence id of the iommu */
         int             agaw; /* agaw of this iommu */
         int             msagaw; /* max sagaw of this iommu */