drm/i915: Store the HW min frequency as min_freq

this leaves a temporarily awkward min_delay (the soft limit) with the
new min_freq (the hardware limit). It's fixed in the next patch.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cd870fb1472..241f5e16cee6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -987,6 +987,7 @@ struct intel_gen6_power_mgmt {
         u8 rp1_delay;
         u8 rp0_delay;
         u8 hw_max;
+        u8 min_freq;
 
         bool rp_up_masked;
         bool rp_down_masked;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd3a1216eab0..dd631d19b2bd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3354,7 +3354,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 
         /* In units of 50MHz */
         dev_priv->rps.hw_max = hw_max = rp_state_cap & 0xff;
-        hw_min = (rp_state_cap >> 16) & 0xff;
+        dev_priv->rps.min_freq = hw_min = (rp_state_cap >> 16) & 0xff;
         dev_priv->rps.rp1_delay = (rp_state_cap >>  8) & 0xff;
         dev_priv->rps.rp0_delay = (rp_state_cap >>  0) & 0xff;
         dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;