diff options
author | Dave Airlie <airlied@redhat.com> | 2013-12-04 18:26:20 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2013-12-04 18:26:20 -0500 |
commit | 1ec2c7fc1100ca91ebedb583aef80a5e9aafdabd (patch) | |
tree | eedc184236e072eac631d2f00bdbb55aa942025a | |
parent | 7bc494a93f52f76595e2378e480217c95da8dbe7 (diff) | |
parent | 993fc6ebaf4af6fdfde08cc8649c386e483a5908 (diff) |
Merge tag 'drm-intel-fixes-2013-12-02' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Just flushing out my pile of bugfixes, most of them for regressions/cc:
stable. Nothing really serious going on.
For outstanding issues we still have the S4 fun due to the hsw S4
duct-tape pending (seems like I need to switch into angry maintainer mode
on that one). And there's the mode merging revert to make my g33 work
again still pending for drm core. For that one I don't have any more clue
(and it looks like no one else has a good idea either). And apparently the
locking WARN fix in here also needs to be replicated for boot, still
confirming that one though.
* tag 'drm-intel-fixes-2013-12-02' of git://people.freedesktop.org/~danvet/drm-intel:
drm/i915: Pin pages whilst allocating for dma-buf vmap()
drm/i915: MI_PREDICATE_RESULT_2 is HSW only
drm/i915: Make the DERRMR SRM target global GTT
drm/i915: use the correct force_wake function at the PC8 code
drm/i915: Fix pipe CSC post offset calculation
drm/i915: Simplify DP vs. eDP detection
drm/i915: Check VBT for eDP ports on VLV
drm/i915: use crtc_htotal in watermark calculations to match fastboot v2
drm/i915: Pin relocations for the duration of constructing the execbuffer
drm/i915: take mode config lock around crtc disable at suspend
drm/i915: Prefer setting PTE cache age to 3
drm/i915/ddi: set sink to power down mode on dp disable
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_dmabuf.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_execbuffer.c | 60 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 34 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 15 |
11 files changed, 82 insertions, 77 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 989be12cdd6e..2e367a1c6a64 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -534,8 +534,10 @@ static int i915_drm_freeze(struct drm_device *dev) | |||
534 | * Disable CRTCs directly since we want to preserve sw state | 534 | * Disable CRTCs directly since we want to preserve sw state |
535 | * for _thaw. | 535 | * for _thaw. |
536 | */ | 536 | */ |
537 | mutex_lock(&dev->mode_config.mutex); | ||
537 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | 538 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
538 | dev_priv->display.crtc_disable(crtc); | 539 | dev_priv->display.crtc_disable(crtc); |
540 | mutex_unlock(&dev->mode_config.mutex); | ||
539 | 541 | ||
540 | intel_modeset_suspend_hw(dev); | 542 | intel_modeset_suspend_hw(dev); |
541 | } | 543 | } |
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 12bbd5eac70d..621c7c67a643 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -4442,10 +4442,9 @@ i915_gem_init_hw(struct drm_device *dev) | |||
4442 | if (dev_priv->ellc_size) | 4442 | if (dev_priv->ellc_size) |
4443 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); | 4443 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4444 | 4444 | ||
4445 | if (IS_HSW_GT3(dev)) | 4445 | if (IS_HASWELL(dev)) |
4446 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); | 4446 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
4447 | else | 4447 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
4448 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); | ||
4449 | 4448 | ||
4450 | if (HAS_PCH_NOP(dev)) { | 4449 | if (HAS_PCH_NOP(dev)) { |
4451 | u32 temp = I915_READ(GEN7_MSG_CTL); | 4450 | u32 temp = I915_READ(GEN7_MSG_CTL); |
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/i915_gem_dmabuf.c index 7d5752fda5f1..9bb533e0d762 100644 --- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c | |||
@@ -125,13 +125,15 @@ static void *i915_gem_dmabuf_vmap(struct dma_buf *dma_buf) | |||
125 | 125 | ||
126 | ret = i915_gem_object_get_pages(obj); | 126 | ret = i915_gem_object_get_pages(obj); |
127 | if (ret) | 127 | if (ret) |
128 | goto error; | 128 | goto err; |
129 | |||
130 | i915_gem_object_pin_pages(obj); | ||
129 | 131 | ||
130 | ret = -ENOMEM; | 132 | ret = -ENOMEM; |
131 | 133 | ||
132 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); | 134 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); |
133 | if (pages == NULL) | 135 | if (pages == NULL) |
134 | goto error; | 136 | goto err_unpin; |
135 | 137 | ||
136 | i = 0; | 138 | i = 0; |
137 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) | 139 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) |
@@ -141,15 +143,16 @@ static void *i915_gem_dmabuf_vmap(struct dma_buf *dma_buf) | |||
141 | drm_free_large(pages); | 143 | drm_free_large(pages); |
142 | 144 | ||
143 | if (!obj->dma_buf_vmapping) | 145 | if (!obj->dma_buf_vmapping) |
144 | goto error; | 146 | goto err_unpin; |
145 | 147 | ||
146 | obj->vmapping_count = 1; | 148 | obj->vmapping_count = 1; |
147 | i915_gem_object_pin_pages(obj); | ||
148 | out_unlock: | 149 | out_unlock: |
149 | mutex_unlock(&dev->struct_mutex); | 150 | mutex_unlock(&dev->struct_mutex); |
150 | return obj->dma_buf_vmapping; | 151 | return obj->dma_buf_vmapping; |
151 | 152 | ||
152 | error: | 153 | err_unpin: |
154 | i915_gem_object_unpin_pages(obj); | ||
155 | err: | ||
153 | mutex_unlock(&dev->struct_mutex); | 156 | mutex_unlock(&dev->struct_mutex); |
154 | return ERR_PTR(ret); | 157 | return ERR_PTR(ret); |
155 | } | 158 | } |
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 885d595e0e02..b7e787fb4649 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c | |||
@@ -33,6 +33,9 @@ | |||
33 | #include "intel_drv.h" | 33 | #include "intel_drv.h" |
34 | #include <linux/dma_remapping.h> | 34 | #include <linux/dma_remapping.h> |
35 | 35 | ||
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) | ||
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | ||
38 | |||
36 | struct eb_vmas { | 39 | struct eb_vmas { |
37 | struct list_head vmas; | 40 | struct list_head vmas; |
38 | int and; | 41 | int and; |
@@ -187,7 +190,28 @@ static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) | |||
187 | } | 190 | } |
188 | } | 191 | } |
189 | 192 | ||
190 | static void eb_destroy(struct eb_vmas *eb) { | 193 | static void |
194 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | ||
195 | { | ||
196 | struct drm_i915_gem_exec_object2 *entry; | ||
197 | struct drm_i915_gem_object *obj = vma->obj; | ||
198 | |||
199 | if (!drm_mm_node_allocated(&vma->node)) | ||
200 | return; | ||
201 | |||
202 | entry = vma->exec_entry; | ||
203 | |||
204 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | ||
205 | i915_gem_object_unpin_fence(obj); | ||
206 | |||
207 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | ||
208 | i915_gem_object_unpin(obj); | ||
209 | |||
210 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | ||
211 | } | ||
212 | |||
213 | static void eb_destroy(struct eb_vmas *eb) | ||
214 | { | ||
191 | while (!list_empty(&eb->vmas)) { | 215 | while (!list_empty(&eb->vmas)) { |
192 | struct i915_vma *vma; | 216 | struct i915_vma *vma; |
193 | 217 | ||
@@ -195,6 +219,7 @@ static void eb_destroy(struct eb_vmas *eb) { | |||
195 | struct i915_vma, | 219 | struct i915_vma, |
196 | exec_list); | 220 | exec_list); |
197 | list_del_init(&vma->exec_list); | 221 | list_del_init(&vma->exec_list); |
222 | i915_gem_execbuffer_unreserve_vma(vma); | ||
198 | drm_gem_object_unreference(&vma->obj->base); | 223 | drm_gem_object_unreference(&vma->obj->base); |
199 | } | 224 | } |
200 | kfree(eb); | 225 | kfree(eb); |
@@ -478,9 +503,6 @@ i915_gem_execbuffer_relocate(struct eb_vmas *eb, | |||
478 | return ret; | 503 | return ret; |
479 | } | 504 | } |
480 | 505 | ||
481 | #define __EXEC_OBJECT_HAS_PIN (1<<31) | ||
482 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | ||
483 | |||
484 | static int | 506 | static int |
485 | need_reloc_mappable(struct i915_vma *vma) | 507 | need_reloc_mappable(struct i915_vma *vma) |
486 | { | 508 | { |
@@ -552,26 +574,6 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, | |||
552 | return 0; | 574 | return 0; |
553 | } | 575 | } |
554 | 576 | ||
555 | static void | ||
556 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | ||
557 | { | ||
558 | struct drm_i915_gem_exec_object2 *entry; | ||
559 | struct drm_i915_gem_object *obj = vma->obj; | ||
560 | |||
561 | if (!drm_mm_node_allocated(&vma->node)) | ||
562 | return; | ||
563 | |||
564 | entry = vma->exec_entry; | ||
565 | |||
566 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | ||
567 | i915_gem_object_unpin_fence(obj); | ||
568 | |||
569 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | ||
570 | i915_gem_object_unpin(obj); | ||
571 | |||
572 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | ||
573 | } | ||
574 | |||
575 | static int | 577 | static int |
576 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, | 578 | i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, |
577 | struct list_head *vmas, | 579 | struct list_head *vmas, |
@@ -670,13 +672,14 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, | |||
670 | goto err; | 672 | goto err; |
671 | } | 673 | } |
672 | 674 | ||
673 | err: /* Decrement pin count for bound objects */ | 675 | err: |
674 | list_for_each_entry(vma, vmas, exec_list) | ||
675 | i915_gem_execbuffer_unreserve_vma(vma); | ||
676 | |||
677 | if (ret != -ENOSPC || retry++) | 676 | if (ret != -ENOSPC || retry++) |
678 | return ret; | 677 | return ret; |
679 | 678 | ||
679 | /* Decrement pin count for bound objects */ | ||
680 | list_for_each_entry(vma, vmas, exec_list) | ||
681 | i915_gem_execbuffer_unreserve_vma(vma); | ||
682 | |||
680 | ret = i915_gem_evict_vm(vm, true); | 683 | ret = i915_gem_evict_vm(vm, true); |
681 | if (ret) | 684 | if (ret) |
682 | return ret; | 685 | return ret; |
@@ -708,6 +711,7 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |||
708 | while (!list_empty(&eb->vmas)) { | 711 | while (!list_empty(&eb->vmas)) { |
709 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | 712 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); |
710 | list_del_init(&vma->exec_list); | 713 | list_del_init(&vma->exec_list); |
714 | i915_gem_execbuffer_unreserve_vma(vma); | ||
711 | drm_gem_object_unreference(&vma->obj->base); | 715 | drm_gem_object_unreference(&vma->obj->base); |
712 | } | 716 | } |
713 | 717 | ||
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 3620a1b0a73c..38cb8d44a013 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -57,7 +57,9 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; | |||
57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | 57 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | 58 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | 59 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
60 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | ||
60 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | 61 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
62 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | ||
61 | 63 | ||
62 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) | 64 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
63 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) | 65 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
@@ -185,10 +187,10 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, | |||
185 | case I915_CACHE_NONE: | 187 | case I915_CACHE_NONE: |
186 | break; | 188 | break; |
187 | case I915_CACHE_WT: | 189 | case I915_CACHE_WT: |
188 | pte |= HSW_WT_ELLC_LLC_AGE0; | 190 | pte |= HSW_WT_ELLC_LLC_AGE3; |
189 | break; | 191 | break; |
190 | default: | 192 | default: |
191 | pte |= HSW_WB_ELLC_LLC_AGE0; | 193 | pte |= HSW_WB_ELLC_LLC_AGE3; |
192 | break; | 194 | break; |
193 | } | 195 | } |
194 | 196 | ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f9eafb6ed523..ee2742122a02 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -235,6 +235,7 @@ | |||
235 | */ | 235 | */ |
236 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) | 236 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) |
237 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) | 237 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1) |
238 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) | ||
238 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ | 239 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
239 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) | 240 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
240 | #define MI_INVALIDATE_TLB (1<<18) | 241 | #define MI_INVALIDATE_TLB (1<<18) |
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 330077bcd0bd..526c8ded16b0 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c | |||
@@ -173,7 +173,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) | |||
173 | ddi_translations = ddi_translations_dp; | 173 | ddi_translations = ddi_translations_dp; |
174 | break; | 174 | break; |
175 | case PORT_D: | 175 | case PORT_D: |
176 | if (intel_dpd_is_edp(dev)) | 176 | if (intel_dp_is_edp(dev, PORT_D)) |
177 | ddi_translations = ddi_translations_edp; | 177 | ddi_translations = ddi_translations_edp; |
178 | else | 178 | else |
179 | ddi_translations = ddi_translations_dp; | 179 | ddi_translations = ddi_translations_dp; |
@@ -1158,9 +1158,10 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) | |||
1158 | if (wait) | 1158 | if (wait) |
1159 | intel_wait_ddi_buf_idle(dev_priv, port); | 1159 | intel_wait_ddi_buf_idle(dev_priv, port); |
1160 | 1160 | ||
1161 | if (type == INTEL_OUTPUT_EDP) { | 1161 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
1162 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | 1162 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1163 | ironlake_edp_panel_vdd_on(intel_dp); | 1163 | ironlake_edp_panel_vdd_on(intel_dp); |
1164 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); | ||
1164 | ironlake_edp_panel_off(intel_dp); | 1165 | ironlake_edp_panel_off(intel_dp); |
1165 | } | 1166 | } |
1166 | 1167 | ||
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7ec8b488bb1d..080f6fd4e839 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -5815,7 +5815,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) | |||
5815 | uint16_t postoff = 0; | 5815 | uint16_t postoff = 0; |
5816 | 5816 | ||
5817 | if (intel_crtc->config.limited_color_range) | 5817 | if (intel_crtc->config.limited_color_range) |
5818 | postoff = (16 * (1 << 13) / 255) & 0x1fff; | 5818 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
5819 | 5819 | ||
5820 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | 5820 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
5821 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | 5821 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
@@ -6402,7 +6402,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |||
6402 | 6402 | ||
6403 | /* Make sure we're not on PC8 state before disabling PC8, otherwise | 6403 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6404 | * we'll hang the machine! */ | 6404 | * we'll hang the machine! */ |
6405 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | 6405 | gen6_gt_force_wake_get(dev_priv); |
6406 | 6406 | ||
6407 | if (val & LCPLL_POWER_DOWN_ALLOW) { | 6407 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6408 | val &= ~LCPLL_POWER_DOWN_ALLOW; | 6408 | val &= ~LCPLL_POWER_DOWN_ALLOW; |
@@ -6436,7 +6436,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |||
6436 | DRM_ERROR("Switching back to LCPLL failed\n"); | 6436 | DRM_ERROR("Switching back to LCPLL failed\n"); |
6437 | } | 6437 | } |
6438 | 6438 | ||
6439 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | 6439 | gen6_gt_force_wake_put(dev_priv); |
6440 | } | 6440 | } |
6441 | 6441 | ||
6442 | void hsw_enable_pc8_work(struct work_struct *__work) | 6442 | void hsw_enable_pc8_work(struct work_struct *__work) |
@@ -8354,7 +8354,8 @@ static int intel_gen7_queue_flip(struct drm_device *dev, | |||
8354 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | 8354 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
8355 | DERRMR_PIPEB_PRI_FLIP_DONE | | 8355 | DERRMR_PIPEB_PRI_FLIP_DONE | |
8356 | DERRMR_PIPEC_PRI_FLIP_DONE)); | 8356 | DERRMR_PIPEC_PRI_FLIP_DONE)); |
8357 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | 8357 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | |
8358 | MI_SRM_LRM_GLOBAL_GTT); | ||
8358 | intel_ring_emit(ring, DERRMR); | 8359 | intel_ring_emit(ring, DERRMR); |
8359 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | 8360 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
8360 | } | 8361 | } |
@@ -10049,7 +10050,7 @@ static void intel_setup_outputs(struct drm_device *dev) | |||
10049 | intel_ddi_init(dev, PORT_D); | 10050 | intel_ddi_init(dev, PORT_D); |
10050 | } else if (HAS_PCH_SPLIT(dev)) { | 10051 | } else if (HAS_PCH_SPLIT(dev)) { |
10051 | int found; | 10052 | int found; |
10052 | dpd_is_edp = intel_dpd_is_edp(dev); | 10053 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
10053 | 10054 | ||
10054 | if (has_edp_a(dev)) | 10055 | if (has_edp_a(dev)) |
10055 | intel_dp_init(dev, DP_A, PORT_A); | 10056 | intel_dp_init(dev, DP_A, PORT_A); |
@@ -10086,8 +10087,7 @@ static void intel_setup_outputs(struct drm_device *dev) | |||
10086 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | 10087 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
10087 | PORT_C); | 10088 | PORT_C); |
10088 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | 10089 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
10089 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | 10090 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
10090 | PORT_C); | ||
10091 | } | 10091 | } |
10092 | 10092 | ||
10093 | intel_dsi_init(dev); | 10093 | intel_dsi_init(dev); |
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0b2e842fef01..30c627c7b7ba 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -3326,11 +3326,19 @@ intel_trans_dp_port_sel(struct drm_crtc *crtc) | |||
3326 | } | 3326 | } |
3327 | 3327 | ||
3328 | /* check the VBT to see whether the eDP is on DP-D port */ | 3328 | /* check the VBT to see whether the eDP is on DP-D port */ |
3329 | bool intel_dpd_is_edp(struct drm_device *dev) | 3329 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
3330 | { | 3330 | { |
3331 | struct drm_i915_private *dev_priv = dev->dev_private; | 3331 | struct drm_i915_private *dev_priv = dev->dev_private; |
3332 | union child_device_config *p_child; | 3332 | union child_device_config *p_child; |
3333 | int i; | 3333 | int i; |
3334 | static const short port_mapping[] = { | ||
3335 | [PORT_B] = PORT_IDPB, | ||
3336 | [PORT_C] = PORT_IDPC, | ||
3337 | [PORT_D] = PORT_IDPD, | ||
3338 | }; | ||
3339 | |||
3340 | if (port == PORT_A) | ||
3341 | return true; | ||
3334 | 3342 | ||
3335 | if (!dev_priv->vbt.child_dev_num) | 3343 | if (!dev_priv->vbt.child_dev_num) |
3336 | return false; | 3344 | return false; |
@@ -3338,7 +3346,7 @@ bool intel_dpd_is_edp(struct drm_device *dev) | |||
3338 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | 3346 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3339 | p_child = dev_priv->vbt.child_dev + i; | 3347 | p_child = dev_priv->vbt.child_dev + i; |
3340 | 3348 | ||
3341 | if (p_child->common.dvo_port == PORT_IDPD && | 3349 | if (p_child->common.dvo_port == port_mapping[port] && |
3342 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == | 3350 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
3343 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | 3351 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
3344 | return true; | 3352 | return true; |
@@ -3616,26 +3624,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |||
3616 | intel_dp->DP = I915_READ(intel_dp->output_reg); | 3624 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
3617 | intel_dp->attached_connector = intel_connector; | 3625 | intel_dp->attached_connector = intel_connector; |
3618 | 3626 | ||
3619 | type = DRM_MODE_CONNECTOR_DisplayPort; | 3627 | if (intel_dp_is_edp(dev, port)) |
3620 | /* | ||
3621 | * FIXME : We need to initialize built-in panels before external panels. | ||
3622 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup | ||
3623 | */ | ||
3624 | switch (port) { | ||
3625 | case PORT_A: | ||
3626 | type = DRM_MODE_CONNECTOR_eDP; | 3628 | type = DRM_MODE_CONNECTOR_eDP; |
3627 | break; | 3629 | else |
3628 | case PORT_C: | 3630 | type = DRM_MODE_CONNECTOR_DisplayPort; |
3629 | if (IS_VALLEYVIEW(dev)) | ||
3630 | type = DRM_MODE_CONNECTOR_eDP; | ||
3631 | break; | ||
3632 | case PORT_D: | ||
3633 | if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev)) | ||
3634 | type = DRM_MODE_CONNECTOR_eDP; | ||
3635 | break; | ||
3636 | default: /* silence GCC warning */ | ||
3637 | break; | ||
3638 | } | ||
3639 | 3631 | ||
3640 | /* | 3632 | /* |
3641 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | 3633 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1e49aa8f5377..a18e88b3e425 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -708,7 +708,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |||
708 | void intel_dp_check_link_status(struct intel_dp *intel_dp); | 708 | void intel_dp_check_link_status(struct intel_dp *intel_dp); |
709 | bool intel_dp_compute_config(struct intel_encoder *encoder, | 709 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
710 | struct intel_crtc_config *pipe_config); | 710 | struct intel_crtc_config *pipe_config); |
711 | bool intel_dpd_is_edp(struct drm_device *dev); | 711 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
712 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp); | 712 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
713 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | 713 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
714 | void ironlake_edp_panel_on(struct intel_dp *intel_dp); | 714 | void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index caf2ee4e5441..6e0d5e075b15 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -1180,7 +1180,7 @@ static bool g4x_compute_wm0(struct drm_device *dev, | |||
1180 | 1180 | ||
1181 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | 1181 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1182 | clock = adjusted_mode->crtc_clock; | 1182 | clock = adjusted_mode->crtc_clock; |
1183 | htotal = adjusted_mode->htotal; | 1183 | htotal = adjusted_mode->crtc_htotal; |
1184 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; | 1184 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
1185 | pixel_size = crtc->fb->bits_per_pixel / 8; | 1185 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1186 | 1186 | ||
@@ -1267,7 +1267,7 @@ static bool g4x_compute_srwm(struct drm_device *dev, | |||
1267 | crtc = intel_get_crtc_for_plane(dev, plane); | 1267 | crtc = intel_get_crtc_for_plane(dev, plane); |
1268 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | 1268 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1269 | clock = adjusted_mode->crtc_clock; | 1269 | clock = adjusted_mode->crtc_clock; |
1270 | htotal = adjusted_mode->htotal; | 1270 | htotal = adjusted_mode->crtc_htotal; |
1271 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; | 1271 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
1272 | pixel_size = crtc->fb->bits_per_pixel / 8; | 1272 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1273 | 1273 | ||
@@ -1498,7 +1498,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc) | |||
1498 | const struct drm_display_mode *adjusted_mode = | 1498 | const struct drm_display_mode *adjusted_mode = |
1499 | &to_intel_crtc(crtc)->config.adjusted_mode; | 1499 | &to_intel_crtc(crtc)->config.adjusted_mode; |
1500 | int clock = adjusted_mode->crtc_clock; | 1500 | int clock = adjusted_mode->crtc_clock; |
1501 | int htotal = adjusted_mode->htotal; | 1501 | int htotal = adjusted_mode->crtc_htotal; |
1502 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; | 1502 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
1503 | int pixel_size = crtc->fb->bits_per_pixel / 8; | 1503 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1504 | unsigned long line_time_us; | 1504 | unsigned long line_time_us; |
@@ -1624,7 +1624,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) | |||
1624 | const struct drm_display_mode *adjusted_mode = | 1624 | const struct drm_display_mode *adjusted_mode = |
1625 | &to_intel_crtc(enabled)->config.adjusted_mode; | 1625 | &to_intel_crtc(enabled)->config.adjusted_mode; |
1626 | int clock = adjusted_mode->crtc_clock; | 1626 | int clock = adjusted_mode->crtc_clock; |
1627 | int htotal = adjusted_mode->htotal; | 1627 | int htotal = adjusted_mode->crtc_htotal; |
1628 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; | 1628 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
1629 | int pixel_size = enabled->fb->bits_per_pixel / 8; | 1629 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
1630 | unsigned long line_time_us; | 1630 | unsigned long line_time_us; |
@@ -1776,7 +1776,7 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, | |||
1776 | crtc = intel_get_crtc_for_plane(dev, plane); | 1776 | crtc = intel_get_crtc_for_plane(dev, plane); |
1777 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | 1777 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1778 | clock = adjusted_mode->crtc_clock; | 1778 | clock = adjusted_mode->crtc_clock; |
1779 | htotal = adjusted_mode->htotal; | 1779 | htotal = adjusted_mode->crtc_htotal; |
1780 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; | 1780 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
1781 | pixel_size = crtc->fb->bits_per_pixel / 8; | 1781 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1782 | 1782 | ||
@@ -2469,8 +2469,9 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |||
2469 | /* The WM are computed with base on how long it takes to fill a single | 2469 | /* The WM are computed with base on how long it takes to fill a single |
2470 | * row at the given clock rate, multiplied by 8. | 2470 | * row at the given clock rate, multiplied by 8. |
2471 | * */ | 2471 | * */ |
2472 | linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock); | 2472 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
2473 | ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, | 2473 | mode->crtc_clock); |
2474 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | ||
2474 | intel_ddi_get_cdclk_freq(dev_priv)); | 2475 | intel_ddi_get_cdclk_freq(dev_priv)); |
2475 | 2476 | ||
2476 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | | 2477 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |