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authorAlex Deucher <alexdeucher@gmail.com>2014-04-11 11:21:49 -0400
committerChristian König <christian.koenig@amd.com>2014-04-17 07:59:49 -0400
commit1ebe92802eaf0569784dce843bc28a78842d236c (patch)
tree82117b649efaef15313229bf5bde4f7e1587f7ba
parent5fb9cc4d8b1639b9a7487c1ee7b2b0c52877327d (diff)
drm/radeon: add support for newer mc ucode on SI (v2)
May fix stability issues with some newer cards. v2: print out mc firmware version used and size Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-rw-r--r--drivers/gpu/drm/radeon/radeon_ucode.h3
-rw-r--r--drivers/gpu/drm/radeon/si.c35
2 files changed, 25 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
index a77cd274dfc3..f4155484b395 100644
--- a/drivers/gpu/drm/radeon/radeon_ucode.h
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -57,6 +57,9 @@
57#define BTC_MC_UCODE_SIZE 6024 57#define BTC_MC_UCODE_SIZE 6024
58#define CAYMAN_MC_UCODE_SIZE 6037 58#define CAYMAN_MC_UCODE_SIZE 6037
59#define SI_MC_UCODE_SIZE 7769 59#define SI_MC_UCODE_SIZE 7769
60#define TAHITI_MC_UCODE_SIZE 7808
61#define PITCAIRN_MC_UCODE_SIZE 7775
62#define VERDE_MC_UCODE_SIZE 7875
60#define OLAND_MC_UCODE_SIZE 7863 63#define OLAND_MC_UCODE_SIZE 7863
61#define CIK_MC_UCODE_SIZE 7866 64#define CIK_MC_UCODE_SIZE 7866
62#define HAWAII_MC_UCODE_SIZE 7933 65#define HAWAII_MC_UCODE_SIZE 7933
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index d589475fe9e6..86f8c9c87f5c 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -39,30 +39,35 @@ MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
39MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 39MODULE_FIRMWARE("radeon/TAHITI_me.bin");
40MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 40MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
41MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 41MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
42MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
42MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 43MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
43MODULE_FIRMWARE("radeon/TAHITI_smc.bin"); 44MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
44MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 45MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
45MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 46MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
46MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 47MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
47MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 48MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
48MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 50MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
49MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin"); 51MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
50MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 52MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
51MODULE_FIRMWARE("radeon/VERDE_me.bin"); 53MODULE_FIRMWARE("radeon/VERDE_me.bin");
52MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 54MODULE_FIRMWARE("radeon/VERDE_ce.bin");
53MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 55MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
54MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 57MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
55MODULE_FIRMWARE("radeon/VERDE_smc.bin"); 58MODULE_FIRMWARE("radeon/VERDE_smc.bin");
56MODULE_FIRMWARE("radeon/OLAND_pfp.bin"); 59MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
57MODULE_FIRMWARE("radeon/OLAND_me.bin"); 60MODULE_FIRMWARE("radeon/OLAND_me.bin");
58MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 61MODULE_FIRMWARE("radeon/OLAND_ce.bin");
59MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 62MODULE_FIRMWARE("radeon/OLAND_mc.bin");
63MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
60MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 64MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
61MODULE_FIRMWARE("radeon/OLAND_smc.bin"); 65MODULE_FIRMWARE("radeon/OLAND_smc.bin");
62MODULE_FIRMWARE("radeon/HAINAN_pfp.bin"); 66MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
63MODULE_FIRMWARE("radeon/HAINAN_me.bin"); 67MODULE_FIRMWARE("radeon/HAINAN_me.bin");
64MODULE_FIRMWARE("radeon/HAINAN_ce.bin"); 68MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
65MODULE_FIRMWARE("radeon/HAINAN_mc.bin"); 69MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
70MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
66MODULE_FIRMWARE("radeon/HAINAN_rlc.bin"); 71MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
67MODULE_FIRMWARE("radeon/HAINAN_smc.bin"); 72MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
68 73
@@ -1467,7 +1472,7 @@ int si_mc_load_microcode(struct radeon_device *rdev)
1467 const __be32 *fw_data; 1472 const __be32 *fw_data;
1468 u32 running, blackout = 0; 1473 u32 running, blackout = 0;
1469 u32 *io_mc_regs; 1474 u32 *io_mc_regs;
1470 int i, ucode_size, regs_size; 1475 int i, regs_size, ucode_size = rdev->mc_fw->size / 4;
1471 1476
1472 if (!rdev->mc_fw) 1477 if (!rdev->mc_fw)
1473 return -EINVAL; 1478 return -EINVAL;
@@ -1475,28 +1480,23 @@ int si_mc_load_microcode(struct radeon_device *rdev)
1475 switch (rdev->family) { 1480 switch (rdev->family) {
1476 case CHIP_TAHITI: 1481 case CHIP_TAHITI:
1477 io_mc_regs = (u32 *)&tahiti_io_mc_regs; 1482 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1478 ucode_size = SI_MC_UCODE_SIZE;
1479 regs_size = TAHITI_IO_MC_REGS_SIZE; 1483 regs_size = TAHITI_IO_MC_REGS_SIZE;
1480 break; 1484 break;
1481 case CHIP_PITCAIRN: 1485 case CHIP_PITCAIRN:
1482 io_mc_regs = (u32 *)&pitcairn_io_mc_regs; 1486 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1483 ucode_size = SI_MC_UCODE_SIZE;
1484 regs_size = TAHITI_IO_MC_REGS_SIZE; 1487 regs_size = TAHITI_IO_MC_REGS_SIZE;
1485 break; 1488 break;
1486 case CHIP_VERDE: 1489 case CHIP_VERDE:
1487 default: 1490 default:
1488 io_mc_regs = (u32 *)&verde_io_mc_regs; 1491 io_mc_regs = (u32 *)&verde_io_mc_regs;
1489 ucode_size = SI_MC_UCODE_SIZE;
1490 regs_size = TAHITI_IO_MC_REGS_SIZE; 1492 regs_size = TAHITI_IO_MC_REGS_SIZE;
1491 break; 1493 break;
1492 case CHIP_OLAND: 1494 case CHIP_OLAND:
1493 io_mc_regs = (u32 *)&oland_io_mc_regs; 1495 io_mc_regs = (u32 *)&oland_io_mc_regs;
1494 ucode_size = OLAND_MC_UCODE_SIZE;
1495 regs_size = TAHITI_IO_MC_REGS_SIZE; 1496 regs_size = TAHITI_IO_MC_REGS_SIZE;
1496 break; 1497 break;
1497 case CHIP_HAINAN: 1498 case CHIP_HAINAN:
1498 io_mc_regs = (u32 *)&hainan_io_mc_regs; 1499 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1499 ucode_size = OLAND_MC_UCODE_SIZE;
1500 regs_size = TAHITI_IO_MC_REGS_SIZE; 1500 regs_size = TAHITI_IO_MC_REGS_SIZE;
1501 break; 1501 break;
1502 } 1502 }
@@ -1552,7 +1552,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1552 const char *chip_name; 1552 const char *chip_name;
1553 const char *rlc_chip_name; 1553 const char *rlc_chip_name;
1554 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 1554 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1555 size_t smc_req_size; 1555 size_t smc_req_size, mc2_req_size;
1556 char fw_name[30]; 1556 char fw_name[30];
1557 int err; 1557 int err;
1558 1558
@@ -1567,6 +1567,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1567 ce_req_size = SI_CE_UCODE_SIZE * 4; 1567 ce_req_size = SI_CE_UCODE_SIZE * 4;
1568 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1568 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1569 mc_req_size = SI_MC_UCODE_SIZE * 4; 1569 mc_req_size = SI_MC_UCODE_SIZE * 4;
1570 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1570 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4); 1571 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1571 break; 1572 break;
1572 case CHIP_PITCAIRN: 1573 case CHIP_PITCAIRN:
@@ -1577,6 +1578,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1577 ce_req_size = SI_CE_UCODE_SIZE * 4; 1578 ce_req_size = SI_CE_UCODE_SIZE * 4;
1578 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1579 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1579 mc_req_size = SI_MC_UCODE_SIZE * 4; 1580 mc_req_size = SI_MC_UCODE_SIZE * 4;
1581 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1580 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4); 1582 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1581 break; 1583 break;
1582 case CHIP_VERDE: 1584 case CHIP_VERDE:
@@ -1587,6 +1589,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1587 ce_req_size = SI_CE_UCODE_SIZE * 4; 1589 ce_req_size = SI_CE_UCODE_SIZE * 4;
1588 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1590 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1589 mc_req_size = SI_MC_UCODE_SIZE * 4; 1591 mc_req_size = SI_MC_UCODE_SIZE * 4;
1592 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1590 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4); 1593 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1591 break; 1594 break;
1592 case CHIP_OLAND: 1595 case CHIP_OLAND:
@@ -1596,7 +1599,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1596 me_req_size = SI_PM4_UCODE_SIZE * 4; 1599 me_req_size = SI_PM4_UCODE_SIZE * 4;
1597 ce_req_size = SI_CE_UCODE_SIZE * 4; 1600 ce_req_size = SI_CE_UCODE_SIZE * 4;
1598 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1601 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1599 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1602 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1600 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4); 1603 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1601 break; 1604 break;
1602 case CHIP_HAINAN: 1605 case CHIP_HAINAN:
@@ -1606,7 +1609,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1606 me_req_size = SI_PM4_UCODE_SIZE * 4; 1609 me_req_size = SI_PM4_UCODE_SIZE * 4;
1607 ce_req_size = SI_CE_UCODE_SIZE * 4; 1610 ce_req_size = SI_CE_UCODE_SIZE * 4;
1608 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1611 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1609 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1612 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1610 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4); 1613 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1611 break; 1614 break;
1612 default: BUG(); 1615 default: BUG();
@@ -1659,16 +1662,22 @@ static int si_init_microcode(struct radeon_device *rdev)
1659 err = -EINVAL; 1662 err = -EINVAL;
1660 } 1663 }
1661 1664
1662 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 1665 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1663 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); 1666 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1664 if (err) 1667 if (err) {
1665 goto out; 1668 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1666 if (rdev->mc_fw->size != mc_req_size) { 1669 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1670 if (err)
1671 goto out;
1672 }
1673 if ((rdev->mc_fw->size != mc_req_size) &&
1674 (rdev->mc_fw->size != mc2_req_size)) {
1667 printk(KERN_ERR 1675 printk(KERN_ERR
1668 "si_mc: Bogus length %zu in firmware \"%s\"\n", 1676 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1669 rdev->mc_fw->size, fw_name); 1677 rdev->mc_fw->size, fw_name);
1670 err = -EINVAL; 1678 err = -EINVAL;
1671 } 1679 }
1680 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1672 1681
1673 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name); 1682 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1674 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); 1683 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);