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authorJon Hunter <jon-hunter@ti.com>2012-10-04 18:01:14 -0400
committerJon Hunter <jon-hunter@ti.com>2012-11-12 17:23:54 -0500
commit1eaff71017d97ce2bc8e22b9a5cf11e5c6dd6c78 (patch)
tree3ef79ceb77fea31ebad95330c110ab07eec80dd5
parentd3004bb43de180c2f6e965716a3abe9b43c8b861 (diff)
ARM: OMAP: Don't restore DMTIMER interrupt status register
Restoring the timer interrupt status is not possible because writing a 1 to any bit in the register clears that bit if set and writing a 0 has no affect. Furthermore, if an interrupt is pending when someone attempts to disable a timer, the timer will fail to transition to the idle state and hence it's context will not be lost. Users should take care to service all interrupts before disabling the timer. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-rw-r--r--arch/arm/plat-omap/dmtimer.c5
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h1
2 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 320d10381715..f0a3c4c72a42 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -83,7 +83,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
83 83
84static void omap_timer_restore_context(struct omap_dm_timer *timer) 84static void omap_timer_restore_context(struct omap_dm_timer *timer)
85{ 85{
86 __raw_writel(timer->context.tisr, timer->irq_stat);
87 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, 86 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
88 timer->context.twer); 87 timer->context.twer);
89 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 88 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
@@ -440,7 +439,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
440 */ 439 */
441 timer->context.tclr = 440 timer->context.tclr =
442 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 441 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
443 timer->context.tisr = __raw_readl(timer->irq_stat);
444 omap_dm_timer_disable(timer); 442 omap_dm_timer_disable(timer);
445 return 0; 443 return 0;
446} 444}
@@ -684,8 +682,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
684 return -EINVAL; 682 return -EINVAL;
685 683
686 __omap_dm_timer_write_status(timer, value); 684 __omap_dm_timer_write_status(timer, value);
687 /* Save the context */ 685
688 timer->context.tisr = value;
689 return 0; 686 return 0;
690} 687}
691EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); 688EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 2f9fd1d27aef..0c07e3753470 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -84,7 +84,6 @@ struct omap_dm_timer;
84 84
85struct timer_regs { 85struct timer_regs {
86 u32 tidr; 86 u32 tidr;
87 u32 tisr;
88 u32 tier; 87 u32 tier;
89 u32 twer; 88 u32 twer;
90 u32 tclr; 89 u32 tclr;