diff options
author | Franck Bui-Huu <fbuihuu@gmail.com> | 2007-05-07 12:01:51 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 09:28:31 -0400 |
commit | 1e54f778af4467b816bf1289e7c4bf7e50067b7b (patch) | |
tree | c6b6daff71c7e26d59dc84a61fb05ff1fe3dac02 | |
parent | 0b6249567b4ecf6e9d5a8efcf149f3e7cf788cc0 (diff) |
[MIPS] Remove Momenco Ocelot G support
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/Kconfig | 23 | ||||
-rw-r--r-- | arch/mips/Makefile | 9 | ||||
-rw-r--r-- | arch/mips/configs/ocelot_g_defconfig | 981 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/Makefile | 6 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/dbg_io.c | 121 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/gt-irq.c | 212 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/irq.c | 101 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/ocelot_pld.h | 30 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/prom.c | 84 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/reset.c | 47 | ||||
-rw-r--r-- | arch/mips/momentum/ocelot_g/setup.c | 267 | ||||
-rw-r--r-- | arch/mips/pci/Makefile | 1 | ||||
-rw-r--r-- | arch/mips/pci/fixup-ocelot-g.c | 37 | ||||
-rw-r--r-- | arch/mips/pci/pci-ocelot-g.c | 97 | ||||
-rw-r--r-- | include/asm-mips/bootinfo.h | 2 | ||||
-rw-r--r-- | include/asm-mips/serial.h | 22 |
16 files changed, 4 insertions, 2036 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b684385c4e65..ea3c53966dfd 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -446,23 +446,6 @@ config MOMENCO_OCELOT_C | |||
446 | The Ocelot is a MIPS-based Single Board Computer (SBC) made by | 446 | The Ocelot is a MIPS-based Single Board Computer (SBC) made by |
447 | Momentum Computer <http://www.momenco.com/>. | 447 | Momentum Computer <http://www.momenco.com/>. |
448 | 448 | ||
449 | config MOMENCO_OCELOT_G | ||
450 | bool "Momentum Ocelot-G board" | ||
451 | select DMA_NONCOHERENT | ||
452 | select HW_HAS_PCI | ||
453 | select IRQ_CPU | ||
454 | select IRQ_CPU_RM7K | ||
455 | select PCI_MARVELL | ||
456 | select RM7000_CPU_SCACHE | ||
457 | select SWAP_IO_SPACE | ||
458 | select SYS_HAS_CPU_RM7000 | ||
459 | select SYS_SUPPORTS_32BIT_KERNEL | ||
460 | select SYS_SUPPORTS_64BIT_KERNEL if BROKEN | ||
461 | select SYS_SUPPORTS_BIG_ENDIAN | ||
462 | help | ||
463 | The Ocelot is a MIPS-based Single Board Computer (SBC) made by | ||
464 | Momentum Computer <http://www.momenco.com/>. | ||
465 | |||
466 | config MIPS_XXS1500 | 449 | config MIPS_XXS1500 |
467 | bool "MyCable XXS1500 board" | 450 | bool "MyCable XXS1500 board" |
468 | select DMA_NONCOHERENT | 451 | select DMA_NONCOHERENT |
@@ -1081,9 +1064,9 @@ config WDT_RM9000 | |||
1081 | choice | 1064 | choice |
1082 | prompt "Galileo Chip Clock" | 1065 | prompt "Galileo Chip Clock" |
1083 | #default SYSCLK_83 if MIPS_EV64120 | 1066 | #default SYSCLK_83 if MIPS_EV64120 |
1084 | depends on MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G | 1067 | depends on MIPS_EV64120 || MOMENCO_OCELOT |
1085 | default SYSCLK_83 if MIPS_EV64120 | 1068 | default SYSCLK_83 if MIPS_EV64120 |
1086 | default SYSCLK_100 if MOMENCO_OCELOT || MOMENCO_OCELOT_G | 1069 | default SYSCLK_100 if MOMENCO_OCELOT |
1087 | 1070 | ||
1088 | config SYSCLK_75 | 1071 | config SYSCLK_75 |
1089 | bool "75" if MIPS_EV64120 | 1072 | bool "75" if MIPS_EV64120 |
@@ -1092,7 +1075,7 @@ config SYSCLK_83 | |||
1092 | bool "83.3" if MIPS_EV64120 | 1075 | bool "83.3" if MIPS_EV64120 |
1093 | 1076 | ||
1094 | config SYSCLK_100 | 1077 | config SYSCLK_100 |
1095 | bool "100" if MIPS_EV64120 || MOMENCO_OCELOT || MOMENCO_OCELOT_G | 1078 | bool "100" if MIPS_EV64120 || MOMENCO_OCELOT |
1096 | 1079 | ||
1097 | endchoice | 1080 | endchoice |
1098 | 1081 | ||
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 4892db88a86a..3c85c396504b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
@@ -343,15 +343,6 @@ cflags-$(CONFIG_MOMENCO_OCELOT) += -Iinclude/asm-mips/mach-ocelot | |||
343 | load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 | 343 | load-$(CONFIG_MOMENCO_OCELOT) += 0xffffffff80100000 |
344 | 344 | ||
345 | # | 345 | # |
346 | # Momentum Ocelot-G board | ||
347 | # | ||
348 | # The Ocelot-G setup.o must be linked early - it does the ioremap() for the | ||
349 | # mips_io_port_base. | ||
350 | # | ||
351 | core-$(CONFIG_MOMENCO_OCELOT_G) += arch/mips/momentum/ocelot_g/ | ||
352 | load-$(CONFIG_MOMENCO_OCELOT_G) += 0xffffffff80100000 | ||
353 | |||
354 | # | ||
355 | # Momentum Ocelot-C and -CS boards | 346 | # Momentum Ocelot-C and -CS boards |
356 | # | 347 | # |
357 | # The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the | 348 | # The Ocelot-C[S] setup.o must be linked early - it does the ioremap() for the |
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig deleted file mode 100644 index 7078e6b3ea11..000000000000 --- a/arch/mips/configs/ocelot_g_defconfig +++ /dev/null | |||
@@ -1,981 +0,0 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.20 | ||
4 | # Tue Feb 20 21:47:36 2007 | ||
5 | # | ||
6 | CONFIG_MIPS=y | ||
7 | |||
8 | # | ||
9 | # Machine selection | ||
10 | # | ||
11 | CONFIG_ZONE_DMA=y | ||
12 | # CONFIG_MIPS_MTX1 is not set | ||
13 | # CONFIG_MIPS_BOSPORUS is not set | ||
14 | # CONFIG_MIPS_PB1000 is not set | ||
15 | # CONFIG_MIPS_PB1100 is not set | ||
16 | # CONFIG_MIPS_PB1500 is not set | ||
17 | # CONFIG_MIPS_PB1550 is not set | ||
18 | # CONFIG_MIPS_PB1200 is not set | ||
19 | # CONFIG_MIPS_DB1000 is not set | ||
20 | # CONFIG_MIPS_DB1100 is not set | ||
21 | # CONFIG_MIPS_DB1500 is not set | ||
22 | # CONFIG_MIPS_DB1550 is not set | ||
23 | # CONFIG_MIPS_DB1200 is not set | ||
24 | # CONFIG_MIPS_MIRAGE is not set | ||
25 | # CONFIG_BASLER_EXCITE is not set | ||
26 | # CONFIG_MIPS_COBALT is not set | ||
27 | # CONFIG_MACH_DECSTATION is not set | ||
28 | # CONFIG_MIPS_EV64120 is not set | ||
29 | # CONFIG_MACH_JAZZ is not set | ||
30 | # CONFIG_LASAT is not set | ||
31 | # CONFIG_MIPS_ATLAS is not set | ||
32 | # CONFIG_MIPS_MALTA is not set | ||
33 | # CONFIG_MIPS_SEAD is not set | ||
34 | # CONFIG_WR_PPMC is not set | ||
35 | # CONFIG_MIPS_SIM is not set | ||
36 | # CONFIG_MOMENCO_JAGUAR_ATX is not set | ||
37 | # CONFIG_MOMENCO_OCELOT is not set | ||
38 | # CONFIG_MOMENCO_OCELOT_3 is not set | ||
39 | # CONFIG_MOMENCO_OCELOT_C is not set | ||
40 | CONFIG_MOMENCO_OCELOT_G=y | ||
41 | # CONFIG_MIPS_XXS1500 is not set | ||
42 | # CONFIG_PNX8550_JBS is not set | ||
43 | # CONFIG_PNX8550_STB810 is not set | ||
44 | # CONFIG_DDB5477 is not set | ||
45 | # CONFIG_MACH_VR41XX is not set | ||
46 | # CONFIG_PMC_YOSEMITE is not set | ||
47 | # CONFIG_QEMU is not set | ||
48 | # CONFIG_MARKEINS is not set | ||
49 | # CONFIG_SGI_IP22 is not set | ||
50 | # CONFIG_SGI_IP27 is not set | ||
51 | # CONFIG_SGI_IP32 is not set | ||
52 | # CONFIG_SIBYTE_BIGSUR is not set | ||
53 | # CONFIG_SIBYTE_SWARM is not set | ||
54 | # CONFIG_SIBYTE_SENTOSA is not set | ||
55 | # CONFIG_SIBYTE_RHONE is not set | ||
56 | # CONFIG_SIBYTE_CARMEL is not set | ||
57 | # CONFIG_SIBYTE_PTSWARM is not set | ||
58 | # CONFIG_SIBYTE_LITTLESUR is not set | ||
59 | # CONFIG_SIBYTE_CRHINE is not set | ||
60 | # CONFIG_SIBYTE_CRHONE is not set | ||
61 | # CONFIG_SNI_RM is not set | ||
62 | # CONFIG_TOSHIBA_JMR3927 is not set | ||
63 | # CONFIG_TOSHIBA_RBTX4927 is not set | ||
64 | # CONFIG_TOSHIBA_RBTX4938 is not set | ||
65 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
66 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
67 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
68 | CONFIG_GENERIC_FIND_NEXT_BIT=y | ||
69 | CONFIG_GENERIC_HWEIGHT=y | ||
70 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
71 | CONFIG_GENERIC_TIME=y | ||
72 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | ||
73 | # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set | ||
74 | CONFIG_DMA_NONCOHERENT=y | ||
75 | CONFIG_DMA_NEED_PCI_MAP_STATE=y | ||
76 | CONFIG_CPU_BIG_ENDIAN=y | ||
77 | # CONFIG_CPU_LITTLE_ENDIAN is not set | ||
78 | CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y | ||
79 | CONFIG_IRQ_CPU=y | ||
80 | CONFIG_IRQ_CPU_RM7K=y | ||
81 | CONFIG_PCI_MARVELL=y | ||
82 | CONFIG_SWAP_IO_SPACE=y | ||
83 | # CONFIG_SYSCLK_75 is not set | ||
84 | # CONFIG_SYSCLK_83 is not set | ||
85 | CONFIG_SYSCLK_100=y | ||
86 | CONFIG_MIPS_L1_CACHE_SHIFT=5 | ||
87 | |||
88 | # | ||
89 | # CPU selection | ||
90 | # | ||
91 | # CONFIG_CPU_MIPS32_R1 is not set | ||
92 | # CONFIG_CPU_MIPS32_R2 is not set | ||
93 | # CONFIG_CPU_MIPS64_R1 is not set | ||
94 | # CONFIG_CPU_MIPS64_R2 is not set | ||
95 | # CONFIG_CPU_R3000 is not set | ||
96 | # CONFIG_CPU_TX39XX is not set | ||
97 | # CONFIG_CPU_VR41XX is not set | ||
98 | # CONFIG_CPU_R4300 is not set | ||
99 | # CONFIG_CPU_R4X00 is not set | ||
100 | # CONFIG_CPU_TX49XX is not set | ||
101 | # CONFIG_CPU_R5000 is not set | ||
102 | # CONFIG_CPU_R5432 is not set | ||
103 | # CONFIG_CPU_R6000 is not set | ||
104 | # CONFIG_CPU_NEVADA is not set | ||
105 | # CONFIG_CPU_R8000 is not set | ||
106 | # CONFIG_CPU_R10000 is not set | ||
107 | CONFIG_CPU_RM7000=y | ||
108 | # CONFIG_CPU_RM9000 is not set | ||
109 | # CONFIG_CPU_SB1 is not set | ||
110 | CONFIG_SYS_HAS_CPU_RM7000=y | ||
111 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y | ||
112 | CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y | ||
113 | CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y | ||
114 | |||
115 | # | ||
116 | # Kernel type | ||
117 | # | ||
118 | CONFIG_32BIT=y | ||
119 | # CONFIG_64BIT is not set | ||
120 | CONFIG_PAGE_SIZE_4KB=y | ||
121 | # CONFIG_PAGE_SIZE_8KB is not set | ||
122 | # CONFIG_PAGE_SIZE_16KB is not set | ||
123 | # CONFIG_PAGE_SIZE_64KB is not set | ||
124 | CONFIG_BOARD_SCACHE=y | ||
125 | CONFIG_RM7000_CPU_SCACHE=y | ||
126 | CONFIG_CPU_HAS_PREFETCH=y | ||
127 | CONFIG_MIPS_MT_DISABLED=y | ||
128 | # CONFIG_MIPS_MT_SMP is not set | ||
129 | # CONFIG_MIPS_MT_SMTC is not set | ||
130 | # CONFIG_MIPS_VPE_LOADER is not set | ||
131 | # CONFIG_64BIT_PHYS_ADDR is not set | ||
132 | CONFIG_CPU_HAS_LLSC=y | ||
133 | CONFIG_CPU_HAS_SYNC=y | ||
134 | CONFIG_GENERIC_HARDIRQS=y | ||
135 | CONFIG_GENERIC_IRQ_PROBE=y | ||
136 | CONFIG_CPU_SUPPORTS_HIGHMEM=y | ||
137 | CONFIG_ARCH_FLATMEM_ENABLE=y | ||
138 | CONFIG_SELECT_MEMORY_MODEL=y | ||
139 | CONFIG_FLATMEM_MANUAL=y | ||
140 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
141 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
142 | CONFIG_FLATMEM=y | ||
143 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
144 | # CONFIG_SPARSEMEM_STATIC is not set | ||
145 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
146 | CONFIG_RESOURCES_64BIT=y | ||
147 | CONFIG_ZONE_DMA_FLAG=1 | ||
148 | # CONFIG_HZ_48 is not set | ||
149 | # CONFIG_HZ_100 is not set | ||
150 | # CONFIG_HZ_128 is not set | ||
151 | # CONFIG_HZ_250 is not set | ||
152 | # CONFIG_HZ_256 is not set | ||
153 | CONFIG_HZ_1000=y | ||
154 | # CONFIG_HZ_1024 is not set | ||
155 | CONFIG_SYS_SUPPORTS_ARBIT_HZ=y | ||
156 | CONFIG_HZ=1000 | ||
157 | CONFIG_PREEMPT_NONE=y | ||
158 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
159 | # CONFIG_PREEMPT is not set | ||
160 | # CONFIG_KEXEC is not set | ||
161 | CONFIG_LOCKDEP_SUPPORT=y | ||
162 | CONFIG_STACKTRACE_SUPPORT=y | ||
163 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
164 | |||
165 | # | ||
166 | # Code maturity level options | ||
167 | # | ||
168 | CONFIG_EXPERIMENTAL=y | ||
169 | CONFIG_BROKEN_ON_SMP=y | ||
170 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
171 | |||
172 | # | ||
173 | # General setup | ||
174 | # | ||
175 | CONFIG_LOCALVERSION="" | ||
176 | CONFIG_LOCALVERSION_AUTO=y | ||
177 | CONFIG_SWAP=y | ||
178 | CONFIG_SYSVIPC=y | ||
179 | # CONFIG_IPC_NS is not set | ||
180 | CONFIG_SYSVIPC_SYSCTL=y | ||
181 | # CONFIG_POSIX_MQUEUE is not set | ||
182 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
183 | # CONFIG_TASKSTATS is not set | ||
184 | # CONFIG_UTS_NS is not set | ||
185 | # CONFIG_AUDIT is not set | ||
186 | # CONFIG_IKCONFIG is not set | ||
187 | CONFIG_SYSFS_DEPRECATED=y | ||
188 | CONFIG_RELAY=y | ||
189 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
190 | CONFIG_SYSCTL=y | ||
191 | CONFIG_EMBEDDED=y | ||
192 | CONFIG_SYSCTL_SYSCALL=y | ||
193 | CONFIG_KALLSYMS=y | ||
194 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
195 | CONFIG_HOTPLUG=y | ||
196 | CONFIG_PRINTK=y | ||
197 | CONFIG_BUG=y | ||
198 | CONFIG_ELF_CORE=y | ||
199 | CONFIG_BASE_FULL=y | ||
200 | CONFIG_FUTEX=y | ||
201 | CONFIG_EPOLL=y | ||
202 | CONFIG_SHMEM=y | ||
203 | CONFIG_SLAB=y | ||
204 | CONFIG_VM_EVENT_COUNTERS=y | ||
205 | CONFIG_RT_MUTEXES=y | ||
206 | # CONFIG_TINY_SHMEM is not set | ||
207 | CONFIG_BASE_SMALL=0 | ||
208 | # CONFIG_SLOB is not set | ||
209 | |||
210 | # | ||
211 | # Loadable module support | ||
212 | # | ||
213 | # CONFIG_MODULES is not set | ||
214 | |||
215 | # | ||
216 | # Block layer | ||
217 | # | ||
218 | CONFIG_BLOCK=y | ||
219 | # CONFIG_LBD is not set | ||
220 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
221 | CONFIG_LSF=y | ||
222 | |||
223 | # | ||
224 | # IO Schedulers | ||
225 | # | ||
226 | CONFIG_IOSCHED_NOOP=y | ||
227 | CONFIG_IOSCHED_AS=y | ||
228 | CONFIG_IOSCHED_DEADLINE=y | ||
229 | CONFIG_IOSCHED_CFQ=y | ||
230 | CONFIG_DEFAULT_AS=y | ||
231 | # CONFIG_DEFAULT_DEADLINE is not set | ||
232 | # CONFIG_DEFAULT_CFQ is not set | ||
233 | # CONFIG_DEFAULT_NOOP is not set | ||
234 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
235 | |||
236 | # | ||
237 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) | ||
238 | # | ||
239 | CONFIG_HW_HAS_PCI=y | ||
240 | CONFIG_PCI=y | ||
241 | CONFIG_MMU=y | ||
242 | |||
243 | # | ||
244 | # PCCARD (PCMCIA/CardBus) support | ||
245 | # | ||
246 | # CONFIG_PCCARD is not set | ||
247 | |||
248 | # | ||
249 | # PCI Hotplug Support | ||
250 | # | ||
251 | # CONFIG_HOTPLUG_PCI is not set | ||
252 | |||
253 | # | ||
254 | # Executable file formats | ||
255 | # | ||
256 | CONFIG_BINFMT_ELF=y | ||
257 | # CONFIG_BINFMT_MISC is not set | ||
258 | CONFIG_TRAD_SIGNALS=y | ||
259 | |||
260 | # | ||
261 | # Power management options | ||
262 | # | ||
263 | CONFIG_PM=y | ||
264 | # CONFIG_PM_LEGACY is not set | ||
265 | # CONFIG_PM_DEBUG is not set | ||
266 | # CONFIG_PM_SYSFS_DEPRECATED is not set | ||
267 | |||
268 | # | ||
269 | # Networking | ||
270 | # | ||
271 | CONFIG_NET=y | ||
272 | |||
273 | # | ||
274 | # Networking options | ||
275 | # | ||
276 | # CONFIG_NETDEBUG is not set | ||
277 | # CONFIG_PACKET is not set | ||
278 | CONFIG_UNIX=y | ||
279 | CONFIG_XFRM=y | ||
280 | CONFIG_XFRM_USER=y | ||
281 | # CONFIG_XFRM_SUB_POLICY is not set | ||
282 | CONFIG_XFRM_MIGRATE=y | ||
283 | CONFIG_NET_KEY=y | ||
284 | CONFIG_NET_KEY_MIGRATE=y | ||
285 | CONFIG_INET=y | ||
286 | # CONFIG_IP_MULTICAST is not set | ||
287 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
288 | CONFIG_IP_FIB_HASH=y | ||
289 | CONFIG_IP_PNP=y | ||
290 | CONFIG_IP_PNP_DHCP=y | ||
291 | # CONFIG_IP_PNP_BOOTP is not set | ||
292 | # CONFIG_IP_PNP_RARP is not set | ||
293 | # CONFIG_NET_IPIP is not set | ||
294 | # CONFIG_NET_IPGRE is not set | ||
295 | # CONFIG_ARPD is not set | ||
296 | # CONFIG_SYN_COOKIES is not set | ||
297 | # CONFIG_INET_AH is not set | ||
298 | # CONFIG_INET_ESP is not set | ||
299 | # CONFIG_INET_IPCOMP is not set | ||
300 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
301 | # CONFIG_INET_TUNNEL is not set | ||
302 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
303 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
304 | CONFIG_INET_XFRM_MODE_BEET=y | ||
305 | CONFIG_INET_DIAG=y | ||
306 | CONFIG_INET_TCP_DIAG=y | ||
307 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
308 | CONFIG_TCP_CONG_CUBIC=y | ||
309 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
310 | CONFIG_TCP_MD5SIG=y | ||
311 | # CONFIG_IPV6 is not set | ||
312 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
313 | # CONFIG_INET6_TUNNEL is not set | ||
314 | CONFIG_NETWORK_SECMARK=y | ||
315 | # CONFIG_NETFILTER is not set | ||
316 | |||
317 | # | ||
318 | # DCCP Configuration (EXPERIMENTAL) | ||
319 | # | ||
320 | # CONFIG_IP_DCCP is not set | ||
321 | |||
322 | # | ||
323 | # SCTP Configuration (EXPERIMENTAL) | ||
324 | # | ||
325 | # CONFIG_IP_SCTP is not set | ||
326 | |||
327 | # | ||
328 | # TIPC Configuration (EXPERIMENTAL) | ||
329 | # | ||
330 | # CONFIG_TIPC is not set | ||
331 | # CONFIG_ATM is not set | ||
332 | # CONFIG_BRIDGE is not set | ||
333 | # CONFIG_VLAN_8021Q is not set | ||
334 | # CONFIG_DECNET is not set | ||
335 | # CONFIG_LLC2 is not set | ||
336 | # CONFIG_IPX is not set | ||
337 | # CONFIG_ATALK is not set | ||
338 | # CONFIG_X25 is not set | ||
339 | # CONFIG_LAPB is not set | ||
340 | # CONFIG_ECONET is not set | ||
341 | # CONFIG_WAN_ROUTER is not set | ||
342 | |||
343 | # | ||
344 | # QoS and/or fair queueing | ||
345 | # | ||
346 | # CONFIG_NET_SCHED is not set | ||
347 | |||
348 | # | ||
349 | # Network testing | ||
350 | # | ||
351 | # CONFIG_NET_PKTGEN is not set | ||
352 | # CONFIG_HAMRADIO is not set | ||
353 | # CONFIG_IRDA is not set | ||
354 | # CONFIG_BT is not set | ||
355 | CONFIG_IEEE80211=y | ||
356 | # CONFIG_IEEE80211_DEBUG is not set | ||
357 | CONFIG_IEEE80211_CRYPT_WEP=y | ||
358 | CONFIG_IEEE80211_CRYPT_CCMP=y | ||
359 | CONFIG_IEEE80211_SOFTMAC=y | ||
360 | # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set | ||
361 | CONFIG_WIRELESS_EXT=y | ||
362 | |||
363 | # | ||
364 | # Device Drivers | ||
365 | # | ||
366 | |||
367 | # | ||
368 | # Generic Driver Options | ||
369 | # | ||
370 | CONFIG_STANDALONE=y | ||
371 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
372 | CONFIG_FW_LOADER=y | ||
373 | # CONFIG_SYS_HYPERVISOR is not set | ||
374 | |||
375 | # | ||
376 | # Connector - unified userspace <-> kernelspace linker | ||
377 | # | ||
378 | CONFIG_CONNECTOR=y | ||
379 | CONFIG_PROC_EVENTS=y | ||
380 | |||
381 | # | ||
382 | # Memory Technology Devices (MTD) | ||
383 | # | ||
384 | # CONFIG_MTD is not set | ||
385 | |||
386 | # | ||
387 | # Parallel port support | ||
388 | # | ||
389 | # CONFIG_PARPORT is not set | ||
390 | |||
391 | # | ||
392 | # Plug and Play support | ||
393 | # | ||
394 | # CONFIG_PNPACPI is not set | ||
395 | |||
396 | # | ||
397 | # Block devices | ||
398 | # | ||
399 | # CONFIG_BLK_CPQ_DA is not set | ||
400 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
401 | # CONFIG_BLK_DEV_DAC960 is not set | ||
402 | # CONFIG_BLK_DEV_UMEM is not set | ||
403 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
404 | # CONFIG_BLK_DEV_LOOP is not set | ||
405 | # CONFIG_BLK_DEV_NBD is not set | ||
406 | # CONFIG_BLK_DEV_SX8 is not set | ||
407 | # CONFIG_BLK_DEV_RAM is not set | ||
408 | # CONFIG_BLK_DEV_INITRD is not set | ||
409 | CONFIG_CDROM_PKTCDVD=y | ||
410 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
411 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
412 | CONFIG_ATA_OVER_ETH=y | ||
413 | |||
414 | # | ||
415 | # Misc devices | ||
416 | # | ||
417 | CONFIG_SGI_IOC4=y | ||
418 | # CONFIG_TIFM_CORE is not set | ||
419 | |||
420 | # | ||
421 | # ATA/ATAPI/MFM/RLL support | ||
422 | # | ||
423 | # CONFIG_IDE is not set | ||
424 | |||
425 | # | ||
426 | # SCSI device support | ||
427 | # | ||
428 | CONFIG_RAID_ATTRS=y | ||
429 | # CONFIG_SCSI is not set | ||
430 | # CONFIG_SCSI_NETLINK is not set | ||
431 | |||
432 | # | ||
433 | # Serial ATA (prod) and Parallel ATA (experimental) drivers | ||
434 | # | ||
435 | # CONFIG_ATA is not set | ||
436 | |||
437 | # | ||
438 | # Multi-device support (RAID and LVM) | ||
439 | # | ||
440 | # CONFIG_MD is not set | ||
441 | |||
442 | # | ||
443 | # Fusion MPT device support | ||
444 | # | ||
445 | # CONFIG_FUSION is not set | ||
446 | |||
447 | # | ||
448 | # IEEE 1394 (FireWire) support | ||
449 | # | ||
450 | # CONFIG_IEEE1394 is not set | ||
451 | |||
452 | # | ||
453 | # I2O device support | ||
454 | # | ||
455 | # CONFIG_I2O is not set | ||
456 | |||
457 | # | ||
458 | # Network device support | ||
459 | # | ||
460 | CONFIG_NETDEVICES=y | ||
461 | # CONFIG_DUMMY is not set | ||
462 | # CONFIG_BONDING is not set | ||
463 | # CONFIG_EQUALIZER is not set | ||
464 | # CONFIG_TUN is not set | ||
465 | |||
466 | # | ||
467 | # ARCnet devices | ||
468 | # | ||
469 | # CONFIG_ARCNET is not set | ||
470 | |||
471 | # | ||
472 | # PHY device support | ||
473 | # | ||
474 | CONFIG_PHYLIB=y | ||
475 | |||
476 | # | ||
477 | # MII PHY device drivers | ||
478 | # | ||
479 | CONFIG_MARVELL_PHY=y | ||
480 | CONFIG_DAVICOM_PHY=y | ||
481 | CONFIG_QSEMI_PHY=y | ||
482 | CONFIG_LXT_PHY=y | ||
483 | CONFIG_CICADA_PHY=y | ||
484 | CONFIG_VITESSE_PHY=y | ||
485 | CONFIG_SMSC_PHY=y | ||
486 | # CONFIG_BROADCOM_PHY is not set | ||
487 | # CONFIG_FIXED_PHY is not set | ||
488 | |||
489 | # | ||
490 | # Ethernet (10 or 100Mbit) | ||
491 | # | ||
492 | CONFIG_NET_ETHERNET=y | ||
493 | CONFIG_MII=y | ||
494 | CONFIG_GALILEO_64240_ETH=y | ||
495 | # CONFIG_HAPPYMEAL is not set | ||
496 | # CONFIG_SUNGEM is not set | ||
497 | # CONFIG_CASSINI is not set | ||
498 | # CONFIG_NET_VENDOR_3COM is not set | ||
499 | # CONFIG_DM9000 is not set | ||
500 | |||
501 | # | ||
502 | # Tulip family network device support | ||
503 | # | ||
504 | # CONFIG_NET_TULIP is not set | ||
505 | # CONFIG_HP100 is not set | ||
506 | # CONFIG_NET_PCI is not set | ||
507 | |||
508 | # | ||
509 | # Ethernet (1000 Mbit) | ||
510 | # | ||
511 | # CONFIG_ACENIC is not set | ||
512 | # CONFIG_DL2K is not set | ||
513 | # CONFIG_E1000 is not set | ||
514 | # CONFIG_NS83820 is not set | ||
515 | # CONFIG_HAMACHI is not set | ||
516 | # CONFIG_YELLOWFIN is not set | ||
517 | # CONFIG_R8169 is not set | ||
518 | # CONFIG_SIS190 is not set | ||
519 | # CONFIG_SKGE is not set | ||
520 | # CONFIG_SKY2 is not set | ||
521 | # CONFIG_SK98LIN is not set | ||
522 | # CONFIG_TIGON3 is not set | ||
523 | # CONFIG_BNX2 is not set | ||
524 | CONFIG_QLA3XXX=y | ||
525 | # CONFIG_ATL1 is not set | ||
526 | |||
527 | # | ||
528 | # Ethernet (10000 Mbit) | ||
529 | # | ||
530 | # CONFIG_CHELSIO_T1 is not set | ||
531 | CONFIG_CHELSIO_T3=y | ||
532 | # CONFIG_IXGB is not set | ||
533 | # CONFIG_S2IO is not set | ||
534 | # CONFIG_MYRI10GE is not set | ||
535 | CONFIG_NETXEN_NIC=y | ||
536 | |||
537 | # | ||
538 | # Token Ring devices | ||
539 | # | ||
540 | # CONFIG_TR is not set | ||
541 | |||
542 | # | ||
543 | # Wireless LAN (non-hamradio) | ||
544 | # | ||
545 | # CONFIG_NET_RADIO is not set | ||
546 | |||
547 | # | ||
548 | # Wan interfaces | ||
549 | # | ||
550 | # CONFIG_WAN is not set | ||
551 | # CONFIG_FDDI is not set | ||
552 | # CONFIG_HIPPI is not set | ||
553 | # CONFIG_PPP is not set | ||
554 | # CONFIG_SLIP is not set | ||
555 | # CONFIG_SHAPER is not set | ||
556 | # CONFIG_NETCONSOLE is not set | ||
557 | # CONFIG_NETPOLL is not set | ||
558 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
559 | |||
560 | # | ||
561 | # ISDN subsystem | ||
562 | # | ||
563 | # CONFIG_ISDN is not set | ||
564 | |||
565 | # | ||
566 | # Telephony Support | ||
567 | # | ||
568 | # CONFIG_PHONE is not set | ||
569 | |||
570 | # | ||
571 | # Input device support | ||
572 | # | ||
573 | CONFIG_INPUT=y | ||
574 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
575 | |||
576 | # | ||
577 | # Userland interfaces | ||
578 | # | ||
579 | CONFIG_INPUT_MOUSEDEV=y | ||
580 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
581 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
582 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
583 | # CONFIG_INPUT_JOYDEV is not set | ||
584 | # CONFIG_INPUT_TSDEV is not set | ||
585 | # CONFIG_INPUT_EVDEV is not set | ||
586 | # CONFIG_INPUT_EVBUG is not set | ||
587 | |||
588 | # | ||
589 | # Input Device Drivers | ||
590 | # | ||
591 | # CONFIG_INPUT_KEYBOARD is not set | ||
592 | # CONFIG_INPUT_MOUSE is not set | ||
593 | # CONFIG_INPUT_JOYSTICK is not set | ||
594 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
595 | # CONFIG_INPUT_MISC is not set | ||
596 | |||
597 | # | ||
598 | # Hardware I/O ports | ||
599 | # | ||
600 | CONFIG_SERIO=y | ||
601 | # CONFIG_SERIO_I8042 is not set | ||
602 | CONFIG_SERIO_SERPORT=y | ||
603 | # CONFIG_SERIO_PCIPS2 is not set | ||
604 | # CONFIG_SERIO_LIBPS2 is not set | ||
605 | CONFIG_SERIO_RAW=y | ||
606 | # CONFIG_GAMEPORT is not set | ||
607 | |||
608 | # | ||
609 | # Character devices | ||
610 | # | ||
611 | CONFIG_VT=y | ||
612 | CONFIG_VT_CONSOLE=y | ||
613 | CONFIG_HW_CONSOLE=y | ||
614 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
615 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
616 | |||
617 | # | ||
618 | # Serial drivers | ||
619 | # | ||
620 | CONFIG_SERIAL_8250=y | ||
621 | CONFIG_SERIAL_8250_CONSOLE=y | ||
622 | CONFIG_SERIAL_8250_PCI=y | ||
623 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
624 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
625 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
626 | |||
627 | # | ||
628 | # Non-8250 serial port support | ||
629 | # | ||
630 | CONFIG_SERIAL_CORE=y | ||
631 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
632 | # CONFIG_SERIAL_JSM is not set | ||
633 | CONFIG_UNIX98_PTYS=y | ||
634 | CONFIG_LEGACY_PTYS=y | ||
635 | CONFIG_LEGACY_PTY_COUNT=256 | ||
636 | |||
637 | # | ||
638 | # IPMI | ||
639 | # | ||
640 | # CONFIG_IPMI_HANDLER is not set | ||
641 | |||
642 | # | ||
643 | # Watchdog Cards | ||
644 | # | ||
645 | # CONFIG_WATCHDOG is not set | ||
646 | # CONFIG_HW_RANDOM is not set | ||
647 | # CONFIG_RTC is not set | ||
648 | # CONFIG_GEN_RTC is not set | ||
649 | # CONFIG_DTLK is not set | ||
650 | # CONFIG_R3964 is not set | ||
651 | # CONFIG_APPLICOM is not set | ||
652 | # CONFIG_DRM is not set | ||
653 | # CONFIG_RAW_DRIVER is not set | ||
654 | |||
655 | # | ||
656 | # TPM devices | ||
657 | # | ||
658 | # CONFIG_TCG_TPM is not set | ||
659 | |||
660 | # | ||
661 | # I2C support | ||
662 | # | ||
663 | # CONFIG_I2C is not set | ||
664 | |||
665 | # | ||
666 | # SPI support | ||
667 | # | ||
668 | # CONFIG_SPI is not set | ||
669 | # CONFIG_SPI_MASTER is not set | ||
670 | |||
671 | # | ||
672 | # Dallas's 1-wire bus | ||
673 | # | ||
674 | # CONFIG_W1 is not set | ||
675 | |||
676 | # | ||
677 | # Hardware Monitoring support | ||
678 | # | ||
679 | # CONFIG_HWMON is not set | ||
680 | # CONFIG_HWMON_VID is not set | ||
681 | |||
682 | # | ||
683 | # Multimedia devices | ||
684 | # | ||
685 | # CONFIG_VIDEO_DEV is not set | ||
686 | |||
687 | # | ||
688 | # Digital Video Broadcasting Devices | ||
689 | # | ||
690 | # CONFIG_DVB is not set | ||
691 | |||
692 | # | ||
693 | # Graphics support | ||
694 | # | ||
695 | # CONFIG_FIRMWARE_EDID is not set | ||
696 | # CONFIG_FB is not set | ||
697 | |||
698 | # | ||
699 | # Console display driver support | ||
700 | # | ||
701 | # CONFIG_VGA_CONSOLE is not set | ||
702 | CONFIG_DUMMY_CONSOLE=y | ||
703 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
704 | |||
705 | # | ||
706 | # Sound | ||
707 | # | ||
708 | # CONFIG_SOUND is not set | ||
709 | |||
710 | # | ||
711 | # HID Devices | ||
712 | # | ||
713 | # CONFIG_HID is not set | ||
714 | |||
715 | # | ||
716 | # USB support | ||
717 | # | ||
718 | CONFIG_USB_ARCH_HAS_HCD=y | ||
719 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
720 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
721 | # CONFIG_USB is not set | ||
722 | |||
723 | # | ||
724 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
725 | # | ||
726 | |||
727 | # | ||
728 | # USB Gadget Support | ||
729 | # | ||
730 | # CONFIG_USB_GADGET is not set | ||
731 | |||
732 | # | ||
733 | # MMC/SD Card support | ||
734 | # | ||
735 | # CONFIG_MMC is not set | ||
736 | |||
737 | # | ||
738 | # LED devices | ||
739 | # | ||
740 | # CONFIG_NEW_LEDS is not set | ||
741 | |||
742 | # | ||
743 | # LED drivers | ||
744 | # | ||
745 | |||
746 | # | ||
747 | # LED Triggers | ||
748 | # | ||
749 | |||
750 | # | ||
751 | # InfiniBand support | ||
752 | # | ||
753 | # CONFIG_INFINIBAND is not set | ||
754 | |||
755 | # | ||
756 | # EDAC - error detection and reporting (RAS) (EXPERIMENTAL) | ||
757 | # | ||
758 | |||
759 | # | ||
760 | # Real Time Clock | ||
761 | # | ||
762 | # CONFIG_RTC_CLASS is not set | ||
763 | |||
764 | # | ||
765 | # DMA Engine support | ||
766 | # | ||
767 | # CONFIG_DMA_ENGINE is not set | ||
768 | |||
769 | # | ||
770 | # DMA Clients | ||
771 | # | ||
772 | |||
773 | # | ||
774 | # DMA Devices | ||
775 | # | ||
776 | |||
777 | # | ||
778 | # Auxiliary Display support | ||
779 | # | ||
780 | |||
781 | # | ||
782 | # Virtualization | ||
783 | # | ||
784 | |||
785 | # | ||
786 | # File systems | ||
787 | # | ||
788 | CONFIG_EXT2_FS=y | ||
789 | # CONFIG_EXT2_FS_XATTR is not set | ||
790 | # CONFIG_EXT2_FS_XIP is not set | ||
791 | # CONFIG_EXT3_FS is not set | ||
792 | # CONFIG_EXT4DEV_FS is not set | ||
793 | # CONFIG_REISERFS_FS is not set | ||
794 | # CONFIG_JFS_FS is not set | ||
795 | CONFIG_FS_POSIX_ACL=y | ||
796 | # CONFIG_XFS_FS is not set | ||
797 | # CONFIG_GFS2_FS is not set | ||
798 | # CONFIG_OCFS2_FS is not set | ||
799 | # CONFIG_MINIX_FS is not set | ||
800 | # CONFIG_ROMFS_FS is not set | ||
801 | CONFIG_INOTIFY=y | ||
802 | CONFIG_INOTIFY_USER=y | ||
803 | # CONFIG_QUOTA is not set | ||
804 | CONFIG_DNOTIFY=y | ||
805 | # CONFIG_AUTOFS_FS is not set | ||
806 | # CONFIG_AUTOFS4_FS is not set | ||
807 | CONFIG_FUSE_FS=y | ||
808 | CONFIG_GENERIC_ACL=y | ||
809 | |||
810 | # | ||
811 | # CD-ROM/DVD Filesystems | ||
812 | # | ||
813 | # CONFIG_ISO9660_FS is not set | ||
814 | # CONFIG_UDF_FS is not set | ||
815 | |||
816 | # | ||
817 | # DOS/FAT/NT Filesystems | ||
818 | # | ||
819 | # CONFIG_MSDOS_FS is not set | ||
820 | # CONFIG_VFAT_FS is not set | ||
821 | # CONFIG_NTFS_FS is not set | ||
822 | |||
823 | # | ||
824 | # Pseudo filesystems | ||
825 | # | ||
826 | CONFIG_PROC_FS=y | ||
827 | CONFIG_PROC_KCORE=y | ||
828 | CONFIG_PROC_SYSCTL=y | ||
829 | CONFIG_SYSFS=y | ||
830 | CONFIG_TMPFS=y | ||
831 | CONFIG_TMPFS_POSIX_ACL=y | ||
832 | # CONFIG_HUGETLB_PAGE is not set | ||
833 | CONFIG_RAMFS=y | ||
834 | CONFIG_CONFIGFS_FS=y | ||
835 | |||
836 | # | ||
837 | # Miscellaneous filesystems | ||
838 | # | ||
839 | # CONFIG_ADFS_FS is not set | ||
840 | # CONFIG_AFFS_FS is not set | ||
841 | # CONFIG_ECRYPT_FS is not set | ||
842 | # CONFIG_HFS_FS is not set | ||
843 | # CONFIG_HFSPLUS_FS is not set | ||
844 | # CONFIG_BEFS_FS is not set | ||
845 | # CONFIG_BFS_FS is not set | ||
846 | # CONFIG_EFS_FS is not set | ||
847 | # CONFIG_CRAMFS is not set | ||
848 | # CONFIG_VXFS_FS is not set | ||
849 | # CONFIG_HPFS_FS is not set | ||
850 | # CONFIG_QNX4FS_FS is not set | ||
851 | # CONFIG_SYSV_FS is not set | ||
852 | # CONFIG_UFS_FS is not set | ||
853 | |||
854 | # | ||
855 | # Network File Systems | ||
856 | # | ||
857 | CONFIG_NFS_FS=y | ||
858 | # CONFIG_NFS_V3 is not set | ||
859 | # CONFIG_NFS_V4 is not set | ||
860 | # CONFIG_NFS_DIRECTIO is not set | ||
861 | CONFIG_NFSD=y | ||
862 | # CONFIG_NFSD_V3 is not set | ||
863 | # CONFIG_NFSD_TCP is not set | ||
864 | CONFIG_ROOT_NFS=y | ||
865 | CONFIG_LOCKD=y | ||
866 | CONFIG_EXPORTFS=y | ||
867 | CONFIG_NFS_COMMON=y | ||
868 | CONFIG_SUNRPC=y | ||
869 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
870 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
871 | # CONFIG_SMB_FS is not set | ||
872 | # CONFIG_CIFS is not set | ||
873 | # CONFIG_NCP_FS is not set | ||
874 | # CONFIG_CODA_FS is not set | ||
875 | # CONFIG_AFS_FS is not set | ||
876 | # CONFIG_9P_FS is not set | ||
877 | |||
878 | # | ||
879 | # Partition Types | ||
880 | # | ||
881 | # CONFIG_PARTITION_ADVANCED is not set | ||
882 | CONFIG_MSDOS_PARTITION=y | ||
883 | |||
884 | # | ||
885 | # Native Language Support | ||
886 | # | ||
887 | # CONFIG_NLS is not set | ||
888 | |||
889 | # | ||
890 | # Distributed Lock Manager | ||
891 | # | ||
892 | CONFIG_DLM=y | ||
893 | CONFIG_DLM_TCP=y | ||
894 | # CONFIG_DLM_SCTP is not set | ||
895 | # CONFIG_DLM_DEBUG is not set | ||
896 | |||
897 | # | ||
898 | # Profiling support | ||
899 | # | ||
900 | # CONFIG_PROFILING is not set | ||
901 | |||
902 | # | ||
903 | # Kernel hacking | ||
904 | # | ||
905 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
906 | # CONFIG_PRINTK_TIME is not set | ||
907 | CONFIG_ENABLE_MUST_CHECK=y | ||
908 | # CONFIG_MAGIC_SYSRQ is not set | ||
909 | # CONFIG_UNUSED_SYMBOLS is not set | ||
910 | # CONFIG_DEBUG_FS is not set | ||
911 | # CONFIG_HEADERS_CHECK is not set | ||
912 | # CONFIG_DEBUG_KERNEL is not set | ||
913 | CONFIG_LOG_BUF_SHIFT=14 | ||
914 | CONFIG_CROSSCOMPILE=y | ||
915 | CONFIG_CMDLINE="" | ||
916 | |||
917 | # | ||
918 | # Security options | ||
919 | # | ||
920 | CONFIG_KEYS=y | ||
921 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | ||
922 | # CONFIG_SECURITY is not set | ||
923 | |||
924 | # | ||
925 | # Cryptographic options | ||
926 | # | ||
927 | CONFIG_CRYPTO=y | ||
928 | CONFIG_CRYPTO_ALGAPI=y | ||
929 | CONFIG_CRYPTO_BLKCIPHER=y | ||
930 | CONFIG_CRYPTO_HASH=y | ||
931 | CONFIG_CRYPTO_MANAGER=y | ||
932 | CONFIG_CRYPTO_HMAC=y | ||
933 | CONFIG_CRYPTO_XCBC=y | ||
934 | CONFIG_CRYPTO_NULL=y | ||
935 | CONFIG_CRYPTO_MD4=y | ||
936 | CONFIG_CRYPTO_MD5=y | ||
937 | CONFIG_CRYPTO_SHA1=y | ||
938 | CONFIG_CRYPTO_SHA256=y | ||
939 | CONFIG_CRYPTO_SHA512=y | ||
940 | CONFIG_CRYPTO_WP512=y | ||
941 | CONFIG_CRYPTO_TGR192=y | ||
942 | CONFIG_CRYPTO_GF128MUL=y | ||
943 | CONFIG_CRYPTO_ECB=y | ||
944 | CONFIG_CRYPTO_CBC=y | ||
945 | CONFIG_CRYPTO_PCBC=y | ||
946 | CONFIG_CRYPTO_LRW=y | ||
947 | CONFIG_CRYPTO_DES=y | ||
948 | CONFIG_CRYPTO_FCRYPT=y | ||
949 | CONFIG_CRYPTO_BLOWFISH=y | ||
950 | CONFIG_CRYPTO_TWOFISH=y | ||
951 | CONFIG_CRYPTO_TWOFISH_COMMON=y | ||
952 | CONFIG_CRYPTO_SERPENT=y | ||
953 | CONFIG_CRYPTO_AES=y | ||
954 | CONFIG_CRYPTO_CAST5=y | ||
955 | CONFIG_CRYPTO_CAST6=y | ||
956 | CONFIG_CRYPTO_TEA=y | ||
957 | CONFIG_CRYPTO_ARC4=y | ||
958 | CONFIG_CRYPTO_KHAZAD=y | ||
959 | CONFIG_CRYPTO_ANUBIS=y | ||
960 | CONFIG_CRYPTO_DEFLATE=y | ||
961 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
962 | CONFIG_CRYPTO_CRC32C=y | ||
963 | CONFIG_CRYPTO_CAMELLIA=y | ||
964 | |||
965 | # | ||
966 | # Hardware crypto devices | ||
967 | # | ||
968 | |||
969 | # | ||
970 | # Library routines | ||
971 | # | ||
972 | CONFIG_BITREVERSE=y | ||
973 | # CONFIG_CRC_CCITT is not set | ||
974 | CONFIG_CRC16=y | ||
975 | CONFIG_CRC32=y | ||
976 | CONFIG_LIBCRC32C=y | ||
977 | CONFIG_ZLIB_INFLATE=y | ||
978 | CONFIG_ZLIB_DEFLATE=y | ||
979 | CONFIG_PLIST=y | ||
980 | CONFIG_HAS_IOMEM=y | ||
981 | CONFIG_HAS_IOPORT=y | ||
diff --git a/arch/mips/momentum/ocelot_g/Makefile b/arch/mips/momentum/ocelot_g/Makefile deleted file mode 100644 index c0a0030d949d..000000000000 --- a/arch/mips/momentum/ocelot_g/Makefile +++ /dev/null | |||
@@ -1,6 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for Momentum Computer's Ocelot-G board. | ||
3 | # | ||
4 | |||
5 | obj-y += irq.o gt-irq.o prom.o reset.o setup.o | ||
6 | obj-$(CONFIG_KGDB) += dbg_io.o | ||
diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c deleted file mode 100644 index 32d6fb4ee679..000000000000 --- a/arch/mips/momentum/ocelot_g/dbg_io.c +++ /dev/null | |||
@@ -1,121 +0,0 @@ | |||
1 | |||
2 | #include <asm/serial.h> /* For the serial port location and base baud */ | ||
3 | |||
4 | /* --- CONFIG --- */ | ||
5 | |||
6 | typedef unsigned char uint8; | ||
7 | typedef unsigned int uint32; | ||
8 | |||
9 | /* --- END OF CONFIG --- */ | ||
10 | |||
11 | #define UART16550_BAUD_2400 2400 | ||
12 | #define UART16550_BAUD_4800 4800 | ||
13 | #define UART16550_BAUD_9600 9600 | ||
14 | #define UART16550_BAUD_19200 19200 | ||
15 | #define UART16550_BAUD_38400 38400 | ||
16 | #define UART16550_BAUD_57600 57600 | ||
17 | #define UART16550_BAUD_115200 115200 | ||
18 | |||
19 | #define UART16550_PARITY_NONE 0 | ||
20 | #define UART16550_PARITY_ODD 0x08 | ||
21 | #define UART16550_PARITY_EVEN 0x18 | ||
22 | #define UART16550_PARITY_MARK 0x28 | ||
23 | #define UART16550_PARITY_SPACE 0x38 | ||
24 | |||
25 | #define UART16550_DATA_5BIT 0x0 | ||
26 | #define UART16550_DATA_6BIT 0x1 | ||
27 | #define UART16550_DATA_7BIT 0x2 | ||
28 | #define UART16550_DATA_8BIT 0x3 | ||
29 | |||
30 | #define UART16550_STOP_1BIT 0x0 | ||
31 | #define UART16550_STOP_2BIT 0x4 | ||
32 | |||
33 | /* ----------------------------------------------------- */ | ||
34 | |||
35 | /* === CONFIG === */ | ||
36 | |||
37 | /* [jsun] we use the second serial port for kdb */ | ||
38 | #define BASE OCELOT_SERIAL1_BASE | ||
39 | #define MAX_BAUD OCELOT_BASE_BAUD | ||
40 | |||
41 | /* === END OF CONFIG === */ | ||
42 | |||
43 | #define REG_OFFSET 4 | ||
44 | |||
45 | /* register offset */ | ||
46 | #define OFS_RCV_BUFFER 0 | ||
47 | #define OFS_TRANS_HOLD 0 | ||
48 | #define OFS_SEND_BUFFER 0 | ||
49 | #define OFS_INTR_ENABLE (1*REG_OFFSET) | ||
50 | #define OFS_INTR_ID (2*REG_OFFSET) | ||
51 | #define OFS_DATA_FORMAT (3*REG_OFFSET) | ||
52 | #define OFS_LINE_CONTROL (3*REG_OFFSET) | ||
53 | #define OFS_MODEM_CONTROL (4*REG_OFFSET) | ||
54 | #define OFS_RS232_OUTPUT (4*REG_OFFSET) | ||
55 | #define OFS_LINE_STATUS (5*REG_OFFSET) | ||
56 | #define OFS_MODEM_STATUS (6*REG_OFFSET) | ||
57 | #define OFS_RS232_INPUT (6*REG_OFFSET) | ||
58 | #define OFS_SCRATCH_PAD (7*REG_OFFSET) | ||
59 | |||
60 | #define OFS_DIVISOR_LSB (0*REG_OFFSET) | ||
61 | #define OFS_DIVISOR_MSB (1*REG_OFFSET) | ||
62 | |||
63 | |||
64 | /* memory-mapped read/write of the port */ | ||
65 | #define UART16550_READ(y) (*((volatile uint8*)(BASE + y))) | ||
66 | #define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z) | ||
67 | |||
68 | void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop) | ||
69 | { | ||
70 | /* disable interrupts */ | ||
71 | UART16550_WRITE(OFS_INTR_ENABLE, 0); | ||
72 | |||
73 | /* set up baud rate */ | ||
74 | { | ||
75 | uint32 divisor; | ||
76 | |||
77 | /* set DIAB bit */ | ||
78 | UART16550_WRITE(OFS_LINE_CONTROL, 0x80); | ||
79 | |||
80 | /* set divisor */ | ||
81 | divisor = MAX_BAUD / baud; | ||
82 | UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); | ||
83 | UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); | ||
84 | |||
85 | /* clear DIAB bit */ | ||
86 | UART16550_WRITE(OFS_LINE_CONTROL, 0x0); | ||
87 | } | ||
88 | |||
89 | /* set data format */ | ||
90 | UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); | ||
91 | } | ||
92 | |||
93 | static int remoteDebugInitialized = 0; | ||
94 | |||
95 | uint8 getDebugChar(void) | ||
96 | { | ||
97 | if (!remoteDebugInitialized) { | ||
98 | remoteDebugInitialized = 1; | ||
99 | debugInit(UART16550_BAUD_38400, | ||
100 | UART16550_DATA_8BIT, | ||
101 | UART16550_PARITY_NONE, UART16550_STOP_1BIT); | ||
102 | } | ||
103 | |||
104 | while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); | ||
105 | return UART16550_READ(OFS_RCV_BUFFER); | ||
106 | } | ||
107 | |||
108 | |||
109 | int putDebugChar(uint8 byte) | ||
110 | { | ||
111 | if (!remoteDebugInitialized) { | ||
112 | remoteDebugInitialized = 1; | ||
113 | debugInit(UART16550_BAUD_38400, | ||
114 | UART16550_DATA_8BIT, | ||
115 | UART16550_PARITY_NONE, UART16550_STOP_1BIT); | ||
116 | } | ||
117 | |||
118 | while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0); | ||
119 | UART16550_WRITE(OFS_SEND_BUFFER, byte); | ||
120 | return 1; | ||
121 | } | ||
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c deleted file mode 100644 index e5576bd50fa9..000000000000 --- a/arch/mips/momentum/ocelot_g/gt-irq.c +++ /dev/null | |||
@@ -1,212 +0,0 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Copyright 2002 Momentum Computer | ||
4 | * Author: mdharm@momenco.com | ||
5 | * | ||
6 | * arch/mips/momentum/ocelot_g/gt_irq.c | ||
7 | * Interrupt routines for gt64240. Currently it only handles timer irq. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | */ | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/sched.h> | ||
18 | #include <linux/kernel_stat.h> | ||
19 | #include <asm/gt64240.h> | ||
20 | #include <asm/io.h> | ||
21 | |||
22 | unsigned long bus_clock; | ||
23 | |||
24 | /* | ||
25 | * These are interrupt handlers for the GT on-chip interrupts. They | ||
26 | * all come in to the MIPS on a single interrupt line, and have to | ||
27 | * be handled and ack'ed differently than other MIPS interrupts. | ||
28 | */ | ||
29 | |||
30 | #if 0 | ||
31 | |||
32 | struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; | ||
33 | void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); | ||
34 | |||
35 | /* | ||
36 | * Hooks IRQ handler to the system. When the system is interrupted | ||
37 | * the interrupt service routine is called. | ||
38 | * | ||
39 | * Inputs : | ||
40 | * int_cause - The interrupt cause number. In EVB64120 two parameters | ||
41 | * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. | ||
42 | * bit_num - Indicates which bit number in the cause register | ||
43 | * isr_ptr - Pointer to the interrupt service routine | ||
44 | */ | ||
45 | void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr) | ||
46 | { | ||
47 | irq_handlers[int_cause][bit_num].routine = isr_ptr; | ||
48 | } | ||
49 | |||
50 | |||
51 | /* | ||
52 | * Enables the IRQ on Galileo Chip | ||
53 | * | ||
54 | * Inputs : | ||
55 | * int_cause - The interrupt cause number. In EVB64120 two parameters | ||
56 | * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. | ||
57 | * bit_num - Indicates which bit number in the cause register | ||
58 | * | ||
59 | * Outputs : | ||
60 | * 1 if successful, 0 if failure | ||
61 | */ | ||
62 | int enable_galileo_irq(int int_cause, int bit_num) | ||
63 | { | ||
64 | if (int_cause == INT_CAUSE_MAIN) | ||
65 | SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num)); | ||
66 | else if (int_cause == INT_CAUSE_HIGH) | ||
67 | SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, | ||
68 | (1 << bit_num)); | ||
69 | else | ||
70 | return 0; | ||
71 | |||
72 | return 1; | ||
73 | } | ||
74 | |||
75 | /* | ||
76 | * Disables the IRQ on Galileo Chip | ||
77 | * | ||
78 | * Inputs : | ||
79 | * int_cause - The interrupt cause number. In EVB64120 two parameters | ||
80 | * are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH. | ||
81 | * bit_num - Indicates which bit number in the cause register | ||
82 | * | ||
83 | * Outputs : | ||
84 | * 1 if successful, 0 if failure | ||
85 | */ | ||
86 | int disable_galileo_irq(int int_cause, int bit_num) | ||
87 | { | ||
88 | if (int_cause == INT_CAUSE_MAIN) | ||
89 | RESET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, | ||
90 | (1 << bit_num)); | ||
91 | else if (int_cause == INT_CAUSE_HIGH) | ||
92 | RESET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER, | ||
93 | (1 << bit_num)); | ||
94 | else | ||
95 | return 0; | ||
96 | return 1; | ||
97 | } | ||
98 | #endif /* 0 */ | ||
99 | |||
100 | /* | ||
101 | * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#. | ||
102 | * | ||
103 | * We route the timer interrupt to P0_INT# (IRQ 6), and that's all this | ||
104 | * routine can handle, for now. | ||
105 | * | ||
106 | * In the future, we'll route more interrupts to this pin, and that's why | ||
107 | * we keep this particular structure in the function. | ||
108 | */ | ||
109 | |||
110 | static irqreturn_t gt64240_p0int_irq(int irq, void *dev) | ||
111 | { | ||
112 | uint32_t irq_src, irq_src_mask; | ||
113 | int handled; | ||
114 | |||
115 | /* get the low interrupt cause register */ | ||
116 | irq_src = MV_READ(LOW_INTERRUPT_CAUSE_REGISTER); | ||
117 | |||
118 | /* get the mask register for this pin */ | ||
119 | irq_src_mask = MV_READ(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW); | ||
120 | |||
121 | /* mask off only the interrupts we're interested in */ | ||
122 | irq_src = irq_src & irq_src_mask; | ||
123 | |||
124 | handled = IRQ_NONE; | ||
125 | |||
126 | /* Check for timer interrupt */ | ||
127 | if (irq_src & 0x00000100) { | ||
128 | handled = IRQ_HANDLED; | ||
129 | irq_src &= ~0x00000100; | ||
130 | |||
131 | /* Clear any pending cause bits */ | ||
132 | MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); | ||
133 | |||
134 | /* handle the timer call */ | ||
135 | do_timer(1); | ||
136 | #ifndef CONFIG_SMP | ||
137 | update_process_times(user_mode(get_irq_regs())); | ||
138 | #endif | ||
139 | } | ||
140 | |||
141 | if (irq_src) { | ||
142 | printk(KERN_INFO | ||
143 | "UNKNOWN P0_INT# interrupt received, irq_src=0x%x\n", | ||
144 | irq_src); | ||
145 | } | ||
146 | |||
147 | return handled; | ||
148 | } | ||
149 | |||
150 | /* | ||
151 | * Initializes timer using galileo's built in timer. | ||
152 | */ | ||
153 | |||
154 | /* | ||
155 | * This will ignore the standard MIPS timer interrupt handler | ||
156 | * that is passed in as *irq (=irq0 in ../kernel/time.c). | ||
157 | * We will do our own timer interrupt handling. | ||
158 | */ | ||
159 | void gt64240_time_init(void) | ||
160 | { | ||
161 | static struct irqaction timer; | ||
162 | |||
163 | /* Stop the timer -- we'll use timer #0 */ | ||
164 | MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x0); | ||
165 | |||
166 | /* Load timer value for 100 Hz */ | ||
167 | MV_WRITE(TIMER_COUNTER0, bus_clock / 100); | ||
168 | |||
169 | /* | ||
170 | * Create the IRQ structure entry for the timer. Since we're too early | ||
171 | * in the boot process to use the "request_irq()" call, we'll hard-code | ||
172 | * the values to the correct interrupt line. | ||
173 | */ | ||
174 | timer.handler = >64240_p0int_irq; | ||
175 | timer.flags = IRQF_SHARED | IRQF_DISABLED; | ||
176 | timer.name = "timer"; | ||
177 | timer.dev_id = NULL; | ||
178 | timer.next = NULL; | ||
179 | timer.mask = CPU_MASK_NONE; | ||
180 | irq_desc[6].action = &timer; | ||
181 | |||
182 | enable_irq(6); | ||
183 | |||
184 | /* Clear any pending cause bits */ | ||
185 | MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_CAUSE, 0x0); | ||
186 | |||
187 | /* Enable the interrupt for timer 0 */ | ||
188 | MV_WRITE(TIMER_COUNTER_0_3_INTERRUPT_MASK, 0x1); | ||
189 | |||
190 | /* Enable the timer interrupt for GT-64240 pin P0_INT# */ | ||
191 | MV_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0x100); | ||
192 | |||
193 | /* Configure and start the timer */ | ||
194 | MV_WRITE(TIMER_COUNTER_0_3_CONTROL, 0x3); | ||
195 | } | ||
196 | |||
197 | void gt64240_irq_init(void) | ||
198 | { | ||
199 | #if 0 | ||
200 | int i, j; | ||
201 | |||
202 | /* Reset irq handlers pointers to NULL */ | ||
203 | for (i = 0; i < MAX_CAUSE_REGS; i++) { | ||
204 | for (j = 0; j < MAX_CAUSE_REG_WIDTH; j++) { | ||
205 | irq_handlers[i][j].next = NULL; | ||
206 | irq_handlers[i][j].sync = 0; | ||
207 | irq_handlers[i][j].routine = NULL; | ||
208 | irq_handlers[i][j].data = NULL; | ||
209 | } | ||
210 | } | ||
211 | #endif /* 0 */ | ||
212 | } | ||
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c deleted file mode 100644 index 273541fe7087..000000000000 --- a/arch/mips/momentum/ocelot_g/irq.c +++ /dev/null | |||
@@ -1,101 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2000 RidgeRun, Inc. | ||
3 | * Author: RidgeRun, Inc. | ||
4 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
5 | * | ||
6 | * Copyright 2001 MontaVista Software Inc. | ||
7 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | ||
8 | * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | * | ||
15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
25 | * | ||
26 | * You should have received a copy of the GNU General Public License along | ||
27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
29 | * | ||
30 | */ | ||
31 | #include <linux/errno.h> | ||
32 | #include <linux/init.h> | ||
33 | #include <linux/kernel_stat.h> | ||
34 | #include <linux/module.h> | ||
35 | #include <linux/signal.h> | ||
36 | #include <linux/sched.h> | ||
37 | #include <linux/types.h> | ||
38 | #include <linux/interrupt.h> | ||
39 | #include <linux/ioport.h> | ||
40 | #include <linux/timex.h> | ||
41 | #include <linux/slab.h> | ||
42 | #include <linux/random.h> | ||
43 | #include <linux/bitops.h> | ||
44 | #include <asm/bootinfo.h> | ||
45 | #include <asm/io.h> | ||
46 | #include <asm/irq.h> | ||
47 | #include <asm/irq_cpu.h> | ||
48 | #include <asm/mipsregs.h> | ||
49 | #include <asm/system.h> | ||
50 | |||
51 | asmlinkage void plat_irq_dispatch(void) | ||
52 | { | ||
53 | unsigned int pending = read_c0_cause() & read_c0_status(); | ||
54 | |||
55 | if (pending & STATUSF_IP2) | ||
56 | do_IRQ(2); | ||
57 | else if (pending & STATUSF_IP3) | ||
58 | do_IRQ(3); | ||
59 | else if (pending & STATUSF_IP4) | ||
60 | do_IRQ(4); | ||
61 | else if (pending & STATUSF_IP5) | ||
62 | do_IRQ(5); | ||
63 | else if (pending & STATUSF_IP6) | ||
64 | do_IRQ(6); | ||
65 | else if (pending & STATUSF_IP7) | ||
66 | do_IRQ(7); | ||
67 | else { | ||
68 | /* | ||
69 | * Now look at the extended interrupts | ||
70 | */ | ||
71 | pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; | ||
72 | |||
73 | if (pending & STATUSF_IP8) | ||
74 | do_IRQ(8); | ||
75 | else if (pending & STATUSF_IP9) | ||
76 | do_IRQ(9); | ||
77 | else if (pending & STATUSF_IP10) | ||
78 | do_IRQ(10); | ||
79 | else if (pending & STATUSF_IP11) | ||
80 | do_IRQ(11); | ||
81 | else | ||
82 | spurious_interrupt(); | ||
83 | } | ||
84 | } | ||
85 | |||
86 | extern void gt64240_irq_init(void); | ||
87 | |||
88 | void __init arch_init_irq(void) | ||
89 | { | ||
90 | /* | ||
91 | * Clear all of the interrupts while we change the able around a bit. | ||
92 | * int-handler is not on bootstrap | ||
93 | */ | ||
94 | clear_c0_status(ST0_IM); | ||
95 | local_irq_disable(); | ||
96 | |||
97 | mips_cpu_irq_init(); | ||
98 | rm7k_cpu_irq_init(); | ||
99 | |||
100 | gt64240_irq_init(); | ||
101 | } | ||
diff --git a/arch/mips/momentum/ocelot_g/ocelot_pld.h b/arch/mips/momentum/ocelot_g/ocelot_pld.h deleted file mode 100644 index 95e0534026d0..000000000000 --- a/arch/mips/momentum/ocelot_g/ocelot_pld.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* | ||
2 | * Ocelot Board Register Definitions | ||
3 | * | ||
4 | * (C) 2001 Red Hat, Inc. | ||
5 | * | ||
6 | * GPL'd | ||
7 | */ | ||
8 | #ifndef __MOMENCO_OCELOT_PLD_H__ | ||
9 | #define __MOMENCO_OCELOT_PLD_H__ | ||
10 | |||
11 | #define OCELOT_CS0_ADDR (0xfc000000) | ||
12 | |||
13 | #define OCELOT_REG_BOARDREV (0) | ||
14 | #define OCELOT_REG_PLD1_ID (1) | ||
15 | #define OCELOT_REG_PLD2_ID (2) | ||
16 | #define OCELOT_REG_RESET_STATUS (3) | ||
17 | #define OCELOT_REG_BOARD_STATUS (4) | ||
18 | #define OCELOT_REG_CPCI_ID (5) | ||
19 | #define OCELOT_REG_I2C_CTRL (8) | ||
20 | #define OCELOT_REG_EEPROM_MODE (9) | ||
21 | #define OCELOT_REG_INTMASK (10) | ||
22 | #define OCELOT_REG_INTSTATUS (11) | ||
23 | #define OCELOT_REG_INTSET (12) | ||
24 | #define OCELOT_REG_INTCLR (13) | ||
25 | |||
26 | #define __PLD_REG_TO_ADDR(reg) ((void *) OCELOT_CS0_ADDR + OCELOT_REG_##reg) | ||
27 | #define OCELOT_PLD_WRITE(x, reg) writeb(x, __PLD_REG_TO_ADDR(reg)) | ||
28 | #define OCELOT_PLD_READ(reg) readb(__PLD_REG_TO_ADDR(reg)) | ||
29 | |||
30 | #endif /* __MOMENCO_OCELOT_PLD_H__ */ | ||
diff --git a/arch/mips/momentum/ocelot_g/prom.c b/arch/mips/momentum/ocelot_g/prom.c deleted file mode 100644 index 836d0830720d..000000000000 --- a/arch/mips/momentum/ocelot_g/prom.c +++ /dev/null | |||
@@ -1,84 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2002 Momentum Computer Inc. | ||
3 | * Author: Matthew Dharm <mdharm@momenco.com> | ||
4 | * | ||
5 | * Based on Ocelot Linux port, which is | ||
6 | * Copyright 2001 MontaVista Software Inc. | ||
7 | * Author: jsun@mvista.com or jsun@junsun.net | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify it | ||
10 | * under the terms of the GNU General Public License as published by the | ||
11 | * Free Software Foundation; either version 2 of the License, or (at your | ||
12 | * option) any later version. | ||
13 | */ | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/mm.h> | ||
16 | #include <linux/sched.h> | ||
17 | #include <linux/bootmem.h> | ||
18 | |||
19 | #include <asm/addrspace.h> | ||
20 | #include <asm/bootinfo.h> | ||
21 | #include <asm/pmon.h> | ||
22 | #include <asm/gt64240.h> | ||
23 | |||
24 | #include "ocelot_pld.h" | ||
25 | |||
26 | struct callvectors* debug_vectors; | ||
27 | |||
28 | extern unsigned long marvell_base; | ||
29 | extern unsigned long bus_clock; | ||
30 | |||
31 | #ifdef CONFIG_GALILEO_GT64240_ETH | ||
32 | extern unsigned char prom_mac_addr_base[6]; | ||
33 | #endif | ||
34 | |||
35 | const char *get_system_type(void) | ||
36 | { | ||
37 | return "Momentum Ocelot"; | ||
38 | } | ||
39 | |||
40 | void __init prom_init(void) | ||
41 | { | ||
42 | int argc = fw_arg0; | ||
43 | char **arg = (char **) fw_arg1; | ||
44 | char **env = (char **) fw_arg2; | ||
45 | struct callvectors *cv = (struct callvectors *) fw_arg3; | ||
46 | int i; | ||
47 | |||
48 | /* save the PROM vectors for debugging use */ | ||
49 | debug_vectors = cv; | ||
50 | |||
51 | /* arg[0] is "g", the rest is boot parameters */ | ||
52 | arcs_cmdline[0] = '\0'; | ||
53 | for (i = 1; i < argc; i++) { | ||
54 | if (strlen(arcs_cmdline) + strlen(arg[i] + 1) | ||
55 | >= sizeof(arcs_cmdline)) | ||
56 | break; | ||
57 | strcat(arcs_cmdline, arg[i]); | ||
58 | strcat(arcs_cmdline, " "); | ||
59 | } | ||
60 | |||
61 | mips_machgroup = MACH_GROUP_MOMENCO; | ||
62 | mips_machtype = MACH_MOMENCO_OCELOT_G; | ||
63 | |||
64 | #ifdef CONFIG_GALILEO_GT64240_ETH | ||
65 | /* get the base MAC address for on-board ethernet ports */ | ||
66 | memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); | ||
67 | #endif | ||
68 | |||
69 | while (*env) { | ||
70 | if (strncmp("gtbase", *env, strlen("gtbase")) == 0) { | ||
71 | marvell_base = simple_strtol(*env + strlen("gtbase="), | ||
72 | NULL, 16); | ||
73 | } | ||
74 | if (strncmp("busclock", *env, strlen("busclock")) == 0) { | ||
75 | bus_clock = simple_strtol(*env + strlen("busclock="), | ||
76 | NULL, 10); | ||
77 | } | ||
78 | env++; | ||
79 | } | ||
80 | } | ||
81 | |||
82 | void __init prom_free_prom_memory(void) | ||
83 | { | ||
84 | } | ||
diff --git a/arch/mips/momentum/ocelot_g/reset.c b/arch/mips/momentum/ocelot_g/reset.c deleted file mode 100644 index 3fd499adf4cf..000000000000 --- a/arch/mips/momentum/ocelot_g/reset.c +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or modify it | ||
3 | * under the terms of the GNU General Public License as published by the | ||
4 | * Free Software Foundation; either version 2 of the License, or (at your | ||
5 | * option) any later version. | ||
6 | * | ||
7 | * Copyright (C) 1997, 2001 Ralf Baechle | ||
8 | * Copyright 2001 MontaVista Software Inc. | ||
9 | * Author: jsun@mvista.com or jsun@junsun.net | ||
10 | */ | ||
11 | #include <linux/sched.h> | ||
12 | #include <linux/mm.h> | ||
13 | #include <asm/io.h> | ||
14 | #include <asm/pgtable.h> | ||
15 | #include <asm/processor.h> | ||
16 | #include <asm/reboot.h> | ||
17 | #include <asm/system.h> | ||
18 | #include <linux/delay.h> | ||
19 | |||
20 | void momenco_ocelot_restart(char *command) | ||
21 | { | ||
22 | void *nvram = ioremap_nocache(0x2c807000, 0x1000); | ||
23 | |||
24 | if (!nvram) { | ||
25 | printk(KERN_NOTICE "ioremap of reset register failed\n"); | ||
26 | return; | ||
27 | } | ||
28 | writeb(0x84, nvram + 0xff7); /* Ask the NVRAM/RTC/watchdog chip to | ||
29 | assert reset in 1/16 second */ | ||
30 | mdelay(10+(1000/16)); | ||
31 | iounmap(nvram); | ||
32 | printk(KERN_NOTICE "Watchdog reset failed\n"); | ||
33 | } | ||
34 | |||
35 | void momenco_ocelot_halt(void) | ||
36 | { | ||
37 | printk(KERN_NOTICE "\n** You can safely turn off the power\n"); | ||
38 | while (1) | ||
39 | __asm__(".set\tmips3\n\t" | ||
40 | "wait\n\t" | ||
41 | ".set\tmips0"); | ||
42 | } | ||
43 | |||
44 | void momenco_ocelot_power_off(void) | ||
45 | { | ||
46 | momenco_ocelot_halt(); | ||
47 | } | ||
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c deleted file mode 100644 index 9db638a7982c..000000000000 --- a/arch/mips/momentum/ocelot_g/setup.c +++ /dev/null | |||
@@ -1,267 +0,0 @@ | |||
1 | /* | ||
2 | * BRIEF MODULE DESCRIPTION | ||
3 | * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines | ||
4 | * | ||
5 | * Copyright (C) 1996, 1997, 2001 Ralf Baechle | ||
6 | * Copyright (C) 2000 RidgeRun, Inc. | ||
7 | * Copyright (C) 2001 Red Hat, Inc. | ||
8 | * Copyright (C) 2002 Momentum Computer | ||
9 | * | ||
10 | * Author: Matthew Dharm, Momentum Computer | ||
11 | * mdharm@momenco.com | ||
12 | * | ||
13 | * Author: RidgeRun, Inc. | ||
14 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | ||
15 | * | ||
16 | * Copyright 2001 MontaVista Software Inc. | ||
17 | * Author: jsun@mvista.com or jsun@junsun.net | ||
18 | * | ||
19 | * This program is free software; you can redistribute it and/or modify it | ||
20 | * under the terms of the GNU General Public License as published by the | ||
21 | * Free Software Foundation; either version 2 of the License, or (at your | ||
22 | * option) any later version. | ||
23 | * | ||
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
29 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
30 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
31 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
33 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
34 | * | ||
35 | * You should have received a copy of the GNU General Public License along | ||
36 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
37 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
38 | * | ||
39 | */ | ||
40 | #include <linux/init.h> | ||
41 | #include <linux/kernel.h> | ||
42 | #include <linux/types.h> | ||
43 | #include <linux/mm.h> | ||
44 | #include <linux/swap.h> | ||
45 | #include <linux/ioport.h> | ||
46 | #include <linux/sched.h> | ||
47 | #include <linux/interrupt.h> | ||
48 | #include <linux/pci.h> | ||
49 | #include <linux/pm.h> | ||
50 | #include <linux/timex.h> | ||
51 | #include <linux/vmalloc.h> | ||
52 | |||
53 | #include <asm/time.h> | ||
54 | #include <asm/bootinfo.h> | ||
55 | #include <asm/page.h> | ||
56 | #include <asm/io.h> | ||
57 | #include <asm/gt64240.h> | ||
58 | #include <asm/irq.h> | ||
59 | #include <asm/pci.h> | ||
60 | #include <asm/pgtable.h> | ||
61 | #include <asm/processor.h> | ||
62 | #include <asm/reboot.h> | ||
63 | #include <linux/bootmem.h> | ||
64 | |||
65 | #include "ocelot_pld.h" | ||
66 | |||
67 | #ifdef CONFIG_GALILEO_GT64240_ETH | ||
68 | extern unsigned char prom_mac_addr_base[6]; | ||
69 | #endif | ||
70 | |||
71 | unsigned long marvell_base; | ||
72 | |||
73 | /* These functions are used for rebooting or halting the machine*/ | ||
74 | extern void momenco_ocelot_restart(char *command); | ||
75 | extern void momenco_ocelot_halt(void); | ||
76 | extern void momenco_ocelot_power_off(void); | ||
77 | |||
78 | extern void gt64240_time_init(void); | ||
79 | extern void momenco_ocelot_irq_setup(void); | ||
80 | |||
81 | static char reset_reason; | ||
82 | |||
83 | static unsigned long ENTRYLO(unsigned long paddr) | ||
84 | { | ||
85 | return ((paddr & PAGE_MASK) | | ||
86 | (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | | ||
87 | _CACHE_UNCACHED)) >> 6; | ||
88 | } | ||
89 | |||
90 | /* setup code for a handoff from a version 2 PMON 2000 PROM */ | ||
91 | void PMON_v2_setup(void) | ||
92 | { | ||
93 | /* A wired TLB entry for the GT64240 and the serial port. The | ||
94 | GT64240 is going to be hit on every IRQ anyway - there's | ||
95 | absolutely no point in letting it be a random TLB entry, as | ||
96 | it'll just cause needless churning of the TLB. And we use | ||
97 | the other half for the serial port, which is just a PITA | ||
98 | otherwise :) | ||
99 | |||
100 | Device Physical Virtual | ||
101 | GT64240 Internal Regs 0xf4000000 0xe0000000 | ||
102 | UARTs (CS2) 0xfd000000 0xe0001000 | ||
103 | */ | ||
104 | add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), | ||
105 | 0xf4000000, PM_64K); | ||
106 | add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), | ||
107 | 0xfd000000, PM_4K); | ||
108 | |||
109 | /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM | ||
110 | in the CS[012] region. We can't use ioremap() yet. The NVRAM | ||
111 | is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. | ||
112 | |||
113 | Ocelot PLD (CS0) 0xfc000000 0xe0020000 | ||
114 | NVRAM (CS1) 0xfc800000 0xe0030000 | ||
115 | */ | ||
116 | add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), | ||
117 | 0xfc000000, PM_64K); | ||
118 | add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), | ||
119 | 0xfc800000, PM_64K); | ||
120 | |||
121 | marvell_base = 0xf4000000; | ||
122 | } | ||
123 | |||
124 | extern int rm7k_tcache_enabled; | ||
125 | |||
126 | /* | ||
127 | * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() | ||
128 | */ | ||
129 | #define Page_Invalidate_T 0x16 | ||
130 | static void __init setup_l3cache(unsigned long size) | ||
131 | { | ||
132 | int register i; | ||
133 | |||
134 | printk("Enabling L3 cache..."); | ||
135 | |||
136 | /* Enable the L3 cache in the GT64120A's CPU Configuration register */ | ||
137 | MV_WRITE(0, MV_READ(0) | (1<<14)); | ||
138 | |||
139 | /* Enable the L3 cache in the CPU */ | ||
140 | set_c0_config(1<<12 /* CONF_TE */); | ||
141 | |||
142 | /* Clear the cache */ | ||
143 | write_c0_taglo(0); | ||
144 | write_c0_taghi(0); | ||
145 | |||
146 | for (i=0; i < size; i+= 4096) { | ||
147 | __asm__ __volatile__ ( | ||
148 | ".set noreorder\n\t" | ||
149 | ".set mips3\n\t" | ||
150 | "cache %1, (%0)\n\t" | ||
151 | ".set mips0\n\t" | ||
152 | ".set reorder" | ||
153 | : | ||
154 | : "r" (KSEG0ADDR(i)), | ||
155 | "i" (Page_Invalidate_T)); | ||
156 | } | ||
157 | |||
158 | /* Let the RM7000 MM code know that the tertiary cache is enabled */ | ||
159 | rm7k_tcache_enabled = 1; | ||
160 | |||
161 | printk("Done\n"); | ||
162 | } | ||
163 | |||
164 | void __init plat_timer_setup(struct irqaction *irq) | ||
165 | { | ||
166 | } | ||
167 | |||
168 | void __init plat_mem_setup(void) | ||
169 | { | ||
170 | void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); | ||
171 | unsigned int tmpword; | ||
172 | |||
173 | board_time_init = gt64240_time_init; | ||
174 | |||
175 | _machine_restart = momenco_ocelot_restart; | ||
176 | _machine_halt = momenco_ocelot_halt; | ||
177 | pm_power_off = momenco_ocelot_power_off; | ||
178 | |||
179 | /* | ||
180 | * initrd_start = (unsigned long)ocelot_initrd_start; | ||
181 | * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; | ||
182 | * initrd_below_start_ok = 1; | ||
183 | */ | ||
184 | |||
185 | /* do handoff reconfiguration */ | ||
186 | PMON_v2_setup(); | ||
187 | |||
188 | #ifdef CONFIG_GALILEO_GT64240_ETH | ||
189 | /* get the mac addr */ | ||
190 | memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); | ||
191 | #endif | ||
192 | |||
193 | /* Turn off the Bit-Error LED */ | ||
194 | OCELOT_PLD_WRITE(0x80, INTCLR); | ||
195 | |||
196 | tmpword = OCELOT_PLD_READ(BOARDREV); | ||
197 | if (tmpword < 26) | ||
198 | printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword); | ||
199 | else | ||
200 | printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword); | ||
201 | |||
202 | tmpword = OCELOT_PLD_READ(PLD1_ID); | ||
203 | printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); | ||
204 | tmpword = OCELOT_PLD_READ(PLD2_ID); | ||
205 | printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); | ||
206 | tmpword = OCELOT_PLD_READ(RESET_STATUS); | ||
207 | printk("Reset reason: 0x%x\n", tmpword); | ||
208 | reset_reason = tmpword; | ||
209 | OCELOT_PLD_WRITE(0xff, RESET_STATUS); | ||
210 | |||
211 | tmpword = OCELOT_PLD_READ(BOARD_STATUS); | ||
212 | printk("Board Status register: 0x%02x\n", tmpword); | ||
213 | printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); | ||
214 | printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); | ||
215 | printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); | ||
216 | printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); | ||
217 | printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); | ||
218 | |||
219 | if (tmpword&12) | ||
220 | l3func((1<<(((tmpword&12) >> 2)+20))); | ||
221 | |||
222 | switch(tmpword &3) { | ||
223 | case 3: | ||
224 | /* 512MiB -- two banks of 256MiB */ | ||
225 | add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM); | ||
226 | /* | ||
227 | add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); | ||
228 | */ | ||
229 | break; | ||
230 | case 2: | ||
231 | /* 256MiB -- two banks of 128MiB */ | ||
232 | add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM); | ||
233 | add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); | ||
234 | break; | ||
235 | case 1: | ||
236 | /* 128MiB -- 64MiB per bank */ | ||
237 | add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); | ||
238 | add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); | ||
239 | break; | ||
240 | case 0: | ||
241 | /* 64MiB */ | ||
242 | add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); | ||
243 | break; | ||
244 | } | ||
245 | |||
246 | /* FIXME: Fix up the DiskOnChip mapping */ | ||
247 | MV_WRITE(0x468, 0xfef73); | ||
248 | } | ||
249 | |||
250 | /* This needs to be one of the first initcalls, because no I/O port access | ||
251 | can work before this */ | ||
252 | |||
253 | static int io_base_ioremap(void) | ||
254 | { | ||
255 | /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ | ||
256 | unsigned long io_remap_range; | ||
257 | |||
258 | io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000); | ||
259 | if (!io_remap_range) | ||
260 | panic("Could not ioremap I/O port range"); | ||
261 | |||
262 | set_io_port_base(io_remap_range - 0xc0000000); | ||
263 | |||
264 | return 0; | ||
265 | } | ||
266 | |||
267 | module_init(io_base_ioremap); | ||
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index df487c063b1d..30a1c79c6f5f 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile | |||
@@ -34,7 +34,6 @@ obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o | |||
34 | obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o | 34 | obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o |
35 | obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o | 35 | obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o |
36 | obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o | 36 | obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o |
37 | obj-$(CONFIG_MOMENCO_OCELOT_G) += fixup-ocelot-g.o pci-ocelot-g.o | ||
38 | obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ | 37 | obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ |
39 | pci-yosemite.o | 38 | pci-yosemite.o |
40 | obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o | 39 | obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o |
diff --git a/arch/mips/pci/fixup-ocelot-g.c b/arch/mips/pci/fixup-ocelot-g.c deleted file mode 100644 index d7a652e326c5..000000000000 --- a/arch/mips/pci/fixup-ocelot-g.c +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or modify it | ||
3 | * under the terms of the GNU General Public License as published by the | ||
4 | * Free Software Foundation; either version 2 of the License, or (at your | ||
5 | * option) any later version. | ||
6 | * | ||
7 | * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) | ||
8 | */ | ||
9 | #include <linux/types.h> | ||
10 | #include <linux/pci.h> | ||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/init.h> | ||
13 | |||
14 | int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
15 | { | ||
16 | int bus = dev->bus->number; | ||
17 | |||
18 | if (bus == 0 && slot == 1) /* Intel 82543 Gigabit MAC */ | ||
19 | return 2; /* irq_nr is 2 for INT0 */ | ||
20 | |||
21 | if (bus == 0 && slot == 2) /* Intel 82543 Gigabit MAC */ | ||
22 | return 3; /* irq_nr is 3 for INT1 */ | ||
23 | |||
24 | if (bus == 1 && slot == 3) /* Intel 21555 bridge */ | ||
25 | return 5; /* irq_nr is 8 for INT6 */ | ||
26 | |||
27 | if (bus == 1 && slot == 4) /* PMC Slot */ | ||
28 | return 9; /* irq_nr is 9 for INT7 */ | ||
29 | |||
30 | return -1; | ||
31 | } | ||
32 | |||
33 | /* Do platform specific device initialization at pci_enable_device() time */ | ||
34 | int pcibios_plat_dev_init(struct pci_dev *dev) | ||
35 | { | ||
36 | return 0; | ||
37 | } | ||
diff --git a/arch/mips/pci/pci-ocelot-g.c b/arch/mips/pci/pci-ocelot-g.c deleted file mode 100644 index 1e3430154fa0..000000000000 --- a/arch/mips/pci/pci-ocelot-g.c +++ /dev/null | |||
@@ -1,97 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | ||
7 | * | ||
8 | * This doesn't really fly - but I don't have a GT64240 system for testing. | ||
9 | */ | ||
10 | #include <linux/init.h> | ||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/types.h> | ||
13 | #include <linux/pci.h> | ||
14 | #include <asm/gt64240.h> | ||
15 | |||
16 | /* | ||
17 | * We assume these address ranges have been programmed into the GT-64240 by | ||
18 | * the firmware. PMON in case of the Ocelot G does that. Note the size of | ||
19 | * the I/O range is completly stupid; I/O mappings are limited to at most | ||
20 | * 256 bytes by the PCI spec and deprecated; and just to make things worse | ||
21 | * apparently many devices don't decode more than 64k of I/O space. | ||
22 | */ | ||
23 | |||
24 | #define gt_io_size 0x20000000UL | ||
25 | #define gt_io_base 0xe0000000UL | ||
26 | |||
27 | static struct resource gt_pci_mem0_resource = { | ||
28 | .name = "MV64240 PCI0 MEM", | ||
29 | .start = 0xc0000000UL, | ||
30 | .end = 0xcfffffffUL, | ||
31 | .flags = IORESOURCE_MEM | ||
32 | }; | ||
33 | |||
34 | static struct resource gt_pci_io_mem0_resource = { | ||
35 | .name = "MV64240 PCI0 IO MEM", | ||
36 | .start = 0xe0000000UL, | ||
37 | .end = 0xefffffffUL, | ||
38 | .flags = IORESOURCE_IO | ||
39 | }; | ||
40 | |||
41 | static struct mv_pci_controller gt_bus0_controller = { | ||
42 | .pcic = { | ||
43 | .pci_ops = &mv_pci_ops, | ||
44 | .mem_resource = >_pci_mem0_resource, | ||
45 | .mem_offset = 0xc0000000UL, | ||
46 | .io_resource = >_pci_io_mem0_resource, | ||
47 | .io_offset = 0x00000000UL | ||
48 | }, | ||
49 | .config_addr = PCI_0CONFIGURATION_ADDRESS, | ||
50 | .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, | ||
51 | }; | ||
52 | |||
53 | static struct resource gt_pci_mem1_resource = { | ||
54 | .name = "MV64240 PCI1 MEM", | ||
55 | .start = 0xd0000000UL, | ||
56 | .end = 0xdfffffffUL, | ||
57 | .flags = IORESOURCE_MEM | ||
58 | }; | ||
59 | |||
60 | static struct resource gt_pci_io_mem1_resource = { | ||
61 | .name = "MV64240 PCI1 IO MEM", | ||
62 | .start = 0xf0000000UL, | ||
63 | .end = 0xffffffffUL, | ||
64 | .flags = IORESOURCE_IO | ||
65 | }; | ||
66 | |||
67 | static struct mv_pci_controller gt_bus1_controller = { | ||
68 | .pcic = { | ||
69 | .pci_ops = &mv_pci_ops, | ||
70 | .mem_resource = >_pci_mem1_resource, | ||
71 | .mem_offset = 0xd0000000UL, | ||
72 | .io_resource = >_pci_io_mem1_resource, | ||
73 | .io_offset = 0x10000000UL | ||
74 | }, | ||
75 | .config_addr = PCI_1CONFIGURATION_ADDRESS, | ||
76 | .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, | ||
77 | }; | ||
78 | |||
79 | static __init int __init ocelot_g_pci_init(void) | ||
80 | { | ||
81 | unsigned long io_v_base; | ||
82 | |||
83 | if (gt_io_size) { | ||
84 | io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size); | ||
85 | if (!io_v_base) | ||
86 | panic("Could not ioremap I/O port range"); | ||
87 | |||
88 | set_io_port_base(io_v_base); | ||
89 | } | ||
90 | |||
91 | register_pci_controller(>_bus0_controller.pcic); | ||
92 | register_pci_controller(>_bus1_controller.pcic); | ||
93 | |||
94 | return 0; | ||
95 | } | ||
96 | |||
97 | arch_initcall(ocelot_g_pci_init); | ||
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index dbf834f4dac4..198ecc08ab40 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h | |||
@@ -119,7 +119,7 @@ | |||
119 | */ | 119 | */ |
120 | #define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ | 120 | #define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ |
121 | #define MACH_MOMENCO_OCELOT 0 | 121 | #define MACH_MOMENCO_OCELOT 0 |
122 | #define MACH_MOMENCO_OCELOT_G 1 | 122 | #define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */ |
123 | #define MACH_MOMENCO_OCELOT_C 2 | 123 | #define MACH_MOMENCO_OCELOT_C 2 |
124 | #define MACH_MOMENCO_JAGUAR_ATX 3 | 124 | #define MACH_MOMENCO_JAGUAR_ATX 3 |
125 | #define MACH_MOMENCO_OCELOT_3 4 | 125 | #define MACH_MOMENCO_OCELOT_3 4 |
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index d7a65135d837..5e0da6e2d698 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h | |||
@@ -134,27 +134,6 @@ | |||
134 | #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS | 134 | #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS |
135 | #endif | 135 | #endif |
136 | 136 | ||
137 | #ifdef CONFIG_MOMENCO_OCELOT_G | ||
138 | /* Ordinary NS16552 duart with a 20MHz crystal. */ | ||
139 | #define OCELOT_G_BASE_BAUD ( 20000000 / 16 ) | ||
140 | |||
141 | #define OCELOT_G_SERIAL1_IRQ 4 | ||
142 | #if 0 | ||
143 | #define OCELOT_G_SERIAL1_BASE 0xe0001020 | ||
144 | #else | ||
145 | #define OCELOT_G_SERIAL1_BASE 0xfd000020 | ||
146 | #endif | ||
147 | |||
148 | #define _OCELOT_G_SERIAL_INIT(int, base) \ | ||
149 | { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\ | ||
150 | .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \ | ||
151 | .io_type = SERIAL_IO_MEM } | ||
152 | #define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ | ||
153 | _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE) | ||
154 | #else | ||
155 | #define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS | ||
156 | #endif | ||
157 | |||
158 | #ifdef CONFIG_MOMENCO_OCELOT_C | 137 | #ifdef CONFIG_MOMENCO_OCELOT_C |
159 | /* Ordinary NS16552 duart with a 20MHz crystal. */ | 138 | /* Ordinary NS16552 duart with a 20MHz crystal. */ |
160 | #define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) | 139 | #define OCELOT_C_BASE_BAUD ( 20000000 / 16 ) |
@@ -210,7 +189,6 @@ | |||
210 | IP32_SERIAL_PORT_DEFNS \ | 189 | IP32_SERIAL_PORT_DEFNS \ |
211 | JAZZ_SERIAL_PORT_DEFNS \ | 190 | JAZZ_SERIAL_PORT_DEFNS \ |
212 | STD_SERIAL_PORT_DEFNS \ | 191 | STD_SERIAL_PORT_DEFNS \ |
213 | MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ | ||
214 | MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ | 192 | MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ |
215 | MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ | 193 | MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ |
216 | MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS | 194 | MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS |