diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-04-22 13:20:04 -0400 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2015-04-24 14:57:06 -0400 |
| commit | 1dcc73d7bb0429994c54d33b40c5fb82b741a791 (patch) | |
| tree | 4e8f84f2940172d1ab0c1329036a1f02ceda7008 | |
| parent | 10a50f1ab5f06c9a3ee5ece3ec52e607ed53c79f (diff) | |
irqchip: gic: Drop support for gic_arch_extn
Now that the users of gic_arch_extn have been fixed, drop the
"feature" for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| -rw-r--r-- | drivers/irqchip/irq-gic.c | 71 | ||||
| -rw-r--r-- | include/linux/irqchip/arm-gic.h | 2 |
2 files changed, 1 insertions, 72 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index a6ce3476834e..dd989148e689 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c | |||
| @@ -80,19 +80,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock); | |||
| 80 | #define NR_GIC_CPU_IF 8 | 80 | #define NR_GIC_CPU_IF 8 |
| 81 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | 81 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; |
| 82 | 82 | ||
| 83 | /* | ||
| 84 | * Supported arch specific GIC irq extension. | ||
| 85 | * Default make them NULL. | ||
| 86 | */ | ||
| 87 | struct irq_chip gic_arch_extn = { | ||
| 88 | .irq_eoi = NULL, | ||
| 89 | .irq_mask = NULL, | ||
| 90 | .irq_unmask = NULL, | ||
| 91 | .irq_retrigger = NULL, | ||
| 92 | .irq_set_type = NULL, | ||
| 93 | .irq_set_wake = NULL, | ||
| 94 | }; | ||
| 95 | |||
| 96 | #ifndef MAX_GIC_NR | 83 | #ifndef MAX_GIC_NR |
| 97 | #define MAX_GIC_NR 1 | 84 | #define MAX_GIC_NR 1 |
| 98 | #endif | 85 | #endif |
| @@ -165,34 +152,16 @@ static int gic_peek_irq(struct irq_data *d, u32 offset) | |||
| 165 | 152 | ||
| 166 | static void gic_mask_irq(struct irq_data *d) | 153 | static void gic_mask_irq(struct irq_data *d) |
| 167 | { | 154 | { |
| 168 | unsigned long flags; | ||
| 169 | |||
| 170 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | ||
| 171 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); | 155 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
| 172 | if (gic_arch_extn.irq_mask) | ||
| 173 | gic_arch_extn.irq_mask(d); | ||
| 174 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | ||
| 175 | } | 156 | } |
| 176 | 157 | ||
| 177 | static void gic_unmask_irq(struct irq_data *d) | 158 | static void gic_unmask_irq(struct irq_data *d) |
| 178 | { | 159 | { |
| 179 | unsigned long flags; | ||
| 180 | |||
| 181 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | ||
| 182 | if (gic_arch_extn.irq_unmask) | ||
| 183 | gic_arch_extn.irq_unmask(d); | ||
| 184 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); | 160 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
| 185 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | ||
| 186 | } | 161 | } |
| 187 | 162 | ||
| 188 | static void gic_eoi_irq(struct irq_data *d) | 163 | static void gic_eoi_irq(struct irq_data *d) |
| 189 | { | 164 | { |
| 190 | if (gic_arch_extn.irq_eoi) { | ||
| 191 | raw_spin_lock(&irq_controller_lock); | ||
| 192 | gic_arch_extn.irq_eoi(d); | ||
| 193 | raw_spin_unlock(&irq_controller_lock); | ||
| 194 | } | ||
| 195 | |||
| 196 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); | 165 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
| 197 | } | 166 | } |
| 198 | 167 | ||
| @@ -249,8 +218,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
| 249 | { | 218 | { |
| 250 | void __iomem *base = gic_dist_base(d); | 219 | void __iomem *base = gic_dist_base(d); |
| 251 | unsigned int gicirq = gic_irq(d); | 220 | unsigned int gicirq = gic_irq(d); |
| 252 | unsigned long flags; | ||
| 253 | int ret; | ||
| 254 | 221 | ||
| 255 | /* Interrupt configuration for SGIs can't be changed */ | 222 | /* Interrupt configuration for SGIs can't be changed */ |
| 256 | if (gicirq < 16) | 223 | if (gicirq < 16) |
| @@ -261,25 +228,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) | |||
| 261 | type != IRQ_TYPE_EDGE_RISING) | 228 | type != IRQ_TYPE_EDGE_RISING) |
| 262 | return -EINVAL; | 229 | return -EINVAL; |
| 263 | 230 | ||
| 264 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | 231 | return gic_configure_irq(gicirq, type, base, NULL); |
| 265 | |||
| 266 | if (gic_arch_extn.irq_set_type) | ||
| 267 | gic_arch_extn.irq_set_type(d, type); | ||
| 268 | |||
| 269 | ret = gic_configure_irq(gicirq, type, base, NULL); | ||
| 270 | |||
| 271 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | ||
| 272 | |||
| 273 | return ret; | ||
| 274 | } | ||
| 275 | |||
| 276 | static int gic_retrigger(struct irq_data *d) | ||
| 277 | { | ||
| 278 | if (gic_arch_extn.irq_retrigger) | ||
| 279 | return gic_arch_extn.irq_retrigger(d); | ||
| 280 | |||
| 281 | /* the genirq layer expects 0 if we can't retrigger in hardware */ | ||
| 282 | return 0; | ||
| 283 | } | 232 | } |
| 284 | 233 | ||
| 285 | #ifdef CONFIG_SMP | 234 | #ifdef CONFIG_SMP |
| @@ -310,21 +259,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |||
| 310 | } | 259 | } |
| 311 | #endif | 260 | #endif |
| 312 | 261 | ||
| 313 | #ifdef CONFIG_PM | ||
| 314 | static int gic_set_wake(struct irq_data *d, unsigned int on) | ||
| 315 | { | ||
| 316 | int ret = -ENXIO; | ||
| 317 | |||
| 318 | if (gic_arch_extn.irq_set_wake) | ||
| 319 | ret = gic_arch_extn.irq_set_wake(d, on); | ||
| 320 | |||
| 321 | return ret; | ||
| 322 | } | ||
| 323 | |||
| 324 | #else | ||
| 325 | #define gic_set_wake NULL | ||
| 326 | #endif | ||
| 327 | |||
| 328 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | 262 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
| 329 | { | 263 | { |
| 330 | u32 irqstat, irqnr; | 264 | u32 irqstat, irqnr; |
| @@ -383,11 +317,9 @@ static struct irq_chip gic_chip = { | |||
| 383 | .irq_unmask = gic_unmask_irq, | 317 | .irq_unmask = gic_unmask_irq, |
| 384 | .irq_eoi = gic_eoi_irq, | 318 | .irq_eoi = gic_eoi_irq, |
| 385 | .irq_set_type = gic_set_type, | 319 | .irq_set_type = gic_set_type, |
| 386 | .irq_retrigger = gic_retrigger, | ||
| 387 | #ifdef CONFIG_SMP | 320 | #ifdef CONFIG_SMP |
| 388 | .irq_set_affinity = gic_set_affinity, | 321 | .irq_set_affinity = gic_set_affinity, |
| 389 | #endif | 322 | #endif |
| 390 | .irq_set_wake = gic_set_wake, | ||
| 391 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | 323 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 392 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | 324 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
| 393 | }; | 325 | }; |
| @@ -1053,7 +985,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start, | |||
| 1053 | set_handle_irq(gic_handle_irq); | 985 | set_handle_irq(gic_handle_irq); |
| 1054 | } | 986 | } |
| 1055 | 987 | ||
| 1056 | gic_chip.flags |= gic_arch_extn.flags; | ||
| 1057 | gic_dist_init(gic); | 988 | gic_dist_init(gic); |
| 1058 | gic_cpu_init(gic); | 989 | gic_cpu_init(gic); |
| 1059 | gic_pm_init(gic); | 990 | gic_pm_init(gic); |
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 36ec4ae74634..9de976b4f9a7 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h | |||
| @@ -95,8 +95,6 @@ | |||
| 95 | 95 | ||
| 96 | struct device_node; | 96 | struct device_node; |
| 97 | 97 | ||
| 98 | extern struct irq_chip gic_arch_extn; | ||
| 99 | |||
| 100 | void gic_set_irqchip_flags(unsigned long flags); | 98 | void gic_set_irqchip_flags(unsigned long flags); |
| 101 | void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, | 99 | void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, |
| 102 | u32 offset, struct device_node *); | 100 | u32 offset, struct device_node *); |
