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authorDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
committerDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
commit1d2add28edd268a8290801ccf46b37f6d5239cdb (patch)
tree534e967b692f816434c00de0893e1089d425ae92
parentbb1dc08c94ead1b98e750caf535422f79363c1a2 (diff)
parent5e501ed7253b369a8a9ec553c35238a3d6808f28 (diff)
Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm changes to use media bus formats and LDB drm_panel support - Add media bus formats needed by imx-drm - Switch to use media bus formats to describe the pixel format on the internal parallel bus between display interface and encoders - Some preparations for TV Output via TVEv2 on i.MX5 - Add drm_panel support to the i.MX LVDS driver, allow to determine the bus pixel format from the panel descriptor. * tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux: drm/imx: imx-ldb: allow to determine bus format from the connected panel drm/imx: imx-ldb: reset display clock input when disabling LVDS drm/imx: imx-ldb: add drm_panel support drm/imx: consolidate bus format variable names drm/imx: switch to use media bus formats Add RGB666_1X24_CPADHI media bus format Add YUV8_1X24 media bus format Add BGR888_1X24 and GBR888_1X24 media bus formats Add LVDS RGB media bus formats Add RGB444_1X12 and RGB565_1X16 media bus formats drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 drm/imx: Add support for interlaced scanout
Diffstat
-rw-r--r--Documentation/DocBook/media/v4l/subdev-formats.xml426
-rw-r--r--Documentation/devicetree/bindings/drm/imx/ldb.txt62
-rw-r--r--drivers/gpu/drm/imx/Kconfig1
-rw-r--r--drivers/gpu/drm/imx/dw_hdmi-imx.c2
-rw-r--r--drivers/gpu/drm/imx/imx-drm-core.c14
-rw-r--r--drivers/gpu/drm/imx/imx-drm.h10
-rw-r--r--drivers/gpu/drm/imx/imx-ldb.c196
-rw-r--r--drivers/gpu/drm/imx/imx-tve.c6
-rw-r--r--drivers/gpu/drm/imx/ipuv3-crtc.c24
-rw-r--r--drivers/gpu/drm/imx/ipuv3-plane.c7
-rw-r--r--drivers/gpu/drm/imx/ipuv3-plane.h2
-rw-r--r--drivers/gpu/drm/imx/parallel-display.c13
-rw-r--r--drivers/gpu/ipu-v3/ipu-dc.c18
-rw-r--r--include/uapi/linux/media-bus-format.h13
-rw-r--r--include/video/imx-ipu-v3.h2
15 files changed, 668 insertions, 128 deletions
diff --git a/Documentation/DocBook/media/v4l/subdev-formats.xml b/Documentation/DocBook/media/v4l/subdev-formats.xml
index c5ea868e3909..18b71aff48c9 100644
--- a/Documentation/DocBook/media/v4l/subdev-formats.xml
+++ b/Documentation/DocBook/media/v4l/subdev-formats.xml
@@ -91,7 +91,9 @@ see <xref linkend="colorspaces" />.</entry>
91 <listitem><para>For formats where the total number of bits per pixel is smaller 91 <listitem><para>For formats where the total number of bits per pixel is smaller
92 than the number of bus samples per pixel times the bus width, a padding 92 than the number of bus samples per pixel times the bus width, a padding
93 value stating if the bytes are padded in their most high order bits 93 value stating if the bytes are padded in their most high order bits
94 (PADHI) or low order bits (PADLO).</para></listitem> 94 (PADHI) or low order bits (PADLO). A "C" prefix is used for component-wise
95 padding in the most high order bits (CPADHI) or low order bits (CPADLO)
96 of each separate component.</para></listitem>
95 <listitem><para>For formats where the number of bus samples per pixel is larger 97 <listitem><para>For formats where the number of bus samples per pixel is larger
96 than 1, an endianness value stating if the pixel is transferred MSB first 98 than 1, an endianness value stating if the pixel is transferred MSB first
97 (BE) or LSB first (LE).</para></listitem> 99 (BE) or LSB first (LE).</para></listitem>
@@ -192,6 +194,24 @@ see <xref linkend="colorspaces" />.</entry>
192 </row> 194 </row>
193 </thead> 195 </thead>
194 <tbody valign="top"> 196 <tbody valign="top">
197 <row id="MEDIA-BUS-FMT-RGB444-1X12">
198 <entry>MEDIA_BUS_FMT_RGB444_1X12</entry>
199 <entry>0x100e</entry>
200 <entry></entry>
201 &dash-ent-20;
202 <entry>r<subscript>3</subscript></entry>
203 <entry>r<subscript>2</subscript></entry>
204 <entry>r<subscript>1</subscript></entry>
205 <entry>r<subscript>0</subscript></entry>
206 <entry>g<subscript>3</subscript></entry>
207 <entry>g<subscript>2</subscript></entry>
208 <entry>g<subscript>1</subscript></entry>
209 <entry>g<subscript>0</subscript></entry>
210 <entry>b<subscript>3</subscript></entry>
211 <entry>b<subscript>2</subscript></entry>
212 <entry>b<subscript>1</subscript></entry>
213 <entry>b<subscript>0</subscript></entry>
214 </row>
195 <row id="MEDIA-BUS-FMT-RGB444-2X8-PADHI-BE"> 215 <row id="MEDIA-BUS-FMT-RGB444-2X8-PADHI-BE">
196 <entry>MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE</entry> 216 <entry>MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE</entry>
197 <entry>0x1001</entry> 217 <entry>0x1001</entry>
@@ -304,6 +324,28 @@ see <xref linkend="colorspaces" />.</entry>
304 <entry>g<subscript>4</subscript></entry> 324 <entry>g<subscript>4</subscript></entry>
305 <entry>g<subscript>3</subscript></entry> 325 <entry>g<subscript>3</subscript></entry>
306 </row> 326 </row>
327 <row id="MEDIA-BUS-FMT-RGB565-1X16">
328 <entry>MEDIA_BUS_FMT_RGB565_1X16</entry>
329 <entry>0x100f</entry>
330 <entry></entry>
331 &dash-ent-16;
332 <entry>r<subscript>4</subscript></entry>
333 <entry>r<subscript>3</subscript></entry>
334 <entry>r<subscript>2</subscript></entry>
335 <entry>r<subscript>1</subscript></entry>
336 <entry>r<subscript>0</subscript></entry>
337 <entry>g<subscript>5</subscript></entry>
338 <entry>g<subscript>4</subscript></entry>
339 <entry>g<subscript>3</subscript></entry>
340 <entry>g<subscript>2</subscript></entry>
341 <entry>g<subscript>1</subscript></entry>
342 <entry>g<subscript>0</subscript></entry>
343 <entry>b<subscript>4</subscript></entry>
344 <entry>b<subscript>3</subscript></entry>
345 <entry>b<subscript>2</subscript></entry>
346 <entry>b<subscript>1</subscript></entry>
347 <entry>b<subscript>0</subscript></entry>
348 </row>
307 <row id="MEDIA-BUS-FMT-BGR565-2X8-BE"> 349 <row id="MEDIA-BUS-FMT-BGR565-2X8-BE">
308 <entry>MEDIA_BUS_FMT_BGR565_2X8_BE</entry> 350 <entry>MEDIA_BUS_FMT_BGR565_2X8_BE</entry>
309 <entry>0x1005</entry> 351 <entry>0x1005</entry>
@@ -440,6 +482,96 @@ see <xref linkend="colorspaces" />.</entry>
440 <entry>b<subscript>1</subscript></entry> 482 <entry>b<subscript>1</subscript></entry>
441 <entry>b<subscript>0</subscript></entry> 483 <entry>b<subscript>0</subscript></entry>
442 </row> 484 </row>
485 <row id="MEDIA-BUS-FMT-RGB666-1X24_CPADHI">
486 <entry>MEDIA_BUS_FMT_RGB666_1X24_CPADHI</entry>
487 <entry>0x1015</entry>
488 <entry></entry>
489 &dash-ent-8;
490 <entry>0</entry>
491 <entry>0</entry>
492 <entry>r<subscript>5</subscript></entry>
493 <entry>r<subscript>4</subscript></entry>
494 <entry>r<subscript>3</subscript></entry>
495 <entry>r<subscript>2</subscript></entry>
496 <entry>r<subscript>1</subscript></entry>
497 <entry>r<subscript>0</subscript></entry>
498 <entry>0</entry>
499 <entry>0</entry>
500 <entry>g<subscript>5</subscript></entry>
501 <entry>g<subscript>4</subscript></entry>
502 <entry>g<subscript>3</subscript></entry>
503 <entry>g<subscript>2</subscript></entry>
504 <entry>g<subscript>1</subscript></entry>
505 <entry>g<subscript>0</subscript></entry>
506 <entry>0</entry>
507 <entry>0</entry>
508 <entry>b<subscript>5</subscript></entry>
509 <entry>b<subscript>4</subscript></entry>
510 <entry>b<subscript>3</subscript></entry>
511 <entry>b<subscript>2</subscript></entry>
512 <entry>b<subscript>1</subscript></entry>
513 <entry>b<subscript>0</subscript></entry>
514 </row>
515 <row id="MEDIA-BUS-FMT-BGR888-1X24">
516 <entry>MEDIA_BUS_FMT_BGR888_1X24</entry>
517 <entry>0x1013</entry>
518 <entry></entry>
519 &dash-ent-8;
520 <entry>b<subscript>7</subscript></entry>
521 <entry>b<subscript>6</subscript></entry>
522 <entry>b<subscript>5</subscript></entry>
523 <entry>b<subscript>4</subscript></entry>
524 <entry>b<subscript>3</subscript></entry>
525 <entry>b<subscript>2</subscript></entry>
526 <entry>b<subscript>1</subscript></entry>
527 <entry>b<subscript>0</subscript></entry>
528 <entry>g<subscript>7</subscript></entry>
529 <entry>g<subscript>6</subscript></entry>
530 <entry>g<subscript>5</subscript></entry>
531 <entry>g<subscript>4</subscript></entry>
532 <entry>g<subscript>3</subscript></entry>
533 <entry>g<subscript>2</subscript></entry>
534 <entry>g<subscript>1</subscript></entry>
535 <entry>g<subscript>0</subscript></entry>
536 <entry>r<subscript>7</subscript></entry>
537 <entry>r<subscript>6</subscript></entry>
538 <entry>r<subscript>5</subscript></entry>
539 <entry>r<subscript>4</subscript></entry>
540 <entry>r<subscript>3</subscript></entry>
541 <entry>r<subscript>2</subscript></entry>
542 <entry>r<subscript>1</subscript></entry>
543 <entry>r<subscript>0</subscript></entry>
544 </row>
545 <row id="MEDIA-BUS-FMT-GBR888-1X24">
546 <entry>MEDIA_BUS_FMT_GBR888_1X24</entry>
547 <entry>0x1014</entry>
548 <entry></entry>
549 &dash-ent-8;
550 <entry>g<subscript>7</subscript></entry>
551 <entry>g<subscript>6</subscript></entry>
552 <entry>g<subscript>5</subscript></entry>
553 <entry>g<subscript>4</subscript></entry>
554 <entry>g<subscript>3</subscript></entry>
555 <entry>g<subscript>2</subscript></entry>
556 <entry>g<subscript>1</subscript></entry>
557 <entry>g<subscript>0</subscript></entry>
558 <entry>b<subscript>7</subscript></entry>
559 <entry>b<subscript>6</subscript></entry>
560 <entry>b<subscript>5</subscript></entry>
561 <entry>b<subscript>4</subscript></entry>
562 <entry>b<subscript>3</subscript></entry>
563 <entry>b<subscript>2</subscript></entry>
564 <entry>b<subscript>1</subscript></entry>
565 <entry>b<subscript>0</subscript></entry>
566 <entry>r<subscript>7</subscript></entry>
567 <entry>r<subscript>6</subscript></entry>
568 <entry>r<subscript>5</subscript></entry>
569 <entry>r<subscript>4</subscript></entry>
570 <entry>r<subscript>3</subscript></entry>
571 <entry>r<subscript>2</subscript></entry>
572 <entry>r<subscript>1</subscript></entry>
573 <entry>r<subscript>0</subscript></entry>
574 </row>
443 <row id="MEDIA-BUS-FMT-RGB888-1X24"> 575 <row id="MEDIA-BUS-FMT-RGB888-1X24">
444 <entry>MEDIA_BUS_FMT_RGB888_1X24</entry> 576 <entry>MEDIA_BUS_FMT_RGB888_1X24</entry>
445 <entry>0x100a</entry> 577 <entry>0x100a</entry>
@@ -582,6 +714,261 @@ see <xref linkend="colorspaces" />.</entry>
582 </tbody> 714 </tbody>
583 </tgroup> 715 </tgroup>
584 </table> 716 </table>
717
718 <para>On LVDS buses, usually each sample is transferred serialized in
719 seven time slots per pixel clock, on three (18-bit) or four (24-bit)
720 differential data pairs at the same time. The remaining bits are used for
721 control signals as defined by SPWG/PSWG/VESA or JEIDA standards.
722 The 24-bit RGB format serialized in seven time slots on four lanes using
723 JEIDA defined bit mapping will be named
724 <constant>MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA</constant>, for example.
725 </para>
726
727 <table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-rgb-lvds">
728 <title>LVDS RGB formats</title>
729 <tgroup cols="8">
730 <colspec colname="id" align="left" />
731 <colspec colname="code" align="center" />
732 <colspec colname="slot" align="center" />
733 <colspec colname="lane" />
734 <colspec colnum="5" colname="l03" align="center" />
735 <colspec colnum="6" colname="l02" align="center" />
736 <colspec colnum="7" colname="l01" align="center" />
737 <colspec colnum="8" colname="l00" align="center" />
738 <spanspec namest="l03" nameend="l00" spanname="l0" />
739 <thead>
740 <row>
741 <entry>Identifier</entry>
742 <entry>Code</entry>
743 <entry></entry>
744 <entry></entry>
745 <entry spanname="l0">Data organization</entry>
746 </row>
747 <row>
748 <entry></entry>
749 <entry></entry>
750 <entry>Timeslot</entry>
751 <entry>Lane</entry>
752 <entry>3</entry>
753 <entry>2</entry>
754 <entry>1</entry>
755 <entry>0</entry>
756 </row>
757 </thead>
758 <tbody valign="top">
759 <row id="MEDIA-BUS-FMT-RGB666-1X7X3-SPWG">
760 <entry>MEDIA_BUS_FMT_RGB666_1X7X3_SPWG</entry>
761 <entry>0x1010</entry>
762 <entry>0</entry>
763 <entry></entry>
764 <entry>-</entry>
765 <entry>d</entry>
766 <entry>b<subscript>1</subscript></entry>
767 <entry>g<subscript>0</subscript></entry>
768 </row>
769 <row>
770 <entry></entry>
771 <entry></entry>
772 <entry>1</entry>
773 <entry></entry>
774 <entry>-</entry>
775 <entry>d</entry>
776 <entry>b<subscript>0</subscript></entry>
777 <entry>r<subscript>5</subscript></entry>
778 </row>
779 <row>
780 <entry></entry>
781 <entry></entry>
782 <entry>2</entry>
783 <entry></entry>
784 <entry>-</entry>
785 <entry>d</entry>
786 <entry>g<subscript>5</subscript></entry>
787 <entry>r<subscript>4</subscript></entry>
788 </row>
789 <row>
790 <entry></entry>
791 <entry></entry>
792 <entry>3</entry>
793 <entry></entry>
794 <entry>-</entry>
795 <entry>b<subscript>5</subscript></entry>
796 <entry>g<subscript>4</subscript></entry>
797 <entry>r<subscript>3</subscript></entry>
798 </row>
799 <row>
800 <entry></entry>
801 <entry></entry>
802 <entry>4</entry>
803 <entry></entry>
804 <entry>-</entry>
805 <entry>b<subscript>4</subscript></entry>
806 <entry>g<subscript>3</subscript></entry>
807 <entry>r<subscript>2</subscript></entry>
808 </row>
809 <row>
810 <entry></entry>
811 <entry></entry>
812 <entry>5</entry>
813 <entry></entry>
814 <entry>-</entry>
815 <entry>b<subscript>3</subscript></entry>
816 <entry>g<subscript>2</subscript></entry>
817 <entry>r<subscript>1</subscript></entry>
818 </row>
819 <row>
820 <entry></entry>
821 <entry></entry>
822 <entry>6</entry>
823 <entry></entry>
824 <entry>-</entry>
825 <entry>b<subscript>2</subscript></entry>
826 <entry>g<subscript>1</subscript></entry>
827 <entry>r<subscript>0</subscript></entry>
828 </row>
829 <row id="MEDIA-BUS-FMT-RGB888-1X7X4-SPWG">
830 <entry>MEDIA_BUS_FMT_RGB888_1X7X4_SPWG</entry>
831 <entry>0x1011</entry>
832 <entry>0</entry>
833 <entry></entry>
834 <entry>d</entry>
835 <entry>d</entry>
836 <entry>b<subscript>1</subscript></entry>
837 <entry>g<subscript>0</subscript></entry>
838 </row>
839 <row>
840 <entry></entry>
841 <entry></entry>
842 <entry>1</entry>
843 <entry></entry>
844 <entry>b<subscript>7</subscript></entry>
845 <entry>d</entry>
846 <entry>b<subscript>0</subscript></entry>
847 <entry>r<subscript>5</subscript></entry>
848 </row>
849 <row>
850 <entry></entry>
851 <entry></entry>
852 <entry>2</entry>
853 <entry></entry>
854 <entry>b<subscript>6</subscript></entry>
855 <entry>d</entry>
856 <entry>g<subscript>5</subscript></entry>
857 <entry>r<subscript>4</subscript></entry>
858 </row>
859 <row>
860 <entry></entry>
861 <entry></entry>
862 <entry>3</entry>
863 <entry></entry>
864 <entry>g<subscript>7</subscript></entry>
865 <entry>b<subscript>5</subscript></entry>
866 <entry>g<subscript>4</subscript></entry>
867 <entry>r<subscript>3</subscript></entry>
868 </row>
869 <row>
870 <entry></entry>
871 <entry></entry>
872 <entry>4</entry>
873 <entry></entry>
874 <entry>g<subscript>6</subscript></entry>
875 <entry>b<subscript>4</subscript></entry>
876 <entry>g<subscript>3</subscript></entry>
877 <entry>r<subscript>2</subscript></entry>
878 </row>
879 <row>
880 <entry></entry>
881 <entry></entry>
882 <entry>5</entry>
883 <entry></entry>
884 <entry>r<subscript>7</subscript></entry>
885 <entry>b<subscript>3</subscript></entry>
886 <entry>g<subscript>2</subscript></entry>
887 <entry>r<subscript>1</subscript></entry>
888 </row>
889 <row>
890 <entry></entry>
891 <entry></entry>
892 <entry>6</entry>
893 <entry></entry>
894 <entry>r<subscript>6</subscript></entry>
895 <entry>b<subscript>2</subscript></entry>
896 <entry>g<subscript>1</subscript></entry>
897 <entry>r<subscript>0</subscript></entry>
898 </row>
899 <row id="MEDIA-BUS-FMT-RGB888-1X7X4-JEIDA">
900 <entry>MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA</entry>
901 <entry>0x1012</entry>
902 <entry>0</entry>
903 <entry></entry>
904 <entry>d</entry>
905 <entry>d</entry>
906 <entry>b<subscript>3</subscript></entry>
907 <entry>g<subscript>2</subscript></entry>
908 </row>
909 <row>
910 <entry></entry>
911 <entry></entry>
912 <entry>1</entry>
913 <entry></entry>
914 <entry>b<subscript>1</subscript></entry>
915 <entry>d</entry>
916 <entry>b<subscript>2</subscript></entry>
917 <entry>r<subscript>7</subscript></entry>
918 </row>
919 <row>
920 <entry></entry>
921 <entry></entry>
922 <entry>2</entry>
923 <entry></entry>
924 <entry>b<subscript>0</subscript></entry>
925 <entry>d</entry>
926 <entry>g<subscript>7</subscript></entry>
927 <entry>r<subscript>6</subscript></entry>
928 </row>
929 <row>
930 <entry></entry>
931 <entry></entry>
932 <entry>3</entry>
933 <entry></entry>
934 <entry>g<subscript>1</subscript></entry>
935 <entry>b<subscript>7</subscript></entry>
936 <entry>g<subscript>6</subscript></entry>
937 <entry>r<subscript>5</subscript></entry>
938 </row>
939 <row>
940 <entry></entry>
941 <entry></entry>
942 <entry>4</entry>
943 <entry></entry>
944 <entry>g<subscript>0</subscript></entry>
945 <entry>b<subscript>6</subscript></entry>
946 <entry>g<subscript>5</subscript></entry>
947 <entry>r<subscript>4</subscript></entry>
948 </row>
949 <row>
950 <entry></entry>
951 <entry></entry>
952 <entry>5</entry>
953 <entry></entry>
954 <entry>r<subscript>1</subscript></entry>
955 <entry>b<subscript>5</subscript></entry>
956 <entry>g<subscript>4</subscript></entry>
957 <entry>r<subscript>3</subscript></entry>
958 </row>
959 <row>
960 <entry></entry>
961 <entry></entry>
962 <entry>6</entry>
963 <entry></entry>
964 <entry>r<subscript>0</subscript></entry>
965 <entry>b<subscript>4</subscript></entry>
966 <entry>g<subscript>3</subscript></entry>
967 <entry>r<subscript>2</subscript></entry>
968 </row>
969 </tbody>
970 </tgroup>
971 </table>
585 </section> 972 </section>
586 973
587 <section> 974 <section>
@@ -2660,6 +3047,43 @@ see <xref linkend="colorspaces" />.</entry>
2660 <entry>u<subscript>1</subscript></entry> 3047 <entry>u<subscript>1</subscript></entry>
2661 <entry>u<subscript>0</subscript></entry> 3048 <entry>u<subscript>0</subscript></entry>
2662 </row> 3049 </row>
3050 <row id="MEDIA-BUS-FMT-YUV8-1X24">
3051 <entry>MEDIA_BUS_FMT_YUV8_1X24</entry>
3052 <entry>0x2024</entry>
3053 <entry></entry>
3054 <entry>-</entry>
3055 <entry>-</entry>
3056 <entry>-</entry>
3057 <entry>-</entry>
3058 <entry>-</entry>
3059 <entry>-</entry>
3060 <entry>-</entry>
3061 <entry>-</entry>
3062 <entry>y<subscript>7</subscript></entry>
3063 <entry>y<subscript>6</subscript></entry>
3064 <entry>y<subscript>5</subscript></entry>
3065 <entry>y<subscript>4</subscript></entry>
3066 <entry>y<subscript>3</subscript></entry>
3067 <entry>y<subscript>2</subscript></entry>
3068 <entry>y<subscript>1</subscript></entry>
3069 <entry>y<subscript>0</subscript></entry>
3070 <entry>u<subscript>7</subscript></entry>
3071 <entry>u<subscript>6</subscript></entry>
3072 <entry>u<subscript>5</subscript></entry>
3073 <entry>u<subscript>4</subscript></entry>
3074 <entry>u<subscript>3</subscript></entry>
3075 <entry>u<subscript>2</subscript></entry>
3076 <entry>u<subscript>1</subscript></entry>
3077 <entry>u<subscript>0</subscript></entry>
3078 <entry>v<subscript>7</subscript></entry>
3079 <entry>v<subscript>6</subscript></entry>
3080 <entry>v<subscript>5</subscript></entry>
3081 <entry>v<subscript>4</subscript></entry>
3082 <entry>v<subscript>3</subscript></entry>
3083 <entry>v<subscript>2</subscript></entry>
3084 <entry>v<subscript>1</subscript></entry>
3085 <entry>v<subscript>0</subscript></entry>
3086 </row>
2663 <row id="MEDIA-BUS-FMT-YUV10-1X30"> 3087 <row id="MEDIA-BUS-FMT-YUV10-1X30">
2664 <entry>MEDIA_BUS_FMT_YUV10_1X30</entry> 3088 <entry>MEDIA_BUS_FMT_YUV10_1X30</entry>
2665 <entry>0x2016</entry> 3089 <entry>0x2016</entry>
diff --git a/Documentation/devicetree/bindings/drm/imx/ldb.txt b/Documentation/devicetree/bindings/drm/imx/ldb.txt
index 443bcb6134d5..9a21366436f6 100644
--- a/Documentation/devicetree/bindings/drm/imx/ldb.txt
+++ b/Documentation/devicetree/bindings/drm/imx/ldb.txt
@@ -44,23 +44,30 @@ Optional properties:
44LVDS Channel 44LVDS Channel
45============ 45============
46 46
47Each LVDS Channel has to contain a display-timings node that describes the 47Each LVDS Channel has to contain either an of graph link to a panel device node
48video timings for the connected LVDS display. For detailed information, also 48or a display-timings node that describes the video timings for the connected
49have a look at Documentation/devicetree/bindings/video/display-timing.txt. 49LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
50 50
51Required properties: 51Required properties:
52 - reg : should be <0> or <1> 52 - reg : should be <0> or <1>
53 - port: Input and output port nodes with endpoint definitions as defined in
54 Documentation/devicetree/bindings/graph.txt.
55 On i.MX5, the internal two-input-multiplexer is used. Due to hardware
56 limitations, only one input port (port@[0,1]) can be used for each channel
57 (lvds-channel@[0,1], respectively).
58 On i.MX6, there should be four input ports (port@[0-3]) that correspond
59 to the four LVDS multiplexer inputs.
60 A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
61 to a panel input port. Optionally, the output port can be left out if
62 display-timings are used instead.
63
64Optional properties (required if display-timings are used):
65 - display-timings : A node that describes the display timings as defined in
66 Documentation/devicetree/bindings/video/display-timing.txt.
53 - fsl,data-mapping : should be "spwg" or "jeida" 67 - fsl,data-mapping : should be "spwg" or "jeida"
54 This describes how the color bits are laid out in the 68 This describes how the color bits are laid out in the
55 serialized LVDS signal. 69 serialized LVDS signal.
56 - fsl,data-width : should be <18> or <24> 70 - fsl,data-width : should be <18> or <24>
57 - port: A port node with endpoint definitions as defined in
58 Documentation/devicetree/bindings/media/video-interfaces.txt.
59 On i.MX5, the internal two-input-multiplexer is used.
60 Due to hardware limitations, only one port (port@[0,1])
61 can be used for each channel (lvds-channel@[0,1], respectively)
62 On i.MX6, there should be four ports (port@[0-3]) that correspond
63 to the four LVDS multiplexer inputs.
64 71
65example: 72example:
66 73
@@ -73,23 +80,21 @@ ldb: ldb@53fa8008 {
73 #size-cells = <0>; 80 #size-cells = <0>;
74 compatible = "fsl,imx53-ldb"; 81 compatible = "fsl,imx53-ldb";
75 gpr = <&gpr>; 82 gpr = <&gpr>;
76 clocks = <&clks 122>, <&clks 120>, 83 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
77 <&clks 115>, <&clks 116>, 84 <&clks IMX5_CLK_LDB_DI1_SEL>,
78 <&clks 123>, <&clks 85>; 85 <&clks IMX5_CLK_IPU_DI0_SEL>,
86 <&clks IMX5_CLK_IPU_DI1_SEL>,
87 <&clks IMX5_CLK_LDB_DI0_GATE>,
88 <&clks IMX5_CLK_LDB_DI1_GATE>;
79 clock-names = "di0_pll", "di1_pll", 89 clock-names = "di0_pll", "di1_pll",
80 "di0_sel", "di1_sel", 90 "di0_sel", "di1_sel",
81 "di0", "di1"; 91 "di0", "di1";
82 92
93 /* Using an of-graph endpoint link to connect the panel */
83 lvds-channel@0 { 94 lvds-channel@0 {
84 #address-cells = <1>; 95 #address-cells = <1>;
85 #size-cells = <0>; 96 #size-cells = <0>;
86 reg = <0>; 97 reg = <0>;
87 fsl,data-mapping = "spwg";
88 fsl,data-width = <24>;
89
90 display-timings {
91 /* ... */
92 };
93 98
94 port@0 { 99 port@0 {
95 reg = <0>; 100 reg = <0>;
@@ -98,8 +103,17 @@ ldb: ldb@53fa8008 {
98 remote-endpoint = <&ipu_di0_lvds0>; 103 remote-endpoint = <&ipu_di0_lvds0>;
99 }; 104 };
100 }; 105 };
106
107 port@2 {
108 reg = <2>;
109
110 lvds0_out: endpoint {
111 remote-endpoint = <&panel_in>;
112 };
113 };
101 }; 114 };
102 115
116 /* Using display-timings and fsl,data-mapping/width instead */
103 lvds-channel@1 { 117 lvds-channel@1 {
104 #address-cells = <1>; 118 #address-cells = <1>;
105 #size-cells = <0>; 119 #size-cells = <0>;
@@ -120,3 +134,13 @@ ldb: ldb@53fa8008 {
120 }; 134 };
121 }; 135 };
122}; 136};
137
138panel: lvds-panel {
139 /* ... */
140
141 port {
142 panel_in: endpoint {
143 remote-endpoint = <&lvds0_out>;
144 };
145 };
146};
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 33cdddf26684..2b81a417cf29 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -36,6 +36,7 @@ config DRM_IMX_TVE
36config DRM_IMX_LDB 36config DRM_IMX_LDB
37 tristate "Support for LVDS displays" 37 tristate "Support for LVDS displays"
38 depends on DRM_IMX && MFD_SYSCON 38 depends on DRM_IMX && MFD_SYSCON
39 select DRM_PANEL
39 help 40 help
40 Choose this to enable the internal LVDS Display Bridge (LDB) 41 Choose this to enable the internal LVDS Display Bridge (LDB)
41 found on i.MX53 and i.MX6 processors. 42 found on i.MX53 and i.MX6 processors.
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 87fe8ed92ebe..1834ac8998cc 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -123,7 +123,7 @@ static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder)
123 123
124static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder) 124static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder)
125{ 125{
126 imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24); 126 imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_RGB888_1X24);
127} 127}
128 128
129static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = { 129static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index db2f5a739e05..74f505b0dd02 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -103,8 +103,8 @@ static struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc)
103 return NULL; 103 return NULL;
104} 104}
105 105
106int imx_drm_panel_format_pins(struct drm_encoder *encoder, 106int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format,
107 u32 interface_pix_fmt, int hsync_pin, int vsync_pin) 107 int hsync_pin, int vsync_pin)
108{ 108{
109 struct imx_drm_crtc_helper_funcs *helper; 109 struct imx_drm_crtc_helper_funcs *helper;
110 struct imx_drm_crtc *imx_crtc; 110 struct imx_drm_crtc *imx_crtc;
@@ -116,16 +116,16 @@ int imx_drm_panel_format_pins(struct drm_encoder *encoder,
116 helper = &imx_crtc->imx_drm_helper_funcs; 116 helper = &imx_crtc->imx_drm_helper_funcs;
117 if (helper->set_interface_pix_fmt) 117 if (helper->set_interface_pix_fmt)
118 return helper->set_interface_pix_fmt(encoder->crtc, 118 return helper->set_interface_pix_fmt(encoder->crtc,
119 interface_pix_fmt, hsync_pin, vsync_pin); 119 bus_format, hsync_pin, vsync_pin);
120 return 0; 120 return 0;
121} 121}
122EXPORT_SYMBOL_GPL(imx_drm_panel_format_pins); 122EXPORT_SYMBOL_GPL(imx_drm_set_bus_format_pins);
123 123
124int imx_drm_panel_format(struct drm_encoder *encoder, u32 interface_pix_fmt) 124int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format)
125{ 125{
126 return imx_drm_panel_format_pins(encoder, interface_pix_fmt, 2, 3); 126 return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3);
127} 127}
128EXPORT_SYMBOL_GPL(imx_drm_panel_format); 128EXPORT_SYMBOL_GPL(imx_drm_set_bus_format);
129 129
130int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc) 130int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc)
131{ 131{
diff --git a/drivers/gpu/drm/imx/imx-drm.h b/drivers/gpu/drm/imx/imx-drm.h
index 3c559ccd6af0..28e776d8d9d2 100644
--- a/drivers/gpu/drm/imx/imx-drm.h
+++ b/drivers/gpu/drm/imx/imx-drm.h
@@ -18,7 +18,7 @@ struct imx_drm_crtc_helper_funcs {
18 int (*enable_vblank)(struct drm_crtc *crtc); 18 int (*enable_vblank)(struct drm_crtc *crtc);
19 void (*disable_vblank)(struct drm_crtc *crtc); 19 void (*disable_vblank)(struct drm_crtc *crtc);
20 int (*set_interface_pix_fmt)(struct drm_crtc *crtc, 20 int (*set_interface_pix_fmt)(struct drm_crtc *crtc,
21 u32 pix_fmt, int hsync_pin, int vsync_pin); 21 u32 bus_format, int hsync_pin, int vsync_pin);
22 const struct drm_crtc_helper_funcs *crtc_helper_funcs; 22 const struct drm_crtc_helper_funcs *crtc_helper_funcs;
23 const struct drm_crtc_funcs *crtc_funcs; 23 const struct drm_crtc_funcs *crtc_funcs;
24}; 24};
@@ -40,10 +40,10 @@ void imx_drm_mode_config_init(struct drm_device *drm);
40 40
41struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb); 41struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
42 42
43int imx_drm_panel_format_pins(struct drm_encoder *encoder, 43int imx_drm_set_bus_format_pins(struct drm_encoder *encoder,
44 u32 interface_pix_fmt, int hsync_pin, int vsync_pin); 44 u32 bus_format, int hsync_pin, int vsync_pin);
45int imx_drm_panel_format(struct drm_encoder *encoder, 45int imx_drm_set_bus_format(struct drm_encoder *encoder,
46 u32 interface_pix_fmt); 46 u32 bus_format);
47 47
48int imx_drm_encoder_get_mux_id(struct device_node *node, 48int imx_drm_encoder_get_mux_id(struct device_node *node,
49 struct drm_encoder *encoder); 49 struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index 2d6dc94e1e64..abacc8f67469 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -19,10 +19,11 @@
19#include <drm/drmP.h> 19#include <drm/drmP.h>
20#include <drm/drm_fb_helper.h> 20#include <drm/drm_fb_helper.h>
21#include <drm/drm_crtc_helper.h> 21#include <drm/drm_crtc_helper.h>
22#include <drm/drm_panel.h>
22#include <linux/mfd/syscon.h> 23#include <linux/mfd/syscon.h>
23#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24#include <linux/of_address.h>
25#include <linux/of_device.h> 25#include <linux/of_device.h>
26#include <linux/of_graph.h>
26#include <video/of_videomode.h> 27#include <video/of_videomode.h>
27#include <linux/regmap.h> 28#include <linux/regmap.h>
28#include <linux/videodev2.h> 29#include <linux/videodev2.h>
@@ -55,12 +56,14 @@ struct imx_ldb_channel {
55 struct imx_ldb *ldb; 56 struct imx_ldb *ldb;
56 struct drm_connector connector; 57 struct drm_connector connector;
57 struct drm_encoder encoder; 58 struct drm_encoder encoder;
59 struct drm_panel *panel;
58 struct device_node *child; 60 struct device_node *child;
59 int chno; 61 int chno;
60 void *edid; 62 void *edid;
61 int edid_len; 63 int edid_len;
62 struct drm_display_mode mode; 64 struct drm_display_mode mode;
63 int mode_valid; 65 int mode_valid;
66 int bus_format;
64}; 67};
65 68
66struct bus_mux { 69struct bus_mux {
@@ -75,6 +78,7 @@ struct imx_ldb {
75 struct imx_ldb_channel channel[2]; 78 struct imx_ldb_channel channel[2];
76 struct clk *clk[2]; /* our own clock */ 79 struct clk *clk[2]; /* our own clock */
77 struct clk *clk_sel[4]; /* parent of display clock */ 80 struct clk *clk_sel[4]; /* parent of display clock */
81 struct clk *clk_parent[4]; /* original parent of clk_sel */
78 struct clk *clk_pll[2]; /* upstream clock we can adjust */ 82 struct clk *clk_pll[2]; /* upstream clock we can adjust */
79 u32 ldb_ctrl; 83 u32 ldb_ctrl;
80 const struct bus_mux *lvds_mux; 84 const struct bus_mux *lvds_mux;
@@ -91,6 +95,17 @@ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
91 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); 95 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
92 int num_modes = 0; 96 int num_modes = 0;
93 97
98 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
99 imx_ldb_ch->panel->funcs->get_modes) {
100 struct drm_display_info *di = &connector->display_info;
101
102 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
103 if (!imx_ldb_ch->bus_format && di->num_bus_formats)
104 imx_ldb_ch->bus_format = di->bus_formats[0];
105 if (num_modes > 0)
106 return num_modes;
107 }
108
94 if (imx_ldb_ch->edid) { 109 if (imx_ldb_ch->edid) {
95 drm_mode_connector_update_edid_property(connector, 110 drm_mode_connector_update_edid_property(connector,
96 imx_ldb_ch->edid); 111 imx_ldb_ch->edid);
@@ -163,24 +178,36 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
163{ 178{
164 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 179 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
165 struct imx_ldb *ldb = imx_ldb_ch->ldb; 180 struct imx_ldb *ldb = imx_ldb_ch->ldb;
166 u32 pixel_fmt; 181 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
182 u32 bus_format;
167 183
168 switch (imx_ldb_ch->chno) { 184 switch (imx_ldb_ch->bus_format) {
169 case 0: 185 default:
170 pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ? 186 dev_warn(ldb->dev,
171 V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; 187 "could not determine data mapping, default to 18-bit \"spwg\"\n");
188 /* fallthrough */
189 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
190 bus_format = MEDIA_BUS_FMT_RGB666_1X18;
172 break; 191 break;
173 case 1: 192 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
174 pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ? 193 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
175 V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; 194 if (imx_ldb_ch->chno == 0 || dual)
195 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
196 if (imx_ldb_ch->chno == 1 || dual)
197 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
198 break;
199 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
200 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
201 if (imx_ldb_ch->chno == 0 || dual)
202 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
203 LDB_BIT_MAP_CH0_JEIDA;
204 if (imx_ldb_ch->chno == 1 || dual)
205 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
206 LDB_BIT_MAP_CH1_JEIDA;
176 break; 207 break;
177 default:
178 dev_err(ldb->dev, "unable to config di%d panel format\n",
179 imx_ldb_ch->chno);
180 pixel_fmt = V4L2_PIX_FMT_RGB24;
181 } 208 }
182 209
183 imx_drm_panel_format(encoder, pixel_fmt); 210 imx_drm_set_bus_format(encoder, bus_format);
184} 211}
185 212
186static void imx_ldb_encoder_commit(struct drm_encoder *encoder) 213static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
@@ -190,6 +217,8 @@ static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
190 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 217 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
191 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); 218 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
192 219
220 drm_panel_prepare(imx_ldb_ch->panel);
221
193 if (dual) { 222 if (dual) {
194 clk_prepare_enable(ldb->clk[0]); 223 clk_prepare_enable(ldb->clk[0]);
195 clk_prepare_enable(ldb->clk[1]); 224 clk_prepare_enable(ldb->clk[1]);
@@ -223,6 +252,8 @@ static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
223 } 252 }
224 253
225 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); 254 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
255
256 drm_panel_enable(imx_ldb_ch->panel);
226} 257}
227 258
228static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, 259static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
@@ -274,6 +305,7 @@ static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
274{ 305{
275 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 306 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
276 struct imx_ldb *ldb = imx_ldb_ch->ldb; 307 struct imx_ldb *ldb = imx_ldb_ch->ldb;
308 int mux, ret;
277 309
278 /* 310 /*
279 * imx_ldb_encoder_disable is called by 311 * imx_ldb_encoder_disable is called by
@@ -287,6 +319,8 @@ static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
287 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) 319 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
288 return; 320 return;
289 321
322 drm_panel_disable(imx_ldb_ch->panel);
323
290 if (imx_ldb_ch == &ldb->channel[0]) 324 if (imx_ldb_ch == &ldb->channel[0])
291 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; 325 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
292 else if (imx_ldb_ch == &ldb->channel[1]) 326 else if (imx_ldb_ch == &ldb->channel[1])
@@ -298,6 +332,30 @@ static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
298 clk_disable_unprepare(ldb->clk[0]); 332 clk_disable_unprepare(ldb->clk[0]);
299 clk_disable_unprepare(ldb->clk[1]); 333 clk_disable_unprepare(ldb->clk[1]);
300 } 334 }
335
336 if (ldb->lvds_mux) {
337 const struct bus_mux *lvds_mux = NULL;
338
339 if (imx_ldb_ch == &ldb->channel[0])
340 lvds_mux = &ldb->lvds_mux[0];
341 else if (imx_ldb_ch == &ldb->channel[1])
342 lvds_mux = &ldb->lvds_mux[1];
343
344 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
345 mux &= lvds_mux->mask;
346 mux >>= lvds_mux->shift;
347 } else {
348 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
349 }
350
351 /* set display clock mux back to original input clock */
352 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
353 if (ret)
354 dev_err(ldb->dev,
355 "unable to set di%d parent clock to original parent\n",
356 mux);
357
358 drm_panel_unprepare(imx_ldb_ch->panel);
301} 359}
302 360
303static struct drm_connector_funcs imx_ldb_connector_funcs = { 361static struct drm_connector_funcs imx_ldb_connector_funcs = {
@@ -371,6 +429,9 @@ static int imx_ldb_register(struct drm_device *drm,
371 drm_connector_init(drm, &imx_ldb_ch->connector, 429 drm_connector_init(drm, &imx_ldb_ch->connector,
372 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); 430 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
373 431
432 if (imx_ldb_ch->panel)
433 drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector);
434
374 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, 435 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
375 &imx_ldb_ch->encoder); 436 &imx_ldb_ch->encoder);
376 437
@@ -382,25 +443,39 @@ enum {
382 LVDS_BIT_MAP_JEIDA 443 LVDS_BIT_MAP_JEIDA
383}; 444};
384 445
385static const char * const imx_ldb_bit_mappings[] = { 446struct imx_ldb_bit_mapping {
386 [LVDS_BIT_MAP_SPWG] = "spwg", 447 u32 bus_format;
387 [LVDS_BIT_MAP_JEIDA] = "jeida", 448 u32 datawidth;
449 const char * const mapping;
450};
451
452static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
453 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
454 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
455 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
388}; 456};
389 457
390static const int of_get_data_mapping(struct device_node *np) 458static u32 of_get_bus_format(struct device *dev, struct device_node *np)
391{ 459{
392 const char *bm; 460 const char *bm;
461 u32 datawidth = 0;
393 int ret, i; 462 int ret, i;
394 463
395 ret = of_property_read_string(np, "fsl,data-mapping", &bm); 464 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
396 if (ret < 0) 465 if (ret < 0)
397 return ret; 466 return ret;
398 467
399 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) 468 of_property_read_u32(np, "fsl,data-width", &datawidth);
400 if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
401 return i;
402 469
403 return -EINVAL; 470 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
471 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
472 datawidth == imx_ldb_bit_mappings[i].datawidth)
473 return imx_ldb_bit_mappings[i].bus_format;
474 }
475
476 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
477
478 return -ENOENT;
404} 479}
405 480
406static struct bus_mux imx6q_lvds_mux[2] = { 481static struct bus_mux imx6q_lvds_mux[2] = {
@@ -437,8 +512,6 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
437 struct device_node *child; 512 struct device_node *child;
438 const u8 *edidp; 513 const u8 *edidp;
439 struct imx_ldb *imx_ldb; 514 struct imx_ldb *imx_ldb;
440 int datawidth;
441 int mapping;
442 int dual; 515 int dual;
443 int ret; 516 int ret;
444 int i; 517 int i;
@@ -479,12 +552,15 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
479 imx_ldb->clk_sel[i] = NULL; 552 imx_ldb->clk_sel[i] = NULL;
480 break; 553 break;
481 } 554 }
555
556 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
482 } 557 }
483 if (i == 0) 558 if (i == 0)
484 return ret; 559 return ret;
485 560
486 for_each_child_of_node(np, child) { 561 for_each_child_of_node(np, child) {
487 struct imx_ldb_channel *channel; 562 struct imx_ldb_channel *channel;
563 struct device_node *port;
488 564
489 ret = of_property_read_u32(child, "reg", &i); 565 ret = of_property_read_u32(child, "reg", &i);
490 if (ret || i < 0 || i > 1) 566 if (ret || i < 0 || i > 1)
@@ -503,49 +579,53 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
503 channel->chno = i; 579 channel->chno = i;
504 channel->child = child; 580 channel->child = child;
505 581
582 /*
583 * The output port is port@4 with an external 4-port mux or
584 * port@2 with the internal 2-port mux.
585 */
586 port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
587 if (port) {
588 struct device_node *endpoint, *remote;
589
590 endpoint = of_get_child_by_name(port, "endpoint");
591 if (endpoint) {
592 remote = of_graph_get_remote_port_parent(endpoint);
593 if (remote)
594 channel->panel = of_drm_find_panel(remote);
595 else
596 return -EPROBE_DEFER;
597 if (!channel->panel) {
598 dev_err(dev, "panel not found: %s\n",
599 remote->full_name);
600 return -EPROBE_DEFER;
601 }
602 }
603 }
604
506 edidp = of_get_property(child, "edid", &channel->edid_len); 605 edidp = of_get_property(child, "edid", &channel->edid_len);
507 if (edidp) { 606 if (edidp) {
508 channel->edid = kmemdup(edidp, channel->edid_len, 607 channel->edid = kmemdup(edidp, channel->edid_len,
509 GFP_KERNEL); 608 GFP_KERNEL);
510 } else { 609 } else if (!channel->panel) {
511 ret = of_get_drm_display_mode(child, &channel->mode, 0); 610 ret = of_get_drm_display_mode(child, &channel->mode, 0);
512 if (!ret) 611 if (!ret)
513 channel->mode_valid = 1; 612 channel->mode_valid = 1;
514 } 613 }
515 614
516 ret = of_property_read_u32(child, "fsl,data-width", &datawidth); 615 channel->bus_format = of_get_bus_format(dev, child);
517 if (ret) 616 if (channel->bus_format == -EINVAL) {
518 datawidth = 0; 617 /*
519 else if (datawidth != 18 && datawidth != 24) 618 * If no bus format was specified in the device tree,
520 return -EINVAL; 619 * we can still get it from the connected panel later.
521 620 */
522 mapping = of_get_data_mapping(child); 621 if (channel->panel && channel->panel->funcs &&
523 switch (mapping) { 622 channel->panel->funcs->get_modes)
524 case LVDS_BIT_MAP_SPWG: 623 channel->bus_format = 0;
525 if (datawidth == 24) { 624 }
526 if (i == 0 || dual) 625 if (channel->bus_format < 0) {
527 imx_ldb->ldb_ctrl |= 626 dev_err(dev, "could not determine data mapping: %d\n",
528 LDB_DATA_WIDTH_CH0_24; 627 channel->bus_format);
529 if (i == 1 || dual) 628 return channel->bus_format;
530 imx_ldb->ldb_ctrl |=
531 LDB_DATA_WIDTH_CH1_24;
532 }
533 break;
534 case LVDS_BIT_MAP_JEIDA:
535 if (datawidth == 18) {
536 dev_err(dev, "JEIDA standard only supported in 24 bit\n");
537 return -EINVAL;
538 }
539 if (i == 0 || dual)
540 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
541 LDB_BIT_MAP_CH0_JEIDA;
542 if (i == 1 || dual)
543 imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
544 LDB_BIT_MAP_CH1_JEIDA;
545 break;
546 default:
547 dev_err(dev, "data mapping not specified or invalid\n");
548 return -EINVAL;
549 } 629 }
550 630
551 ret = imx_ldb_register(drm, channel); 631 ret = imx_ldb_register(drm, channel);
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index 4216e479a9be..214eceefc981 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -301,11 +301,11 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
301 301
302 switch (tve->mode) { 302 switch (tve->mode) {
303 case TVE_MODE_VGA: 303 case TVE_MODE_VGA:
304 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24, 304 imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_YUV8_1X24,
305 tve->hsync_pin, tve->vsync_pin); 305 tve->hsync_pin, tve->vsync_pin);
306 break; 306 break;
307 case TVE_MODE_TVOUT: 307 case TVE_MODE_TVOUT:
308 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444); 308 imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24);
309 break; 309 break;
310 } 310 }
311} 311}
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 98551e356e12..7bc8301fafff 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -45,7 +45,7 @@ struct ipu_crtc {
45 struct drm_pending_vblank_event *page_flip_event; 45 struct drm_pending_vblank_event *page_flip_event;
46 struct drm_framebuffer *newfb; 46 struct drm_framebuffer *newfb;
47 int irq; 47 int irq;
48 u32 interface_pix_fmt; 48 u32 bus_format;
49 int di_hsync_pin; 49 int di_hsync_pin;
50 int di_vsync_pin; 50 int di_vsync_pin;
51}; 51};
@@ -145,7 +145,6 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
145 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); 145 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
146 struct ipu_di_signal_cfg sig_cfg = {}; 146 struct ipu_di_signal_cfg sig_cfg = {};
147 unsigned long encoder_types = 0; 147 unsigned long encoder_types = 0;
148 u32 out_pixel_fmt;
149 int ret; 148 int ret;
150 149
151 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__, 150 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
@@ -161,21 +160,21 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
161 __func__, encoder_types); 160 __func__, encoder_types);
162 161
163 /* 162 /*
164 * If we have DAC, TVDAC or LDB, then we need the IPU DI clock 163 * If we have DAC or LDB, then we need the IPU DI clock to be
165 * to be the same as the LDB DI clock. 164 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
165 * clock from 27 MHz TVE_DI clock, but allow to divide it.
166 */ 166 */
167 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | 167 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
168 BIT(DRM_MODE_ENCODER_TVDAC) |
169 BIT(DRM_MODE_ENCODER_LVDS))) 168 BIT(DRM_MODE_ENCODER_LVDS)))
170 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; 169 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
170 else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
171 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
171 else 172 else
172 sig_cfg.clkflags = 0; 173 sig_cfg.clkflags = 0;
173 174
174 out_pixel_fmt = ipu_crtc->interface_pix_fmt;
175
176 sig_cfg.enable_pol = 1; 175 sig_cfg.enable_pol = 1;
177 sig_cfg.clk_pol = 0; 176 sig_cfg.clk_pol = 0;
178 sig_cfg.pixel_fmt = out_pixel_fmt; 177 sig_cfg.bus_format = ipu_crtc->bus_format;
179 sig_cfg.v_to_h_sync = 0; 178 sig_cfg.v_to_h_sync = 0;
180 sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; 179 sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
181 sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin; 180 sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
@@ -184,7 +183,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
184 183
185 ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, 184 ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
186 mode->flags & DRM_MODE_FLAG_INTERLACE, 185 mode->flags & DRM_MODE_FLAG_INTERLACE,
187 out_pixel_fmt, mode->hdisplay); 186 ipu_crtc->bus_format, mode->hdisplay);
188 if (ret) { 187 if (ret) {
189 dev_err(ipu_crtc->dev, 188 dev_err(ipu_crtc->dev,
190 "initializing display controller failed with %d\n", 189 "initializing display controller failed with %d\n",
@@ -202,7 +201,8 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
202 return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode, 201 return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode,
203 crtc->primary->fb, 202 crtc->primary->fb,
204 0, 0, mode->hdisplay, mode->vdisplay, 203 0, 0, mode->hdisplay, mode->vdisplay,
205 x, y, mode->hdisplay, mode->vdisplay); 204 x, y, mode->hdisplay, mode->vdisplay,
205 mode->flags & DRM_MODE_FLAG_INTERLACE);
206} 206}
207 207
208static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc) 208static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
@@ -291,11 +291,11 @@ static void ipu_disable_vblank(struct drm_crtc *crtc)
291} 291}
292 292
293static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, 293static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc,
294 u32 pixfmt, int hsync_pin, int vsync_pin) 294 u32 bus_format, int hsync_pin, int vsync_pin)
295{ 295{
296 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); 296 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
297 297
298 ipu_crtc->interface_pix_fmt = pixfmt; 298 ipu_crtc->bus_format = bus_format;
299 ipu_crtc->di_hsync_pin = hsync_pin; 299 ipu_crtc->di_hsync_pin = hsync_pin;
300 ipu_crtc->di_vsync_pin = vsync_pin; 300 ipu_crtc->di_vsync_pin = vsync_pin;
301 301
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 6987e16fe99b..878a643d72e4 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -99,7 +99,7 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
99 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 99 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
100 unsigned int crtc_w, unsigned int crtc_h, 100 unsigned int crtc_w, unsigned int crtc_h,
101 uint32_t src_x, uint32_t src_y, 101 uint32_t src_x, uint32_t src_y,
102 uint32_t src_w, uint32_t src_h) 102 uint32_t src_w, uint32_t src_h, bool interlaced)
103{ 103{
104 struct device *dev = ipu_plane->base.dev->dev; 104 struct device *dev = ipu_plane->base.dev->dev;
105 int ret; 105 int ret;
@@ -213,6 +213,8 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
213 ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y); 213 ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
214 if (ret < 0) 214 if (ret < 0)
215 return ret; 215 return ret;
216 if (interlaced)
217 ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
216 218
217 ipu_plane->w = src_w; 219 ipu_plane->w = src_w;
218 ipu_plane->h = src_h; 220 ipu_plane->h = src_h;
@@ -312,7 +314,8 @@ static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
312 314
313 ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb, 315 ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
314 crtc_x, crtc_y, crtc_w, crtc_h, 316 crtc_x, crtc_y, crtc_w, crtc_h,
315 src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16); 317 src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
318 false);
316 if (ret < 0) { 319 if (ret < 0) {
317 ipu_plane_put_resources(ipu_plane); 320 ipu_plane_put_resources(ipu_plane);
318 return ret; 321 return ret;
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.h b/drivers/gpu/drm/imx/ipuv3-plane.h
index af125fb40ef5..9b5eff18f5b8 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.h
+++ b/drivers/gpu/drm/imx/ipuv3-plane.h
@@ -42,7 +42,7 @@ int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
42 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 42 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
43 unsigned int crtc_w, unsigned int crtc_h, 43 unsigned int crtc_w, unsigned int crtc_h,
44 uint32_t src_x, uint32_t src_y, uint32_t src_w, 44 uint32_t src_x, uint32_t src_y, uint32_t src_w,
45 uint32_t src_h); 45 uint32_t src_h, bool interlaced);
46 46
47void ipu_plane_enable(struct ipu_plane *plane); 47void ipu_plane_enable(struct ipu_plane *plane);
48void ipu_plane_disable(struct ipu_plane *plane); 48void ipu_plane_disable(struct ipu_plane *plane);
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c
index 900dda6a8e71..74a9ce40ddc4 100644
--- a/drivers/gpu/drm/imx/parallel-display.c
+++ b/drivers/gpu/drm/imx/parallel-display.c
@@ -33,7 +33,7 @@ struct imx_parallel_display {
33 struct device *dev; 33 struct device *dev;
34 void *edid; 34 void *edid;
35 int edid_len; 35 int edid_len;
36 u32 interface_pix_fmt; 36 u32 bus_format;
37 int mode_valid; 37 int mode_valid;
38 struct drm_display_mode mode; 38 struct drm_display_mode mode;
39 struct drm_panel *panel; 39 struct drm_panel *panel;
@@ -118,7 +118,7 @@ static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
118{ 118{
119 struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); 119 struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
120 120
121 imx_drm_panel_format(encoder, imxpd->interface_pix_fmt); 121 imx_drm_set_bus_format(encoder, imxpd->bus_format);
122} 122}
123 123
124static void imx_pd_encoder_commit(struct drm_encoder *encoder) 124static void imx_pd_encoder_commit(struct drm_encoder *encoder)
@@ -225,14 +225,13 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
225 ret = of_property_read_string(np, "interface-pix-fmt", &fmt); 225 ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
226 if (!ret) { 226 if (!ret) {
227 if (!strcmp(fmt, "rgb24")) 227 if (!strcmp(fmt, "rgb24"))
228 imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB24; 228 imxpd->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
229 else if (!strcmp(fmt, "rgb565")) 229 else if (!strcmp(fmt, "rgb565"))
230 imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB565; 230 imxpd->bus_format = MEDIA_BUS_FMT_RGB565_1X16;
231 else if (!strcmp(fmt, "bgr666")) 231 else if (!strcmp(fmt, "bgr666"))
232 imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666; 232 imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
233 else if (!strcmp(fmt, "lvds666")) 233 else if (!strcmp(fmt, "lvds666"))
234 imxpd->interface_pix_fmt = 234 imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI;
235 v4l2_fourcc('L', 'V', 'D', '6');
236 } 235 }
237 236
238 panel_node = of_parse_phandle(np, "fsl,panel", 0); 237 panel_node = of_parse_phandle(np, "fsl,panel", 0);
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 4864f8300797..9ef2e1f54ca4 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -147,20 +147,20 @@ static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); 147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
148} 148}
149 149
150static int ipu_pixfmt_to_map(u32 fmt) 150static int ipu_bus_format_to_map(u32 fmt)
151{ 151{
152 switch (fmt) { 152 switch (fmt) {
153 case V4L2_PIX_FMT_RGB24: 153 case MEDIA_BUS_FMT_RGB888_1X24:
154 return IPU_DC_MAP_RGB24; 154 return IPU_DC_MAP_RGB24;
155 case V4L2_PIX_FMT_RGB565: 155 case MEDIA_BUS_FMT_RGB565_1X16:
156 return IPU_DC_MAP_RGB565; 156 return IPU_DC_MAP_RGB565;
157 case IPU_PIX_FMT_GBR24: 157 case MEDIA_BUS_FMT_GBR888_1X24:
158 return IPU_DC_MAP_GBR24; 158 return IPU_DC_MAP_GBR24;
159 case V4L2_PIX_FMT_BGR666: 159 case MEDIA_BUS_FMT_RGB666_1X18:
160 return IPU_DC_MAP_BGR666; 160 return IPU_DC_MAP_BGR666;
161 case v4l2_fourcc('L', 'V', 'D', '6'): 161 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
162 return IPU_DC_MAP_LVDS666; 162 return IPU_DC_MAP_LVDS666;
163 case V4L2_PIX_FMT_BGR24: 163 case MEDIA_BUS_FMT_BGR888_1X24:
164 return IPU_DC_MAP_BGR24; 164 return IPU_DC_MAP_BGR24;
165 default: 165 default:
166 return -EINVAL; 166 return -EINVAL;
@@ -168,7 +168,7 @@ static int ipu_pixfmt_to_map(u32 fmt)
168} 168}
169 169
170int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, 170int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
171 u32 pixel_fmt, u32 width) 171 u32 bus_format, u32 width)
172{ 172{
173 struct ipu_dc_priv *priv = dc->priv; 173 struct ipu_dc_priv *priv = dc->priv;
174 u32 reg = 0; 174 u32 reg = 0;
@@ -176,7 +176,7 @@ int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
176 176
177 dc->di = ipu_di_get_num(di); 177 dc->di = ipu_di_get_num(di);
178 178
179 map = ipu_pixfmt_to_map(pixel_fmt); 179 map = ipu_bus_format_to_map(bus_format);
180 if (map < 0) { 180 if (map < 0) {
181 dev_dbg(priv->dev, "IPU_DISP: No MAP\n"); 181 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
182 return map; 182 return map;
diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
index 23b40908be30..83ea46f4be51 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -33,22 +33,30 @@
33 33
34#define MEDIA_BUS_FMT_FIXED 0x0001 34#define MEDIA_BUS_FMT_FIXED 0x0001
35 35
36/* RGB - next is 0x100e */ 36/* RGB - next is 0x1016 */
37#define MEDIA_BUS_FMT_RGB444_1X12 0x100e
37#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 38#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
38#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 39#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
39#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 40#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
40#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 41#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
42#define MEDIA_BUS_FMT_RGB565_1X16 0x100f
41#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 43#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
42#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 44#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006
43#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 45#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007
44#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 46#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008
45#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 47#define MEDIA_BUS_FMT_RGB666_1X18 0x1009
48#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015
49#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010
50#define MEDIA_BUS_FMT_BGR888_1X24 0x1013
51#define MEDIA_BUS_FMT_GBR888_1X24 0x1014
46#define MEDIA_BUS_FMT_RGB888_1X24 0x100a 52#define MEDIA_BUS_FMT_RGB888_1X24 0x100a
47#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b 53#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b
48#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c 54#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c
55#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
56#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
49#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d 57#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
50 58
51/* YUV (including grey) - next is 0x2024 */ 59/* YUV (including grey) - next is 0x2025 */
52#define MEDIA_BUS_FMT_Y8_1X8 0x2001 60#define MEDIA_BUS_FMT_Y8_1X8 0x2001
53#define MEDIA_BUS_FMT_UV8_1X8 0x2015 61#define MEDIA_BUS_FMT_UV8_1X8 0x2015
54#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 62#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002
@@ -74,6 +82,7 @@
74#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b 82#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b
75#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d 83#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d
76#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e 84#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e
85#define MEDIA_BUS_FMT_YUV8_1X24 0x2024
77#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 86#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
78#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 87#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
79#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c 88#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 73390c120cad..85dedca3dcfb 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -39,7 +39,7 @@ struct ipu_di_signal_cfg {
39 39
40 struct videomode mode; 40 struct videomode mode;
41 41
42 u32 pixel_fmt; 42 u32 bus_format;
43 u32 v_to_h_sync; 43 u32 v_to_h_sync;
44 44
45#define IPU_DI_CLKMODE_SYNC (1 << 0) 45#define IPU_DI_CLKMODE_SYNC (1 << 0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 19:28:26 -0500