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authorGeert Uytterhoeven <geert+renesas@glider.be>2015-03-18 14:55:55 -0400
committerJason Cooper <jason@lakedaemon.net>2015-03-23 05:34:32 -0400
commit1cd5ec73306d6e361b90e27ae17bd5f87e009567 (patch)
tree84c34b2e3952ac54b97003202bef5a6d889b6f8c
parentc517d838eb7d07bbe9507871fab3931deccff539 (diff)
irqchip: renesas-irqc: Add more register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lkml.kernel.org/r/1426704961-27322-2-git-send-email-geert+renesas@glider.be Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--drivers/irqchip/irq-renesas-irqc.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
index 384e6ed61d7c..44fe04a8da95 100644
--- a/drivers/irqchip/irq-renesas-irqc.c
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -30,14 +30,24 @@
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/platform_data/irq-renesas-irqc.h> 31#include <linux/platform_data/irq-renesas-irqc.h>
32 32
33#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ 33#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
34 34
35#define IRQC_REQ_STS 0x00 35#define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */
36#define IRQC_EN_STS 0x04 36#define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */
37#define IRQC_EN_SET 0x08 37#define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */
38#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) 38#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
39#define DETECT_STATUS 0x100 39 /* SYS-CPU vs. RT-CPU */
40#define DETECT_STATUS 0x100 /* IRQn Detect Status Register */
41#define MONITOR 0x104 /* IRQn Signal Level Monitor Register */
42#define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */
43#define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */
44#define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */
45#define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */
46#define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */
47#define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */
48#define CHTEN_STS 0x120 /* Chattering Reduction Status Register */
40#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) 49#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
50 /* IRQn Configuration Register */
41 51
42struct irqc_irq { 52struct irqc_irq {
43 int hw_irq; 53 int hw_irq;