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authorTomeu Vizoso <tomeu.vizoso@collabora.com>2015-01-23 06:03:31 -0500
committerMichael Turquette <mturquette@linaro.org>2015-02-02 17:23:42 -0500
commit1c8e600440c7f5036bd9a94526d01e9c7cb68dca (patch)
tree36c9811e976332bc23a00a6fb216dce5e6b55a5a
parentb09d6d99102504a929cfaba4cd0e07658d7f01d1 (diff)
clk: Add rate constraints to clocks
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
Diffstat
-rw-r--r--Documentation/clk.txt2
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c2
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c2
-rw-r--r--arch/mips/alchemy/common/clock.c8
-rw-r--r--drivers/clk/at91/clk-programmable.c2
-rw-r--r--drivers/clk/bcm/clk-kona.c2
-rw-r--r--drivers/clk/clk-composite.c9
-rw-r--r--drivers/clk/clk.c272
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c2
-rw-r--r--drivers/clk/mmp/clk-mix.c2
-rw-r--r--drivers/clk/qcom/clk-pll.c1
-rw-r--r--drivers/clk/qcom/clk-rcg.c10
-rw-r--r--drivers/clk/qcom/clk-rcg2.c6
-rw-r--r--drivers/clk/sunxi/clk-factors.c2
-rw-r--r--drivers/clk/sunxi/clk-sun6i-ar100.c2
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c2
-rw-r--r--include/linux/clk-provider.h17
-rw-r--r--include/linux/clk.h28
-rw-r--r--include/linux/clk/ti.h4
19 files changed, 314 insertions, 61 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 4ff84623d5e1..0e4f90aa1c13 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -73,6 +73,8 @@ the operations defined in clk.h:
73 unsigned long *parent_rate); 73 unsigned long *parent_rate);
74 long (*determine_rate)(struct clk_hw *hw, 74 long (*determine_rate)(struct clk_hw *hw,
75 unsigned long rate, 75 unsigned long rate,
76 unsigned long min_rate,
77 unsigned long max_rate,
76 unsigned long *best_parent_rate, 78 unsigned long *best_parent_rate,
77 struct clk_hw **best_parent_clk); 79 struct clk_hw **best_parent_clk);
78 int (*set_parent)(struct clk_hw *hw, u8 index); 80 int (*set_parent)(struct clk_hw *hw, u8 index);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 49752d77f5bc..44e57ec225d4 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
473 * in failure. 473 * in failure.
474 */ 474 */
475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, 475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long min_rate,
477 unsigned long max_rate,
476 unsigned long *best_parent_rate, 478 unsigned long *best_parent_rate,
477 struct clk_hw **best_parent_clk) 479 struct clk_hw **best_parent_clk)
478{ 480{
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 0e58e5a85d53..acacb900a58b 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -222,6 +222,8 @@ out:
222 * in failure. 222 * in failure.
223 */ 223 */
224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, 224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long min_rate,
226 unsigned long max_rate,
225 unsigned long *best_parent_rate, 227 unsigned long *best_parent_rate,
226 struct clk_hw **best_parent_clk) 228 struct clk_hw **best_parent_clk)
227{ 229{
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 48a9dfc55b51..4e65404b3ba3 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -373,6 +373,8 @@ static long alchemy_calc_div(unsigned long rate, unsigned long prate,
373} 373}
374 374
375static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate, 375static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
376 unsigned long min_rate,
377 unsigned long max_rate,
376 unsigned long *best_parent_rate, 378 unsigned long *best_parent_rate,
377 struct clk_hw **best_parent_clk, 379 struct clk_hw **best_parent_clk,
378 int scale, int maxdiv) 380 int scale, int maxdiv)
@@ -546,6 +548,8 @@ static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
546} 548}
547 549
548static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate, 550static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
551 unsigned long min_rate,
552 unsigned long max_rate,
549 unsigned long *best_parent_rate, 553 unsigned long *best_parent_rate,
550 struct clk_hw **best_parent_clk) 554 struct clk_hw **best_parent_clk)
551{ 555{
@@ -678,6 +682,8 @@ static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
678} 682}
679 683
680static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate, 684static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
685 unsigned long min_rate,
686 unsigned long max_rate,
681 unsigned long *best_parent_rate, 687 unsigned long *best_parent_rate,
682 struct clk_hw **best_parent_clk) 688 struct clk_hw **best_parent_clk)
683{ 689{
@@ -897,6 +903,8 @@ static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
897} 903}
898 904
899static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate, 905static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
906 unsigned long min_rate,
907 unsigned long max_rate,
900 unsigned long *best_parent_rate, 908 unsigned long *best_parent_rate,
901 struct clk_hw **best_parent_clk) 909 struct clk_hw **best_parent_clk)
902{ 910{
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index bbdb1b985c91..86c8a073dcc3 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -56,6 +56,8 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
56 56
57static long clk_programmable_determine_rate(struct clk_hw *hw, 57static long clk_programmable_determine_rate(struct clk_hw *hw,
58 unsigned long rate, 58 unsigned long rate,
59 unsigned long min_rate,
60 unsigned long max_rate,
59 unsigned long *best_parent_rate, 61 unsigned long *best_parent_rate,
60 struct clk_hw **best_parent_hw) 62 struct clk_hw **best_parent_hw)
61{ 63{
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
index 1c06f6f3a8c5..05abae89262e 100644
--- a/drivers/clk/bcm/clk-kona.c
+++ b/drivers/clk/bcm/clk-kona.c
@@ -1032,6 +1032,8 @@ static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1032} 1032}
1033 1033
1034static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate, 1034static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
1035 unsigned long min_rate,
1036 unsigned long max_rate,
1035 unsigned long *best_parent_rate, struct clk_hw **best_parent) 1037 unsigned long *best_parent_rate, struct clk_hw **best_parent)
1036{ 1038{
1037 struct kona_clk *bcm_clk = to_kona_clk(hw); 1039 struct kona_clk *bcm_clk = to_kona_clk(hw);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 4386697236a7..dee81b83c4b3 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -56,6 +56,8 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
56} 56}
57 57
58static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, 58static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long min_rate,
60 unsigned long max_rate,
59 unsigned long *best_parent_rate, 61 unsigned long *best_parent_rate,
60 struct clk_hw **best_parent_p) 62 struct clk_hw **best_parent_p)
61{ 63{
@@ -73,7 +75,9 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
73 75
74 if (rate_hw && rate_ops && rate_ops->determine_rate) { 76 if (rate_hw && rate_ops && rate_ops->determine_rate) {
75 rate_hw->clk = hw->clk; 77 rate_hw->clk = hw->clk;
76 return rate_ops->determine_rate(rate_hw, rate, best_parent_rate, 78 return rate_ops->determine_rate(rate_hw, rate, min_rate,
79 max_rate,
80 best_parent_rate,
77 best_parent_p); 81 best_parent_p);
78 } else if (rate_hw && rate_ops && rate_ops->round_rate && 82 } else if (rate_hw && rate_ops && rate_ops->round_rate &&
79 mux_hw && mux_ops && mux_ops->set_parent) { 83 mux_hw && mux_ops && mux_ops->set_parent) {
@@ -117,7 +121,8 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
117 return best_rate; 121 return best_rate;
118 } else if (mux_hw && mux_ops && mux_ops->determine_rate) { 122 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
119 mux_hw->clk = hw->clk; 123 mux_hw->clk = hw->clk;
120 return mux_ops->determine_rate(mux_hw, rate, best_parent_rate, 124 return mux_ops->determine_rate(mux_hw, rate, min_rate,
125 max_rate, best_parent_rate,
121 best_parent_p); 126 best_parent_p);
122 } else { 127 } else {
123 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n"); 128 pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index cdc1fa58e4f1..113456030d66 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -42,8 +42,6 @@ static unsigned long clk_core_get_rate(struct clk_core *clk);
42static int clk_core_get_phase(struct clk_core *clk); 42static int clk_core_get_phase(struct clk_core *clk);
43static bool clk_core_is_prepared(struct clk_core *clk); 43static bool clk_core_is_prepared(struct clk_core *clk);
44static bool clk_core_is_enabled(struct clk_core *clk); 44static bool clk_core_is_enabled(struct clk_core *clk);
45static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
46 unsigned long rate);
47static struct clk_core *clk_core_lookup(const char *name); 45static struct clk_core *clk_core_lookup(const char *name);
48 46
49/*** private data structures ***/ 47/*** private data structures ***/
@@ -59,6 +57,7 @@ struct clk_core {
59 u8 num_parents; 57 u8 num_parents;
60 u8 new_parent_index; 58 u8 new_parent_index;
61 unsigned long rate; 59 unsigned long rate;
60 unsigned long req_rate;
62 unsigned long new_rate; 61 unsigned long new_rate;
63 struct clk_core *new_parent; 62 struct clk_core *new_parent;
64 struct clk_core *new_child; 63 struct clk_core *new_child;
@@ -70,6 +69,7 @@ struct clk_core {
70 struct hlist_head children; 69 struct hlist_head children;
71 struct hlist_node child_node; 70 struct hlist_node child_node;
72 struct hlist_node debug_node; 71 struct hlist_node debug_node;
72 struct hlist_head clks;
73 unsigned int notifier_count; 73 unsigned int notifier_count;
74#ifdef CONFIG_DEBUG_FS 74#ifdef CONFIG_DEBUG_FS
75 struct dentry *dentry; 75 struct dentry *dentry;
@@ -81,6 +81,9 @@ struct clk {
81 struct clk_core *core; 81 struct clk_core *core;
82 const char *dev_id; 82 const char *dev_id;
83 const char *con_id; 83 const char *con_id;
84 unsigned long min_rate;
85 unsigned long max_rate;
86 struct hlist_node child_node;
84}; 87};
85 88
86/*** locking ***/ 89/*** locking ***/
@@ -783,6 +786,8 @@ static bool mux_is_better_rate(unsigned long rate, unsigned long now,
783 786
784static long 787static long
785clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate, 788clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
789 unsigned long min_rate,
790 unsigned long max_rate,
786 unsigned long *best_parent_rate, 791 unsigned long *best_parent_rate,
787 struct clk_hw **best_parent_p, 792 struct clk_hw **best_parent_p,
788 unsigned long flags) 793 unsigned long flags)
@@ -795,7 +800,8 @@ clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
795 if (core->flags & CLK_SET_RATE_NO_REPARENT) { 800 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
796 parent = core->parent; 801 parent = core->parent;
797 if (core->flags & CLK_SET_RATE_PARENT) 802 if (core->flags & CLK_SET_RATE_PARENT)
798 best = clk_core_round_rate_nolock(parent, rate); 803 best = __clk_determine_rate(parent->hw, rate,
804 min_rate, max_rate);
799 else if (parent) 805 else if (parent)
800 best = clk_core_get_rate_nolock(parent); 806 best = clk_core_get_rate_nolock(parent);
801 else 807 else
@@ -810,7 +816,9 @@ clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
810 if (!parent) 816 if (!parent)
811 continue; 817 continue;
812 if (core->flags & CLK_SET_RATE_PARENT) 818 if (core->flags & CLK_SET_RATE_PARENT)
813 parent_rate = clk_core_round_rate_nolock(parent, rate); 819 parent_rate = __clk_determine_rate(parent->hw, rate,
820 min_rate,
821 max_rate);
814 else 822 else
815 parent_rate = clk_core_get_rate_nolock(parent); 823 parent_rate = clk_core_get_rate_nolock(parent);
816 if (mux_is_better_rate(rate, parent_rate, best, flags)) { 824 if (mux_is_better_rate(rate, parent_rate, best, flags)) {
@@ -834,25 +842,47 @@ struct clk *__clk_lookup(const char *name)
834 return !core ? NULL : core->hw->clk; 842 return !core ? NULL : core->hw->clk;
835} 843}
836 844
845static void clk_core_get_boundaries(struct clk_core *clk,
846 unsigned long *min_rate,
847 unsigned long *max_rate)
848{
849 struct clk *clk_user;
850
851 *min_rate = 0;
852 *max_rate = ULONG_MAX;
853
854 hlist_for_each_entry(clk_user, &clk->clks, child_node)
855 *min_rate = max(*min_rate, clk_user->min_rate);
856
857 hlist_for_each_entry(clk_user, &clk->clks, child_node)
858 *max_rate = min(*max_rate, clk_user->max_rate);
859}
860
837/* 861/*
838 * Helper for finding best parent to provide a given frequency. This can be used 862 * Helper for finding best parent to provide a given frequency. This can be used
839 * directly as a determine_rate callback (e.g. for a mux), or from a more 863 * directly as a determine_rate callback (e.g. for a mux), or from a more
840 * complex clock that may combine a mux with other operations. 864 * complex clock that may combine a mux with other operations.
841 */ 865 */
842long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 866long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
867 unsigned long min_rate,
868 unsigned long max_rate,
843 unsigned long *best_parent_rate, 869 unsigned long *best_parent_rate,
844 struct clk_hw **best_parent_p) 870 struct clk_hw **best_parent_p)
845{ 871{
846 return clk_mux_determine_rate_flags(hw, rate, best_parent_rate, 872 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
873 best_parent_rate,
847 best_parent_p, 0); 874 best_parent_p, 0);
848} 875}
849EXPORT_SYMBOL_GPL(__clk_mux_determine_rate); 876EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
850 877
851long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate, 878long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
879 unsigned long min_rate,
880 unsigned long max_rate,
852 unsigned long *best_parent_rate, 881 unsigned long *best_parent_rate,
853 struct clk_hw **best_parent_p) 882 struct clk_hw **best_parent_p)
854{ 883{
855 return clk_mux_determine_rate_flags(hw, rate, best_parent_rate, 884 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
885 best_parent_rate,
856 best_parent_p, 886 best_parent_p,
857 CLK_MUX_ROUND_CLOSEST); 887 CLK_MUX_ROUND_CLOSEST);
858} 888}
@@ -1068,7 +1098,9 @@ int clk_enable(struct clk *clk)
1068EXPORT_SYMBOL_GPL(clk_enable); 1098EXPORT_SYMBOL_GPL(clk_enable);
1069 1099
1070static unsigned long clk_core_round_rate_nolock(struct clk_core *clk, 1100static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
1071 unsigned long rate) 1101 unsigned long rate,
1102 unsigned long min_rate,
1103 unsigned long max_rate)
1072{ 1104{
1073 unsigned long parent_rate = 0; 1105 unsigned long parent_rate = 0;
1074 struct clk_core *parent; 1106 struct clk_core *parent;
@@ -1083,17 +1115,41 @@ static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
1083 1115
1084 if (clk->ops->determine_rate) { 1116 if (clk->ops->determine_rate) {
1085 parent_hw = parent ? parent->hw : NULL; 1117 parent_hw = parent ? parent->hw : NULL;
1086 return clk->ops->determine_rate(clk->hw, rate, &parent_rate, 1118 return clk->ops->determine_rate(clk->hw, rate,
1087 &parent_hw); 1119 min_rate, max_rate,
1120 &parent_rate, &parent_hw);
1088 } else if (clk->ops->round_rate) 1121 } else if (clk->ops->round_rate)
1089 return clk->ops->round_rate(clk->hw, rate, &parent_rate); 1122 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
1090 else if (clk->flags & CLK_SET_RATE_PARENT) 1123 else if (clk->flags & CLK_SET_RATE_PARENT)
1091 return clk_core_round_rate_nolock(clk->parent, rate); 1124 return clk_core_round_rate_nolock(clk->parent, rate, min_rate,
1125 max_rate);
1092 else 1126 else
1093 return clk->rate; 1127 return clk->rate;
1094} 1128}
1095 1129
1096/** 1130/**
1131 * __clk_determine_rate - get the closest rate actually supported by a clock
1132 * @hw: determine the rate of this clock
1133 * @rate: target rate
1134 * @min_rate: returned rate must be greater than this rate
1135 * @max_rate: returned rate must be less than this rate
1136 *
1137 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate and
1138 * .determine_rate.
1139 */
1140unsigned long __clk_determine_rate(struct clk_hw *hw,
1141 unsigned long rate,
1142 unsigned long min_rate,
1143 unsigned long max_rate)
1144{
1145 if (!hw)
1146 return 0;
1147
1148 return clk_core_round_rate_nolock(hw->core, rate, min_rate, max_rate);
1149}
1150EXPORT_SYMBOL_GPL(__clk_determine_rate);
1151
1152/**
1097 * __clk_round_rate - round the given rate for a clk 1153 * __clk_round_rate - round the given rate for a clk
1098 * @clk: round the rate of this clock 1154 * @clk: round the rate of this clock
1099 * @rate: the rate which is to be rounded 1155 * @rate: the rate which is to be rounded
@@ -1102,10 +1158,15 @@ static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
1102 */ 1158 */
1103unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) 1159unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
1104{ 1160{
1161 unsigned long min_rate;
1162 unsigned long max_rate;
1163
1105 if (!clk) 1164 if (!clk)
1106 return 0; 1165 return 0;
1107 1166
1108 return clk_core_round_rate_nolock(clk->core, rate); 1167 clk_core_get_boundaries(clk->core, &min_rate, &max_rate);
1168
1169 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate);
1109} 1170}
1110EXPORT_SYMBOL_GPL(__clk_round_rate); 1171EXPORT_SYMBOL_GPL(__clk_round_rate);
1111 1172
@@ -1126,7 +1187,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
1126 return 0; 1187 return 0;
1127 1188
1128 clk_prepare_lock(); 1189 clk_prepare_lock();
1129 ret = clk_core_round_rate_nolock(clk->core, rate); 1190 ret = __clk_round_rate(clk, rate);
1130 clk_prepare_unlock(); 1191 clk_prepare_unlock();
1131 1192
1132 return ret; 1193 return ret;
@@ -1517,6 +1578,8 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1517 struct clk_hw *parent_hw; 1578 struct clk_hw *parent_hw;
1518 unsigned long best_parent_rate = 0; 1579 unsigned long best_parent_rate = 0;
1519 unsigned long new_rate; 1580 unsigned long new_rate;
1581 unsigned long min_rate;
1582 unsigned long max_rate;
1520 int p_index = 0; 1583 int p_index = 0;
1521 1584
1522 /* sanity */ 1585 /* sanity */
@@ -1528,16 +1591,22 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1528 if (parent) 1591 if (parent)
1529 best_parent_rate = parent->rate; 1592 best_parent_rate = parent->rate;
1530 1593
1594 clk_core_get_boundaries(clk, &min_rate, &max_rate);
1595
1531 /* find the closest rate and parent clk/rate */ 1596 /* find the closest rate and parent clk/rate */
1532 if (clk->ops->determine_rate) { 1597 if (clk->ops->determine_rate) {
1533 parent_hw = parent ? parent->hw : NULL; 1598 parent_hw = parent ? parent->hw : NULL;
1534 new_rate = clk->ops->determine_rate(clk->hw, rate, 1599 new_rate = clk->ops->determine_rate(clk->hw, rate,
1600 min_rate,
1601 max_rate,
1535 &best_parent_rate, 1602 &best_parent_rate,
1536 &parent_hw); 1603 &parent_hw);
1537 parent = parent_hw ? parent_hw->core : NULL; 1604 parent = parent_hw ? parent_hw->core : NULL;
1538 } else if (clk->ops->round_rate) { 1605 } else if (clk->ops->round_rate) {
1539 new_rate = clk->ops->round_rate(clk->hw, rate, 1606 new_rate = clk->ops->round_rate(clk->hw, rate,
1540 &best_parent_rate); 1607 &best_parent_rate);
1608 if (new_rate < min_rate || new_rate > max_rate)
1609 return NULL;
1541 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) { 1610 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
1542 /* pass-through clock without adjustable parent */ 1611 /* pass-through clock without adjustable parent */
1543 clk->new_rate = clk->rate; 1612 clk->new_rate = clk->rate;
@@ -1675,6 +1744,45 @@ static void clk_change_rate(struct clk_core *clk)
1675 clk_change_rate(clk->new_child); 1744 clk_change_rate(clk->new_child);
1676} 1745}
1677 1746
1747static int clk_core_set_rate_nolock(struct clk_core *clk,
1748 unsigned long req_rate)
1749{
1750 struct clk_core *top, *fail_clk;
1751 unsigned long rate = req_rate;
1752 int ret = 0;
1753
1754 if (!clk)
1755 return 0;
1756
1757 /* bail early if nothing to do */
1758 if (rate == clk_core_get_rate_nolock(clk))
1759 return 0;
1760
1761 if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count)
1762 return -EBUSY;
1763
1764 /* calculate new rates and get the topmost changed clock */
1765 top = clk_calc_new_rates(clk, rate);
1766 if (!top)
1767 return -EINVAL;
1768
1769 /* notify that we are about to change rates */
1770 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1771 if (fail_clk) {
1772 pr_debug("%s: failed to set %s rate\n", __func__,
1773 fail_clk->name);
1774 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1775 return -EBUSY;
1776 }
1777
1778 /* change the rates */
1779 clk_change_rate(top);
1780
1781 clk->req_rate = req_rate;
1782
1783 return ret;
1784}
1785
1678/** 1786/**
1679 * clk_set_rate - specify a new rate for clk 1787 * clk_set_rate - specify a new rate for clk
1680 * @clk: the clk whose rate is being changed 1788 * @clk: the clk whose rate is being changed
@@ -1698,8 +1806,7 @@ static void clk_change_rate(struct clk_core *clk)
1698 */ 1806 */
1699int clk_set_rate(struct clk *clk, unsigned long rate) 1807int clk_set_rate(struct clk *clk, unsigned long rate)
1700{ 1808{
1701 struct clk_core *top, *fail_clk; 1809 int ret;
1702 int ret = 0;
1703 1810
1704 if (!clk) 1811 if (!clk)
1705 return 0; 1812 return 0;
@@ -1707,42 +1814,81 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
1707 /* prevent racing with updates to the clock topology */ 1814 /* prevent racing with updates to the clock topology */
1708 clk_prepare_lock(); 1815 clk_prepare_lock();
1709 1816
1710 /* bail early if nothing to do */ 1817 ret = clk_core_set_rate_nolock(clk->core, rate);
1711 if (rate == clk_get_rate(clk))
1712 goto out;
1713 1818
1714 if ((clk->core->flags & CLK_SET_RATE_GATE) && 1819 clk_prepare_unlock();
1715 clk->core->prepare_count) {
1716 ret = -EBUSY;
1717 goto out;
1718 }
1719 1820
1720 /* calculate new rates and get the topmost changed clock */ 1821 return ret;
1721 top = clk_calc_new_rates(clk->core, rate); 1822}
1722 if (!top) { 1823EXPORT_SYMBOL_GPL(clk_set_rate);
1723 ret = -EINVAL;
1724 goto out;
1725 }
1726 1824
1727 /* notify that we are about to change rates */ 1825/**
1728 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE); 1826 * clk_set_rate_range - set a rate range for a clock source
1729 if (fail_clk) { 1827 * @clk: clock source
1730 pr_debug("%s: failed to set %s rate\n", __func__, 1828 * @min: desired minimum clock rate in Hz, inclusive
1731 fail_clk->name); 1829 * @max: desired maximum clock rate in Hz, inclusive
1732 clk_propagate_rate_change(top, ABORT_RATE_CHANGE); 1830 *
1733 ret = -EBUSY; 1831 * Returns success (0) or negative errno.
1734 goto out; 1832 */
1833int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
1834{
1835 int ret = 0;
1836
1837 if (!clk)
1838 return 0;
1839
1840 if (min > max) {
1841 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1842 __func__, clk->core->name, clk->dev_id, clk->con_id,
1843 min, max);
1844 return -EINVAL;
1735 } 1845 }
1736 1846
1737 /* change the rates */ 1847 clk_prepare_lock();
1738 clk_change_rate(top); 1848
1849 if (min != clk->min_rate || max != clk->max_rate) {
1850 clk->min_rate = min;
1851 clk->max_rate = max;
1852 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
1853 }
1739 1854
1740out:
1741 clk_prepare_unlock(); 1855 clk_prepare_unlock();
1742 1856
1743 return ret; 1857 return ret;
1744} 1858}
1745EXPORT_SYMBOL_GPL(clk_set_rate); 1859EXPORT_SYMBOL_GPL(clk_set_rate_range);
1860
1861/**
1862 * clk_set_min_rate - set a minimum clock rate for a clock source
1863 * @clk: clock source
1864 * @rate: desired minimum clock rate in Hz, inclusive
1865 *
1866 * Returns success (0) or negative errno.
1867 */
1868int clk_set_min_rate(struct clk *clk, unsigned long rate)
1869{
1870 if (!clk)
1871 return 0;
1872
1873 return clk_set_rate_range(clk, rate, clk->max_rate);
1874}
1875EXPORT_SYMBOL_GPL(clk_set_min_rate);
1876
1877/**
1878 * clk_set_max_rate - set a maximum clock rate for a clock source
1879 * @clk: clock source
1880 * @rate: desired maximum clock rate in Hz, inclusive
1881 *
1882 * Returns success (0) or negative errno.
1883 */
1884int clk_set_max_rate(struct clk *clk, unsigned long rate)
1885{
1886 if (!clk)
1887 return 0;
1888
1889 return clk_set_rate_range(clk, clk->min_rate, rate);
1890}
1891EXPORT_SYMBOL_GPL(clk_set_max_rate);
1746 1892
1747/** 1893/**
1748 * clk_get_parent - return the parent of a clk 1894 * clk_get_parent - return the parent of a clk
@@ -2038,6 +2184,7 @@ static int __clk_init(struct device *dev, struct clk *clk_user)
2038 struct clk_core *orphan; 2184 struct clk_core *orphan;
2039 struct hlist_node *tmp2; 2185 struct hlist_node *tmp2;
2040 struct clk_core *clk; 2186 struct clk_core *clk;
2187 unsigned long rate;
2041 2188
2042 if (!clk_user) 2189 if (!clk_user)
2043 return -EINVAL; 2190 return -EINVAL;
@@ -2162,12 +2309,13 @@ static int __clk_init(struct device *dev, struct clk *clk_user)
2162 * then rate is set to zero. 2309 * then rate is set to zero.
2163 */ 2310 */
2164 if (clk->ops->recalc_rate) 2311 if (clk->ops->recalc_rate)
2165 clk->rate = clk->ops->recalc_rate(clk->hw, 2312 rate = clk->ops->recalc_rate(clk->hw,
2166 clk_core_get_rate_nolock(clk->parent)); 2313 clk_core_get_rate_nolock(clk->parent));
2167 else if (clk->parent) 2314 else if (clk->parent)
2168 clk->rate = clk->parent->rate; 2315 rate = clk->parent->rate;
2169 else 2316 else
2170 clk->rate = 0; 2317 rate = 0;
2318 clk->rate = clk->req_rate = rate;
2171 2319
2172 /* 2320 /*
2173 * walk the list of orphan clocks and reparent any that are children of 2321 * walk the list of orphan clocks and reparent any that are children of
@@ -2225,10 +2373,24 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2225 clk->core = hw->core; 2373 clk->core = hw->core;
2226 clk->dev_id = dev_id; 2374 clk->dev_id = dev_id;
2227 clk->con_id = con_id; 2375 clk->con_id = con_id;
2376 clk->max_rate = ULONG_MAX;
2377
2378 clk_prepare_lock();
2379 hlist_add_head(&clk->child_node, &hw->core->clks);
2380 clk_prepare_unlock();
2228 2381
2229 return clk; 2382 return clk;
2230} 2383}
2231 2384
2385static void __clk_free_clk(struct clk *clk)
2386{
2387 clk_prepare_lock();
2388 hlist_del(&clk->child_node);
2389 clk_prepare_unlock();
2390
2391 kfree(clk);
2392}
2393
2232/** 2394/**
2233 * clk_register - allocate a new clock, register it and return an opaque cookie 2395 * clk_register - allocate a new clock, register it and return an opaque cookie
2234 * @dev: device that is registering this clock 2396 * @dev: device that is registering this clock
@@ -2288,6 +2450,8 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
2288 } 2450 }
2289 } 2451 }
2290 2452
2453 INIT_HLIST_HEAD(&clk->clks);
2454
2291 hw->clk = __clk_create_clk(hw, NULL, NULL); 2455 hw->clk = __clk_create_clk(hw, NULL, NULL);
2292 if (IS_ERR(hw->clk)) { 2456 if (IS_ERR(hw->clk)) {
2293 pr_err("%s: could not allocate per-user clk\n", __func__); 2457 pr_err("%s: could not allocate per-user clk\n", __func__);
@@ -2299,8 +2463,9 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
2299 if (!ret) 2463 if (!ret)
2300 return hw->clk; 2464 return hw->clk;
2301 2465
2302 kfree(hw->clk); 2466 __clk_free_clk(hw->clk);
2303 hw->clk = NULL; 2467 hw->clk = NULL;
2468
2304fail_parent_names_copy: 2469fail_parent_names_copy:
2305 while (--i >= 0) 2470 while (--i >= 0)
2306 kfree(clk->parent_names[i]); 2471 kfree(clk->parent_names[i]);
@@ -2489,25 +2654,24 @@ int __clk_get(struct clk *clk)
2489 return 1; 2654 return 1;
2490} 2655}
2491 2656
2492static void clk_core_put(struct clk_core *core) 2657void __clk_put(struct clk *clk)
2493{ 2658{
2494 struct module *owner; 2659 struct module *owner;
2495 2660
2496 owner = core->owner; 2661 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2662 return;
2497 2663
2498 clk_prepare_lock(); 2664 clk_prepare_lock();
2499 kref_put(&core->ref, __clk_release); 2665
2666 hlist_del(&clk->child_node);
2667 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2668 owner = clk->core->owner;
2669 kref_put(&clk->core->ref, __clk_release);
2670
2500 clk_prepare_unlock(); 2671 clk_prepare_unlock();
2501 2672
2502 module_put(owner); 2673 module_put(owner);
2503}
2504
2505void __clk_put(struct clk *clk)
2506{
2507 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2508 return;
2509 2674
2510 clk_core_put(clk->core);
2511 kfree(clk); 2675 kfree(clk);
2512} 2676}
2513 2677
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 007144f81f50..2e4f6d432beb 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -295,6 +295,8 @@ static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
295} 295}
296 296
297static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate, 297static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
298 unsigned long min_rate,
299 unsigned long max_rate,
298 unsigned long *best_parent_rate, 300 unsigned long *best_parent_rate,
299 struct clk_hw **best_parent_p) 301 struct clk_hw **best_parent_p)
300{ 302{
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index 48fa53c7ce5e..de6a873175d2 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -202,6 +202,8 @@ error:
202} 202}
203 203
204static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate, 204static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
205 unsigned long min_rate,
206 unsigned long max_rate,
205 unsigned long *best_parent_rate, 207 unsigned long *best_parent_rate,
206 struct clk_hw **best_parent_clk) 208 struct clk_hw **best_parent_clk)
207{ 209{
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 60873a7f45d9..b4325f65a1bf 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -141,6 +141,7 @@ struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
141 141
142static long 142static long
143clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate, 143clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
144 unsigned long min_rate, unsigned long max_rate,
144 unsigned long *p_rate, struct clk_hw **p) 145 unsigned long *p_rate, struct clk_hw **p)
145{ 146{
146 struct clk_pll *pll = to_clk_pll(hw); 147 struct clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 0b93972c8807..0039bd7d3965 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -368,6 +368,7 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
368 368
369static long _freq_tbl_determine_rate(struct clk_hw *hw, 369static long _freq_tbl_determine_rate(struct clk_hw *hw,
370 const struct freq_tbl *f, unsigned long rate, 370 const struct freq_tbl *f, unsigned long rate,
371 unsigned long min_rate, unsigned long max_rate,
371 unsigned long *p_rate, struct clk_hw **p_hw) 372 unsigned long *p_rate, struct clk_hw **p_hw)
372{ 373{
373 unsigned long clk_flags; 374 unsigned long clk_flags;
@@ -397,22 +398,27 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
397} 398}
398 399
399static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, 400static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
401 unsigned long min_rate, unsigned long max_rate,
400 unsigned long *p_rate, struct clk_hw **p) 402 unsigned long *p_rate, struct clk_hw **p)
401{ 403{
402 struct clk_rcg *rcg = to_clk_rcg(hw); 404 struct clk_rcg *rcg = to_clk_rcg(hw);
403 405
404 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); 406 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
407 max_rate, p_rate, p);
405} 408}
406 409
407static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate, 410static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
411 unsigned long min_rate, unsigned long max_rate,
408 unsigned long *p_rate, struct clk_hw **p) 412 unsigned long *p_rate, struct clk_hw **p)
409{ 413{
410 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); 414 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
411 415
412 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); 416 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
417 max_rate, p_rate, p);
413} 418}
414 419
415static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate, 420static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long min_rate, unsigned long max_rate,
416 unsigned long *p_rate, struct clk_hw **p_hw) 422 unsigned long *p_rate, struct clk_hw **p_hw)
417{ 423{
418 struct clk_rcg *rcg = to_clk_rcg(hw); 424 struct clk_rcg *rcg = to_clk_rcg(hw);
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 08b8b3729f53..742acfa18d63 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -208,6 +208,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
208} 208}
209 209
210static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate, 210static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
211 unsigned long min_rate, unsigned long max_rate,
211 unsigned long *p_rate, struct clk_hw **p) 212 unsigned long *p_rate, struct clk_hw **p)
212{ 213{
213 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 214 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -361,6 +362,8 @@ static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
361} 362}
362 363
363static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, 364static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
365 unsigned long min_rate,
366 unsigned long max_rate,
364 unsigned long *p_rate, struct clk_hw **p) 367 unsigned long *p_rate, struct clk_hw **p)
365{ 368{
366 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 369 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -412,6 +415,7 @@ const struct clk_ops clk_edp_pixel_ops = {
412EXPORT_SYMBOL_GPL(clk_edp_pixel_ops); 415EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
413 416
414static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate, 417static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
418 unsigned long min_rate, unsigned long max_rate,
415 unsigned long *p_rate, struct clk_hw **p_hw) 419 unsigned long *p_rate, struct clk_hw **p_hw)
416{ 420{
417 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 421 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
@@ -476,6 +480,8 @@ static const struct frac_entry frac_table_pixel[] = {
476}; 480};
477 481
478static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate, 482static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
483 unsigned long min_rate,
484 unsigned long max_rate,
479 unsigned long *p_rate, struct clk_hw **p) 485 unsigned long *p_rate, struct clk_hw **p)
480{ 486{
481 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 487 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index a9ebbd207d58..8c20190a3e9f 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -80,6 +80,8 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
80} 80}
81 81
82static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate, 82static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
83 unsigned long min_rate,
84 unsigned long max_rate,
83 unsigned long *best_parent_rate, 85 unsigned long *best_parent_rate,
84 struct clk_hw **best_parent_p) 86 struct clk_hw **best_parent_p)
85{ 87{
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index 3d282fb8f85c..63cf149195ae 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -45,6 +45,8 @@ static unsigned long ar100_recalc_rate(struct clk_hw *hw,
45} 45}
46 46
47static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate, 47static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
48 unsigned long min_rate,
49 unsigned long max_rate,
48 unsigned long *best_parent_rate, 50 unsigned long *best_parent_rate,
49 struct clk_hw **best_parent_clk) 51 struct clk_hw **best_parent_clk)
50{ 52{
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 9b79f8907cc5..69937eaba795 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -119,6 +119,8 @@ static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
119} 119}
120 120
121static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate, 121static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
122 unsigned long min_rate,
123 unsigned long max_rate,
122 unsigned long *best_parent_rate, 124 unsigned long *best_parent_rate,
123 struct clk_hw **best_parent_clk) 125 struct clk_hw **best_parent_clk)
124{ 126{
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 12f13b0673af..17dd6e9439d1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -175,9 +175,12 @@ struct clk_ops {
175 unsigned long parent_rate); 175 unsigned long parent_rate);
176 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 176 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
177 unsigned long *parent_rate); 177 unsigned long *parent_rate);
178 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 178 long (*determine_rate)(struct clk_hw *hw,
179 unsigned long *best_parent_rate, 179 unsigned long rate,
180 struct clk_hw **best_parent_hw); 180 unsigned long min_rate,
181 unsigned long max_rate,
182 unsigned long *best_parent_rate,
183 struct clk_hw **best_parent_hw);
181 int (*set_parent)(struct clk_hw *hw, u8 index); 184 int (*set_parent)(struct clk_hw *hw, u8 index);
182 u8 (*get_parent)(struct clk_hw *hw); 185 u8 (*get_parent)(struct clk_hw *hw);
183 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 186 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -573,9 +576,17 @@ bool __clk_is_prepared(struct clk *clk);
573bool __clk_is_enabled(struct clk *clk); 576bool __clk_is_enabled(struct clk *clk);
574struct clk *__clk_lookup(const char *name); 577struct clk *__clk_lookup(const char *name);
575long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 578long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
579 unsigned long min_rate,
580 unsigned long max_rate,
576 unsigned long *best_parent_rate, 581 unsigned long *best_parent_rate,
577 struct clk_hw **best_parent_p); 582 struct clk_hw **best_parent_p);
583unsigned long __clk_determine_rate(struct clk_hw *core,
584 unsigned long rate,
585 unsigned long min_rate,
586 unsigned long max_rate);
578long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate, 587long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
588 unsigned long min_rate,
589 unsigned long max_rate,
579 unsigned long *best_parent_rate, 590 unsigned long *best_parent_rate,
580 struct clk_hw **best_parent_p); 591 struct clk_hw **best_parent_p);
581 592
diff --git a/include/linux/clk.h b/include/linux/clk.h
index ba7e9eda4347..8381bbfbc308 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -314,6 +314,34 @@ int clk_set_rate(struct clk *clk, unsigned long rate);
314bool clk_has_parent(struct clk *clk, struct clk *parent); 314bool clk_has_parent(struct clk *clk, struct clk *parent);
315 315
316/** 316/**
317 * clk_set_rate_range - set a rate range for a clock source
318 * @clk: clock source
319 * @min: desired minimum clock rate in Hz, inclusive
320 * @max: desired maximum clock rate in Hz, inclusive
321 *
322 * Returns success (0) or negative errno.
323 */
324int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
325
326/**
327 * clk_set_min_rate - set a minimum clock rate for a clock source
328 * @clk: clock source
329 * @rate: desired minimum clock rate in Hz, inclusive
330 *
331 * Returns success (0) or negative errno.
332 */
333int clk_set_min_rate(struct clk *clk, unsigned long rate);
334
335/**
336 * clk_set_max_rate - set a maximum clock rate for a clock source
337 * @clk: clock source
338 * @rate: desired maximum clock rate in Hz, inclusive
339 *
340 * Returns success (0) or negative errno.
341 */
342int clk_set_max_rate(struct clk *clk, unsigned long rate);
343
344/**
317 * clk_set_parent - set the parent clock source for this clock 345 * clk_set_parent - set the parent clock source for this clock
318 * @clk: clock source 346 * @clk: clock source
319 * @parent: parent clock source 347 * @parent: parent clock source
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 310122dcd9b5..0eac65054283 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -271,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
271 u8 index); 271 u8 index);
272long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 272long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
273 unsigned long rate, 273 unsigned long rate,
274 unsigned long min_rate,
275 unsigned long max_rate,
274 unsigned long *best_parent_rate, 276 unsigned long *best_parent_rate,
275 struct clk_hw **best_parent_clk); 277 struct clk_hw **best_parent_clk);
276unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 278unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
@@ -280,6 +282,8 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
280 unsigned long *parent_rate); 282 unsigned long *parent_rate);
281long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 283long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
282 unsigned long rate, 284 unsigned long rate,
285 unsigned long min_rate,
286 unsigned long max_rate,
283 unsigned long *best_parent_rate, 287 unsigned long *best_parent_rate,
284 struct clk_hw **best_parent_clk); 288 struct clk_hw **best_parent_clk);
285u8 omap2_init_dpll_parent(struct clk_hw *hw); 289u8 omap2_init_dpll_parent(struct clk_hw *hw);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 13:24:22 -0500