Merge branch 'clockevents/cmt-mtu2-tmu-cleanups' of git://git.linaro.org/people/daniel.lezcano/linux into cmt-mtu2-tmu-cleanups-for-v3.16

4 files changed, 1306 insertions, 680 deletions

diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 0b1836a6c539..bc8d025ce861 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -11,40 +11,93 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/err.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
 #include <linux/interrupt.h>
-#include <linux/ioport.h>
 #include <linux/io.h>
-#include <linux/clk.h>
+#include <linux/ioport.h>
 #include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/sh_timer.h>
-#include <linux/slab.h>
 #include <linux/module.h>
+#include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
+#include <linux/sh_timer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+struct sh_cmt_device;
+
+/*
+ * The CMT comes in 5 different identified flavours, depending not only on the
+ * SoC but also on the particular instance. The following table lists the main
+ * characteristics of those flavours.
+ *
+ *                      16B     32B     32B-F   48B     48B-2
+ * -----------------------------------------------------------------------------
+ * Channels             2       1/4     1       6       2/8
+ * Control Width        16      16      16      16      32
+ * Counter Width        16      32      32      32/48   32/48
+ * Shared Start/Stop    Y       Y       Y       Y       N
+ *
+ * The 48-bit gen2 version has a per-channel start/stop register located in the
+ * channel registers block. All other versions have a shared start/stop register
+ * located in the global space.
+ *
+ * Channels are indexed from 0 to N-1 in the documentation. The channel index
+ * infers the start/stop bit position in the control register and the channel
+ * registers block address. Some CMT instances have a subset of channels
+ * available, in which case the index in the documentation doesn't match the
+ * "real" index as implemented in hardware. This is for instance the case with
+ * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
+ * in the documentation but using start/stop bit 5 and having its registers
+ * block at 0x60.
+ *
+ * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
+ * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
+ */
+
+enum sh_cmt_model {
+        SH_CMT_16BIT,
+        SH_CMT_32BIT,
+        SH_CMT_32BIT_FAST,
+        SH_CMT_48BIT,
+        SH_CMT_48BIT_GEN2,
+};
+
+struct sh_cmt_info {
+        enum sh_cmt_model model;
 
-struct sh_cmt_priv {
-        void __iomem *mapbase;
-        void __iomem *mapbase_str;
-        struct clk *clk;
         unsigned long width; /* 16 or 32 bit version of hardware block */
         unsigned long overflow_bit;
         unsigned long clear_bits;
-        struct irqaction irqaction;
-        struct platform_device *pdev;
 
+        /* callbacks for CMSTR and CMCSR access */
+        unsigned long (*read_control)(void __iomem *base, unsigned long offs);
+        void (*write_control)(void __iomem *base, unsigned long offs,
+                              unsigned long value);
+
+        /* callbacks for CMCNT and CMCOR access */
+        unsigned long (*read_count)(void __iomem *base, unsigned long offs);
+        void (*write_count)(void __iomem *base, unsigned long offs,
+                            unsigned long value);
+};
+
+struct sh_cmt_channel {
+        struct sh_cmt_device *cmt;
+
+        unsigned int index;     /* Index in the documentation */
+        unsigned int hwidx;     /* Real hardware index */
+
+        void __iomem *iostart;
+        void __iomem *ioctrl;
+
+        unsigned int timer_bit;
         unsigned long flags;
         unsigned long match_value;
         unsigned long next_match_value;
@@ -55,38 +108,52 @@ struct sh_cmt_priv {
         struct clocksource cs;
         unsigned long total_cycles;
         bool cs_enabled;
+};
 
-        /* callbacks for CMSTR and CMCSR access */
-        unsigned long (*read_control)(void __iomem *base, unsigned long offs);
-        void (*write_control)(void __iomem *base, unsigned long offs,
-                              unsigned long value);
+struct sh_cmt_device {
+        struct platform_device *pdev;
 
-        /* callbacks for CMCNT and CMCOR access */
-        unsigned long (*read_count)(void __iomem *base, unsigned long offs);
-        void (*write_count)(void __iomem *base, unsigned long offs,
-                            unsigned long value);
+        const struct sh_cmt_info *info;
+        bool legacy;
+
+        void __iomem *mapbase_ch;
+        void __iomem *mapbase;
+        struct clk *clk;
+
+        struct sh_cmt_channel *channels;
+        unsigned int num_channels;
+
+        bool has_clockevent;
+        bool has_clocksource;
 };
 
-/* Examples of supported CMT timer register layouts and I/O access widths:
- *
- * "16-bit counter and 16-bit control" as found on sh7263:
- * CMSTR 0xfffec000 16-bit
- * CMCSR 0xfffec002 16-bit
- * CMCNT 0xfffec004 16-bit
- * CMCOR 0xfffec006 16-bit
- *
- * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
- * CMSTR 0xffca0000 16-bit
- * CMCSR 0xffca0060 16-bit
- * CMCNT 0xffca0064 32-bit
- * CMCOR 0xffca0068 32-bit
- *
- * "32-bit counter and 32-bit control" as found on r8a73a4 and r8a7790:
- * CMSTR 0xffca0500 32-bit
- * CMCSR 0xffca0510 32-bit
- * CMCNT 0xffca0514 32-bit
- * CMCOR 0xffca0518 32-bit
- */
+#define SH_CMT16_CMCSR_CMF              (1 << 7)
+#define SH_CMT16_CMCSR_CMIE             (1 << 6)
+#define SH_CMT16_CMCSR_CKS8             (0 << 0)
+#define SH_CMT16_CMCSR_CKS32            (1 << 0)
+#define SH_CMT16_CMCSR_CKS128           (2 << 0)
+#define SH_CMT16_CMCSR_CKS512           (3 << 0)
+#define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
+
+#define SH_CMT32_CMCSR_CMF              (1 << 15)
+#define SH_CMT32_CMCSR_OVF              (1 << 14)
+#define SH_CMT32_CMCSR_WRFLG            (1 << 13)
+#define SH_CMT32_CMCSR_STTF             (1 << 12)
+#define SH_CMT32_CMCSR_STPF             (1 << 11)
+#define SH_CMT32_CMCSR_SSIE             (1 << 10)
+#define SH_CMT32_CMCSR_CMS              (1 << 9)
+#define SH_CMT32_CMCSR_CMM              (1 << 8)
+#define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
+#define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
+#define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
+#define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)