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authorChris Wilson <chris@chris-wilson.co.uk>2012-04-17 10:31:27 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-04-18 07:19:51 -0400
commit1c293ea3b1d1c72f1fc5f398e03232d8d302bd23 (patch)
tree7ce98e815843da6c3ef6f900dd21487d8be8b091
parent69963e7c76743bd9e8ef559f955165dd85d9ba72 (diff)
drm/i915: Discard the unused obj->last_fenced_ring
As we now never pipeline a fence update, obj->last_fenced_ring is always the same as the obj->ring whenever obj->last_fenced_seqno is active, so remove it. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h5
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c16
2 files changed, 7 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6a504f997251..69e153956182 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -930,13 +930,12 @@ struct drm_i915_gem_object {
930 */ 930 */
931 uint32_t gtt_offset; 931 uint32_t gtt_offset;
932 932
933 /** Breadcrumb of last rendering to the buffer. */
934 uint32_t last_rendering_seqno;
935 struct intel_ring_buffer *ring; 933 struct intel_ring_buffer *ring;
936 934
935 /** Breadcrumb of last rendering to the buffer. */
936 uint32_t last_rendering_seqno;
937 /** Breadcrumb of last fenced GPU access to the buffer. */ 937 /** Breadcrumb of last fenced GPU access to the buffer. */
938 uint32_t last_fenced_seqno; 938 uint32_t last_fenced_seqno;
939 struct intel_ring_buffer *last_fenced_ring;
940 939
941 /** Current tiling stride for the object, if it's tiled. */ 940 /** Current tiling stride for the object, if it's tiled. */
942 uint32_t stride; 941 uint32_t stride;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3a091f55fbcc..b25d22971513 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1398,7 +1398,6 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1398 1398
1399 if (obj->fenced_gpu_access) { 1399 if (obj->fenced_gpu_access) {
1400 obj->last_fenced_seqno = seqno; 1400 obj->last_fenced_seqno = seqno;
1401 obj->last_fenced_ring = ring;
1402 1401
1403 /* Bump MRU to take account of the delayed flush */ 1402 /* Bump MRU to take account of the delayed flush */
1404 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1403 if (obj->fence_reg != I915_FENCE_REG_NONE) {
@@ -1445,7 +1444,6 @@ i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1445 BUG_ON(!list_empty(&obj->gpu_write_list)); 1444 BUG_ON(!list_empty(&obj->gpu_write_list));
1446 BUG_ON(!obj->active); 1445 BUG_ON(!obj->active);
1447 obj->ring = NULL; 1446 obj->ring = NULL;
1448 obj->last_fenced_ring = NULL;
1449 1447
1450 i915_gem_object_move_off_active(obj); 1448 i915_gem_object_move_off_active(obj);
1451 obj->fenced_gpu_access = false; 1449 obj->fenced_gpu_access = false;
@@ -1650,7 +1648,6 @@ static void i915_gem_reset_fences(struct drm_device *dev)
1650 reg->obj->fence_reg = I915_FENCE_REG_NONE; 1648 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1651 reg->obj->fenced_gpu_access = false; 1649 reg->obj->fenced_gpu_access = false;
1652 reg->obj->last_fenced_seqno = 0; 1650 reg->obj->last_fenced_seqno = 0;
1653 reg->obj->last_fenced_ring = NULL;
1654 i915_gem_clear_fence_reg(dev, reg); 1651 i915_gem_clear_fence_reg(dev, reg);
1655 } 1652 }
1656} 1653}
@@ -2295,7 +2292,7 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2295 2292
2296 if (obj->fenced_gpu_access) { 2293 if (obj->fenced_gpu_access) {
2297 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { 2294 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2298 ret = i915_gem_flush_ring(obj->last_fenced_ring, 2295 ret = i915_gem_flush_ring(obj->ring,
2299 0, obj->base.write_domain); 2296 0, obj->base.write_domain);
2300 if (ret) 2297 if (ret)
2301 return ret; 2298 return ret;
@@ -2304,10 +2301,10 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2304 obj->fenced_gpu_access = false; 2301 obj->fenced_gpu_access = false;
2305 } 2302 }
2306 2303
2307 if (obj->last_fenced_seqno && NULL != obj->last_fenced_ring) { 2304 if (obj->last_fenced_seqno) {
2308 if (!ring_passed_seqno(obj->last_fenced_ring, 2305 if (!ring_passed_seqno(obj->ring,
2309 obj->last_fenced_seqno)) { 2306 obj->last_fenced_seqno)) {
2310 ret = i915_wait_request(obj->last_fenced_ring, 2307 ret = i915_wait_request(obj->ring,
2311 obj->last_fenced_seqno, 2308 obj->last_fenced_seqno,
2312 true); 2309 true);
2313 if (ret) 2310 if (ret)
@@ -2315,7 +2312,6 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2315 } 2312 }
2316 2313
2317 obj->last_fenced_seqno = 0; 2314 obj->last_fenced_seqno = 0;
2318 obj->last_fenced_ring = NULL;
2319 } 2315 }
2320 2316
2321 /* Ensure that all CPU reads are completed before installing a fence 2317 /* Ensure that all CPU reads are completed before installing a fence
@@ -2382,7 +2378,7 @@ i915_find_fence_reg(struct drm_device *dev)
2382 if (first == NULL) 2378 if (first == NULL)
2383 first = reg; 2379 first = reg;
2384 2380
2385 if (reg->obj->last_fenced_ring == NULL) { 2381 if (reg->obj->last_fenced_seqno == 0) {
2386 avail = reg; 2382 avail = reg;
2387 break; 2383 break;
2388 } 2384 }
@@ -2458,7 +2454,6 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2458 } 2454 }
2459 2455
2460 old->fence_reg = I915_FENCE_REG_NONE; 2456 old->fence_reg = I915_FENCE_REG_NONE;
2461 old->last_fenced_ring = NULL;
2462 old->last_fenced_seqno = 0; 2457 old->last_fenced_seqno = 0;
2463 2458
2464 drm_gem_object_unreference(&old->base); 2459 drm_gem_object_unreference(&old->base);
@@ -2467,7 +2462,6 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2467 reg->obj = obj; 2462 reg->obj = obj;
2468 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list); 2463 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2469 obj->fence_reg = reg - dev_priv->fence_regs; 2464 obj->fence_reg = reg - dev_priv->fence_regs;
2470 obj->last_fenced_ring = NULL;
2471 2465
2472update: 2466update:
2473 obj->tiling_changed = false; 2467 obj->tiling_changed = false;