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authorJon Mason <mason@myri.com>2011-06-20 15:51:22 -0400
committerDavid S. Miller <davem@davemloft.net>2011-06-20 15:51:22 -0400
commit1b9c4134c126aa8ae00a57672d4a4eaecc436b54 (patch)
tree9dbddd98f0358b5285db4da047f58f06ba39981b
parentcf05c700cf6dd6f28bd95586d3040f809fd365f5 (diff)
myri_sbus: remove driver
Remove the myri_sbus driver. Why? * There is no possibility of ethernet mode on this adapter, so it's Myrinet only. * It won't inter-op with modern versions of Myrinet, and thus can only work with legacy adapters. * There are no in-kernel Linux drivers for the PCI version of this adapter, so it only can work on ~15 year old Sun hardware. It's long in the tooth, let's take it to the knackers. Signed-off-by: Jon Mason <mason@myri.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/Kconfig9
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/myri_sbus.c1187
-rw-r--r--drivers/net/myri_sbus.h311
4 files changed, 0 insertions, 1508 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 399cf4b28aef..f5919c28a4b8 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2196,15 +2196,6 @@ config IGBVF
2196 2196
2197source "drivers/net/ixp2000/Kconfig" 2197source "drivers/net/ixp2000/Kconfig"
2198 2198
2199config MYRI_SBUS
2200 tristate "MyriCOM Gigabit Ethernet support"
2201 depends on SBUS
2202 help
2203 This driver supports MyriCOM Sbus gigabit Ethernet cards.
2204
2205 To compile this driver as a module, choose M here: the module
2206 will be called myri_sbus. This is recommended.
2207
2208config NS83820 2199config NS83820
2209 tristate "National Semiconductor DP83820 support" 2200 tristate "National Semiconductor DP83820 support"
2210 depends on PCI 2201 depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 800684104b17..86f6c8d08407 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -59,7 +59,6 @@ obj-$(CONFIG_HAPPYMEAL) += sunhme.o
59obj-$(CONFIG_SUNLANCE) += sunlance.o 59obj-$(CONFIG_SUNLANCE) += sunlance.o
60obj-$(CONFIG_SUNQE) += sunqe.o 60obj-$(CONFIG_SUNQE) += sunqe.o
61obj-$(CONFIG_SUNBMAC) += sunbmac.o 61obj-$(CONFIG_SUNBMAC) += sunbmac.o
62obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
63obj-$(CONFIG_SUNGEM) += sungem.o sungem_phy.o 62obj-$(CONFIG_SUNGEM) += sungem.o sungem_phy.o
64obj-$(CONFIG_CASSINI) += cassini.o 63obj-$(CONFIG_CASSINI) += cassini.o
65obj-$(CONFIG_SUNVNET) += sunvnet.o 64obj-$(CONFIG_SUNVNET) += sunvnet.o
diff --git a/drivers/net/myri_sbus.c b/drivers/net/myri_sbus.c
deleted file mode 100644
index 53aeea4b536e..000000000000
--- a/drivers/net/myri_sbus.c
+++ /dev/null
@@ -1,1187 +0,0 @@
1/* myri_sbus.c: MyriCOM MyriNET SBUS card driver.
2 *
3 * Copyright (C) 1996, 1999, 2006, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6static char version[] =
7 "myri_sbus.c:v2.0 June 23, 2006 David S. Miller (davem@davemloft.net)\n";
8
9#include <linux/module.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/fcntl.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/in.h>
17#include <linux/string.h>
18#include <linux/delay.h>
19#include <linux/init.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/skbuff.h>
23#include <linux/bitops.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/firmware.h>
28#include <linux/gfp.h>
29
30#include <net/dst.h>
31#include <net/arp.h>
32#include <net/sock.h>
33#include <net/ipv6.h>
34
35#include <asm/system.h>
36#include <asm/io.h>
37#include <asm/dma.h>
38#include <asm/byteorder.h>
39#include <asm/idprom.h>
40#include <asm/openprom.h>
41#include <asm/oplib.h>
42#include <asm/auxio.h>
43#include <asm/pgtable.h>
44#include <asm/irq.h>
45
46#include "myri_sbus.h"
47
48/* #define DEBUG_DETECT */
49/* #define DEBUG_IRQ */
50/* #define DEBUG_TRANSMIT */
51/* #define DEBUG_RECEIVE */
52/* #define DEBUG_HEADER */
53
54#ifdef DEBUG_DETECT
55#define DET(x) printk x
56#else
57#define DET(x)
58#endif
59
60#ifdef DEBUG_IRQ
61#define DIRQ(x) printk x
62#else
63#define DIRQ(x)
64#endif
65
66#ifdef DEBUG_TRANSMIT
67#define DTX(x) printk x
68#else
69#define DTX(x)
70#endif
71
72#ifdef DEBUG_RECEIVE
73#define DRX(x) printk x
74#else
75#define DRX(x)
76#endif
77
78#ifdef DEBUG_HEADER
79#define DHDR(x) printk x
80#else
81#define DHDR(x)
82#endif
83
84/* Firmware name */
85#define FWNAME "myricom/lanai.bin"
86
87static void myri_reset_off(void __iomem *lp, void __iomem *cregs)
88{
89 /* Clear IRQ mask. */
90 sbus_writel(0, lp + LANAI_EIMASK);
91
92 /* Turn RESET function off. */
93 sbus_writel(CONTROL_ROFF, cregs + MYRICTRL_CTRL);
94}
95
96static void myri_reset_on(void __iomem *cregs)
97{
98 /* Enable RESET function. */
99 sbus_writel(CONTROL_RON, cregs + MYRICTRL_CTRL);
100
101 /* Disable IRQ's. */
102 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
103}
104
105static void myri_disable_irq(void __iomem *lp, void __iomem *cregs)
106{
107 sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
108 sbus_writel(0, lp + LANAI_EIMASK);
109 sbus_writel(ISTAT_HOST, lp + LANAI_ISTAT);
110}
111
112static void myri_enable_irq(void __iomem *lp, void __iomem *cregs)
113{
114 sbus_writel(CONTROL_EIRQ, cregs + MYRICTRL_CTRL);
115 sbus_writel(ISTAT_HOST, lp + LANAI_EIMASK);
116}
117
118static inline void bang_the_chip(struct myri_eth *mp)
119{
120 struct myri_shmem __iomem *shmem = mp->shmem;
121 void __iomem *cregs = mp->cregs;
122
123 sbus_writel(1, &shmem->send);
124 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
125}
126
127static int myri_do_handshake(struct myri_eth *mp)
128{
129 struct myri_shmem __iomem *shmem = mp->shmem;
130 void __iomem *cregs = mp->cregs;
131 struct myri_channel __iomem *chan = &shmem->channel;
132 int tick = 0;
133
134 DET(("myri_do_handshake: "));
135 if (sbus_readl(&chan->state) == STATE_READY) {
136 DET(("Already STATE_READY, failed.\n"));
137 return -1; /* We're hosed... */
138 }
139
140 myri_disable_irq(mp->lregs, cregs);
141
142 while (tick++ < 25) {
143 u32 softstate;
144
145 /* Wake it up. */
146 DET(("shakedown, CONTROL_WON, "));
147 sbus_writel(1, &shmem->shakedown);
148 sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
149
150 softstate = sbus_readl(&chan->state);
151 DET(("chanstate[%08x] ", softstate));
152 if (softstate == STATE_READY) {
153 DET(("wakeup successful, "));
154 break;
155 }
156
157 if (softstate != STATE_WFN) {
158 DET(("not WFN setting that, "));
159 sbus_writel(STATE_WFN, &chan->state);
160 }
161
162 udelay(20);
163 }
164
165 myri_enable_irq(mp->lregs, cregs);
166
167 if (tick > 25) {
168 DET(("25 ticks we lose, failure.\n"));
169 return -1;
170 }
171 DET(("success\n"));
172 return 0;
173}
174
175static int __devinit myri_load_lanai(struct myri_eth *mp)
176{
177 const struct firmware *fw;
178 struct net_device *dev = mp->dev;
179 struct myri_shmem __iomem *shmem = mp->shmem;
180 void __iomem *rptr;
181 int i, lanai4_data_size;
182
183 myri_disable_irq(mp->lregs, mp->cregs);
184 myri_reset_on(mp->cregs);
185
186 rptr = mp->lanai;
187 for (i = 0; i < mp->eeprom.ramsz; i++)
188 sbus_writeb(0, rptr + i);
189
190 if (mp->eeprom.cpuvers >= CPUVERS_3_0)
191 sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
192
193 i = request_firmware(&fw, FWNAME, &mp->myri_op->dev);
194 if (i) {
195 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
196 FWNAME, i);
197 return i;
198 }
199 if (fw->size < 2) {
200 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
201 fw->size, FWNAME);
202 release_firmware(fw);
203 return -EINVAL;
204 }
205 lanai4_data_size = fw->data[0] << 8 | fw->data[1];
206
207 /* Load executable code. */
208 for (i = 2; i < fw->size; i++)
209 sbus_writeb(fw->data[i], rptr++);
210
211 /* Load data segment. */
212 for (i = 0; i < lanai4_data_size; i++)
213 sbus_writeb(0, rptr++);
214
215 /* Set device address. */
216 sbus_writeb(0, &shmem->addr[0]);
217 sbus_writeb(0, &shmem->addr[1]);
218 for (i = 0; i < 6; i++)
219 sbus_writeb(dev->dev_addr[i],
220 &shmem->addr[i + 2]);
221
222 /* Set SBUS bursts and interrupt mask. */
223 sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
224 sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
225
226 /* Release the LANAI. */
227 myri_disable_irq(mp->lregs, mp->cregs);
228 myri_reset_off(mp->lregs, mp->cregs);
229 myri_disable_irq(mp->lregs, mp->cregs);
230
231 /* Wait for the reset to complete. */
232 for (i = 0; i < 5000; i++) {
233 if (sbus_readl(&shmem->channel.state) != STATE_READY)
234 break;
235 else
236 udelay(10);
237 }
238
239 if (i == 5000)
240 printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n");
241
242 i = myri_do_handshake(mp);
243 if (i)
244 printk(KERN_ERR "myricom: Handshake with LANAI failed.\n");
245
246 if (mp->eeprom.cpuvers == CPUVERS_4_0)
247 sbus_writel(0, mp->lregs + LANAI_VERS);
248
249 release_firmware(fw);
250 return i;
251}
252
253static void myri_clean_rings(struct myri_eth *mp)
254{
255 struct sendq __iomem *sq = mp->sq;
256 struct recvq __iomem *rq = mp->rq;
257 int i;
258
259 sbus_writel(0, &rq->tail);
260 sbus_writel(0, &rq->head);
261 for (i = 0; i < (RX_RING_SIZE+1); i++) {
262 if (mp->rx_skbs[i] != NULL) {
263 struct myri_rxd __iomem *rxd = &rq->myri_rxd[i];
264 u32 dma_addr;
265
266 dma_addr = sbus_readl(&rxd->myri_scatters[0].addr);
267 dma_unmap_single(&mp->myri_op->dev, dma_addr,
268 RX_ALLOC_SIZE, DMA_FROM_DEVICE);
269 dev_kfree_skb(mp->rx_skbs[i]);
270 mp->rx_skbs[i] = NULL;
271 }
272 }
273
274 mp->tx_old = 0;
275 sbus_writel(0, &sq->tail);
276 sbus_writel(0, &sq->head);
277 for (i = 0; i < TX_RING_SIZE; i++) {
278 if (mp->tx_skbs[i] != NULL) {
279 struct sk_buff *skb = mp->tx_skbs[i];
280 struct myri_txd __iomem *txd = &sq->myri_txd[i];
281 u32 dma_addr;
282
283 dma_addr = sbus_readl(&txd->myri_gathers[0].addr);
284 dma_unmap_single(&mp->myri_op->dev, dma_addr,
285 (skb->len + 3) & ~3,
286 DMA_TO_DEVICE);
287 dev_kfree_skb(mp->tx_skbs[i]);
288 mp->tx_skbs[i] = NULL;
289 }
290 }
291}
292
293static void myri_init_rings(struct myri_eth *mp, int from_irq)
294{
295 struct recvq __iomem *rq = mp->rq;
296 struct myri_rxd __iomem *rxd = &rq->myri_rxd[0];
297 struct net_device *dev = mp->dev;
298 gfp_t gfp_flags = GFP_KERNEL;
299 int i;
300
301 if (from_irq || in_interrupt())
302 gfp_flags = GFP_ATOMIC;
303
304 myri_clean_rings(mp);
305 for (i = 0; i < RX_RING_SIZE; i++) {
306 struct sk_buff *skb = myri_alloc_skb(RX_ALLOC_SIZE, gfp_flags);
307 u32 dma_addr;
308
309 if (!skb)
310 continue;
311 mp->rx_skbs[i] = skb;
312 skb->dev = dev;
313 skb_put(skb, RX_ALLOC_SIZE);
314
315 dma_addr = dma_map_single(&mp->myri_op->dev,
316 skb->data, RX_ALLOC_SIZE,
317 DMA_FROM_DEVICE);
318 sbus_writel(dma_addr, &rxd[i].myri_scatters[0].addr);
319 sbus_writel(RX_ALLOC_SIZE, &rxd[i].myri_scatters[0].len);
320 sbus_writel(i, &rxd[i].ctx);
321 sbus_writel(1, &rxd[i].num_sg);
322 }
323 sbus_writel(0, &rq->head);
324 sbus_writel(RX_RING_SIZE, &rq->tail);
325}
326
327static int myri_init(struct myri_eth *mp, int from_irq)
328{
329 myri_init_rings(mp, from_irq);
330 return 0;
331}
332
333static void myri_is_not_so_happy(struct myri_eth *mp)
334{
335}
336
337#ifdef DEBUG_HEADER
338static void dump_ehdr(struct ethhdr *ehdr)
339{
340 printk("ehdr[h_dst(%pM)"
341 "h_source(%pM)"
342 "h_proto(%04x)]\n",
343 ehdr->h_dest, ehdr->h_source, ehdr->h_proto);
344}
345
346static void dump_ehdr_and_myripad(unsigned char *stuff)
347{
348 struct ethhdr *ehdr = (struct ethhdr *) (stuff + 2);
349
350 printk("pad[%02x:%02x]", stuff[0], stuff[1]);
351 dump_ehdr(ehdr);
352}
353#endif
354
355static void myri_tx(struct myri_eth *mp, struct net_device *dev)
356{
357 struct sendq __iomem *sq= mp->sq;
358 int entry = mp->tx_old;
359 int limit = sbus_readl(&sq->head);
360
361 DTX(("entry[%d] limit[%d] ", entry, limit));
362 if (entry == limit)
363 return;
364 while (entry != limit) {
365 struct sk_buff *skb = mp->tx_skbs[entry];
366 u32 dma_addr;
367
368 DTX(("SKB[%d] ", entry));
369 dma_addr = sbus_readl(&sq->myri_txd[entry].myri_gathers[0].addr);
370 dma_unmap_single(&mp->myri_op->dev, dma_addr,
371 skb->len, DMA_TO_DEVICE);
372 dev_kfree_skb(skb);
373 mp->tx_skbs[entry] = NULL;
374 dev->stats.tx_packets++;
375 entry = NEXT_TX(entry);
376 }
377 mp->tx_old = entry;
378}
379
380/* Determine the packet's protocol ID. The rule here is that we
381 * assume 802.3 if the type field is short enough to be a length.
382 * This is normal practice and works for any 'now in use' protocol.
383 */
384static __be16 myri_type_trans(struct sk_buff *skb, struct net_device *dev)
385{
386 struct ethhdr *eth;
387 unsigned char *rawp;
388
389 skb_set_mac_header(skb, MYRI_PAD_LEN);
390 skb_pull(skb, dev->hard_header_len);
391 eth = eth_hdr(skb);
392
393#ifdef DEBUG_HEADER
394 DHDR(("myri_type_trans: "));
395 dump_ehdr(eth);
396#endif
397 if (*eth->h_dest & 1) {
398 if (memcmp(eth->h_dest, dev->broadcast, ETH_ALEN)==0)
399 skb->pkt_type = PACKET_BROADCAST;
400 else
401 skb->pkt_type = PACKET_MULTICAST;
402 } else if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) {
403 if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN))
404 skb->pkt_type = PACKET_OTHERHOST;
405 }
406
407 if (ntohs(eth->h_proto) >= 1536)
408 return eth->h_proto;
409
410 rawp = skb->data;
411
412 /* This is a magic hack to spot IPX packets. Older Novell breaks
413 * the protocol design and runs IPX over 802.3 without an 802.2 LLC
414 * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This
415 * won't work for fault tolerant netware but does for the rest.
416 */
417 if (*(unsigned short *)rawp == 0xFFFF)
418 return htons(ETH_P_802_3);
419
420 /* Real 802.2 LLC */
421 return htons(ETH_P_802_2);
422}
423
424static void myri_rx(struct myri_eth *mp, struct net_device *dev)
425{
426 struct recvq __iomem *rq = mp->rq;
427 struct recvq __iomem *rqa = mp->rqack;
428 int entry = sbus_readl(&rqa->head);
429 int limit = sbus_readl(&rqa->tail);
430 int drops;
431
432 DRX(("entry[%d] limit[%d] ", entry, limit));
433 if (entry == limit)
434 return;
435 drops = 0;
436 DRX(("\n"));
437 while (entry != limit) {
438 struct myri_rxd __iomem *rxdack = &rqa->myri_rxd[entry];
439 u32 csum = sbus_readl(&rxdack->csum);
440 int len = sbus_readl(&rxdack->myri_scatters[0].len);
441 int index = sbus_readl(&rxdack->ctx);
442 struct myri_rxd __iomem *rxd = &rq->myri_rxd[sbus_readl(&rq->tail)];
443 struct sk_buff *skb = mp->rx_skbs[index];
444
445 /* Ack it. */
446 sbus_writel(NEXT_RX(entry), &rqa->head);
447
448 /* Check for errors. */
449 DRX(("rxd[%d]: %p len[%d] csum[%08x] ", entry, rxd, len, csum));
450 dma_sync_single_for_cpu(&mp->myri_op->dev,
451 sbus_readl(&rxd->myri_scatters[0].addr),
452 RX_ALLOC_SIZE, DMA_FROM_DEVICE);
453 if (len < (ETH_HLEN + MYRI_PAD_LEN) || (skb->data[0] != MYRI_PAD_LEN)) {
454 DRX(("ERROR["));
455 dev->stats.rx_errors++;
456 if (len < (ETH_HLEN + MYRI_PAD_LEN)) {
457 DRX(("BAD_LENGTH] "));
458 dev->stats.rx_length_errors++;
459 } else {
460 DRX(("NO_PADDING] "));
461 dev->stats.rx_frame_errors++;
462 }
463
464 /* Return it to the LANAI. */
465 drop_it:
466 drops++;
467 DRX(("DROP "));
468 dev->stats.rx_dropped++;
469 dma_sync_single_for_device(&mp->myri_op->dev,
470 sbus_readl(&rxd->myri_scatters[0].addr),
471 RX_ALLOC_SIZE,
472 DMA_FROM_DEVICE);
473 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
474 sbus_writel(index, &rxd->ctx);
475 sbus_writel(1, &rxd->num_sg);
476 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
477 goto next;
478 }
479
480 DRX(("len[%d] ", len));
481 if (len > RX_COPY_THRESHOLD) {
482 struct sk_buff *new_skb;
483 u32 dma_addr;
484
485 DRX(("BIGBUFF "));
486 new_skb = myri_alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC);
487 if (new_skb == NULL) {
488 DRX(("skb_alloc(FAILED) "));
489 goto drop_it;
490 }
491 dma_unmap_single(&mp->myri_op->dev,
492 sbus_readl(&rxd->myri_scatters[0].addr),
493 RX_ALLOC_SIZE,
494 DMA_FROM_DEVICE);
495 mp->rx_skbs[index] = new_skb;
496 new_skb->dev = dev;
497 skb_put(new_skb, RX_ALLOC_SIZE);
498 dma_addr = dma_map_single(&mp->myri_op->dev,
499 new_skb->data,
500 RX_ALLOC_SIZE,
501 DMA_FROM_DEVICE);
502 sbus_writel(dma_addr, &rxd->myri_scatters[0].addr);
503 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
504 sbus_writel(index, &rxd->ctx);
505 sbus_writel(1, &rxd->num_sg);
506 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
507
508 /* Trim the original skb for the netif. */
509 DRX(("trim(%d) ", len));
510 skb_trim(skb, len);
511 } else {
512 struct sk_buff *copy_skb = dev_alloc_skb(len);
513
514 DRX(("SMALLBUFF "));
515 if (copy_skb == NULL) {
516 DRX(("dev_alloc_skb(FAILED) "));
517 goto drop_it;
518 }
519 /* DMA sync already done above. */
520 copy_skb->dev = dev;
521 DRX(("resv_and_put "));
522 skb_put(copy_skb, len);
523 skb_copy_from_linear_data(skb, copy_skb->data, len);
524
525 /* Reuse original ring buffer. */
526 DRX(("reuse "));
527 dma_sync_single_for_device(&mp->myri_op->dev,
528 sbus_readl(&rxd->myri_scatters[0].addr),
529 RX_ALLOC_SIZE,
530 DMA_FROM_DEVICE);
531 sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
532 sbus_writel(index, &rxd->ctx);
533 sbus_writel(1, &rxd->num_sg);
534 sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
535
536 skb = copy_skb;
537 }
538
539 /* Just like the happy meal we get checksums from this card. */
540 skb->csum = csum;
541 skb->ip_summed = CHECKSUM_UNNECESSARY; /* XXX */
542
543 skb->protocol = myri_type_trans(skb, dev);
544 DRX(("prot[%04x] netif_rx ", skb->protocol));
545 netif_rx(skb);
546
547 dev->stats.rx_packets++;
548 dev->stats.rx_bytes += len;
549 next:
550 DRX(("NEXT\n"));
551 entry = NEXT_RX(entry);
552 }
553}
554
555static irqreturn_t myri_interrupt(int irq, void *dev_id)
556{
557 struct net_device *dev = (struct net_device *) dev_id;
558 struct myri_eth *mp = netdev_priv(dev);
559 void __iomem *lregs = mp->lregs;
560 struct myri_channel __iomem *chan = &mp->shmem->channel;
561 unsigned long flags;
562 u32 status;
563 int handled = 0;
564
565 spin_lock_irqsave(&mp->irq_lock, flags);
566
567 status = sbus_readl(lregs + LANAI_ISTAT);
568 DIRQ(("myri_interrupt: status[%08x] ", status));
569 if (status & ISTAT_HOST) {
570 u32 softstate;
571
572 handled = 1;
573 DIRQ(("IRQ_DISAB "));
574 myri_disable_irq(lregs, mp->cregs);
575 softstate = sbus_readl(&chan->state);
576 DIRQ(("state[%08x] ", softstate));
577 if (softstate != STATE_READY) {
578 DIRQ(("myri_not_so_happy "));
579 myri_is_not_so_happy(mp);
580 }
581 DIRQ(("\nmyri_rx: "));
582 myri_rx(mp, dev);
583 DIRQ(("\nistat=ISTAT_HOST "));
584 sbus_writel(ISTAT_HOST, lregs + LANAI_ISTAT);
585 DIRQ(("IRQ_ENAB "));
586 myri_enable_irq(lregs, mp->cregs);
587 }
588 DIRQ(("\n"));
589
590 spin_unlock_irqrestore(&mp->irq_lock, flags);
591
592 return IRQ_RETVAL(handled);
593}
594
595static int myri_open(struct net_device *dev)
596{
597 struct myri_eth *mp = netdev_priv(dev);
598
599 return myri_init(mp, in_interrupt());
600}
601
602static int myri_close(struct net_device *dev)
603{
604 struct myri_eth *mp = netdev_priv(dev);
605
606 myri_clean_rings(mp);
607 return 0;
608}
609
610static void myri_tx_timeout(struct net_device *dev)
611{
612 struct myri_eth *mp = netdev_priv(dev);
613
614 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
615
616 dev->stats.tx_errors++;
617 myri_init(mp, 0);
618 netif_wake_queue(dev);
619}
620
621static int myri_start_xmit(struct sk_buff *skb, struct net_device *dev)
622{
623 struct myri_eth *mp = netdev_priv(dev);
624 struct sendq __iomem *sq = mp->sq;
625 struct myri_txd __iomem *txd;
626 unsigned long flags;
627 unsigned int head, tail;
628 int len, entry;
629 u32 dma_addr;
630
631 DTX(("myri_start_xmit: "));
632
633 myri_tx(mp, dev);
634
635 netif_stop_queue(dev);
636
637 /* This is just to prevent multiple PIO reads for TX_BUFFS_AVAIL. */
638 head = sbus_readl(&sq->head);
639 tail = sbus_readl(&sq->tail);
640
641 if (!TX_BUFFS_AVAIL(head, tail)) {
642 DTX(("no buffs available, returning 1\n"));
643 return NETDEV_TX_BUSY;
644 }
645
646 spin_lock_irqsave(&mp->irq_lock, flags);
647
648 DHDR(("xmit[skbdata(%p)]\n", skb->data));
649#ifdef DEBUG_HEADER
650 dump_ehdr_and_myripad(((unsigned char *) skb->data));
651#endif
652
653 /* XXX Maybe this can go as well. */
654 len = skb->len;
655 if (len & 3) {
656 DTX(("len&3 "));
657 len = (len + 4) & (~3);
658 }
659
660 entry = sbus_readl(&sq->tail);
661
662 txd = &sq->myri_txd[entry];
663 mp->tx_skbs[entry] = skb;
664
665 /* Must do this before we sbus map it. */
666 if (skb->data[MYRI_PAD_LEN] & 0x1) {
667 sbus_writew(0xffff, &txd->addr[0]);
668 sbus_writew(0xffff, &txd->addr[1]);
669 sbus_writew(0xffff, &txd->addr[2]);
670 sbus_writew(0xffff, &txd->addr[3]);
671 } else {
672 sbus_writew(0xffff, &txd->addr[0]);
673 sbus_writew((skb->data[0] << 8) | skb->data[1], &txd->addr[1]);
674 sbus_writew((skb->data[2] << 8) | skb->data[3], &txd->addr[2]);
675 sbus_writew((skb->data[4] << 8) | skb->data[5], &txd->addr[3]);
676 }
677
678 dma_addr = dma_map_single(&mp->myri_op->dev, skb->data,
679 len, DMA_TO_DEVICE);
680 sbus_writel(dma_addr, &txd->myri_gathers[0].addr);
681 sbus_writel(len, &txd->myri_gathers[0].len);
682 sbus_writel(1, &txd->num_sg);
683 sbus_writel(KERNEL_CHANNEL, &txd->chan);
684 sbus_writel(len, &txd->len);
685 sbus_writel((u32)-1, &txd->csum_off);
686 sbus_writel(0, &txd->csum_field);
687
688 sbus_writel(NEXT_TX(entry), &sq->tail);
689 DTX(("BangTheChip "));
690 bang_the_chip(mp);
691
692 DTX(("tbusy=0, returning 0\n"));
693 netif_start_queue(dev);
694 spin_unlock_irqrestore(&mp->irq_lock, flags);
695 return NETDEV_TX_OK;
696}
697
698/* Create the MyriNet MAC header for an arbitrary protocol layer
699 *
700 * saddr=NULL means use device source address
701 * daddr=NULL means leave destination address (eg unresolved arp)
702 */
703static int myri_header(struct sk_buff *skb, struct net_device *dev,
704 unsigned short type, const void *daddr,
705 const void *saddr, unsigned len)
706{
707 struct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN);
708 unsigned char *pad = (unsigned char *) skb_push(skb, MYRI_PAD_LEN);
709
710#ifdef DEBUG_HEADER
711 DHDR(("myri_header: pad[%02x,%02x] ", pad[0], pad[1]));
712 dump_ehdr(eth);
713#endif
714
715 /* Set the MyriNET padding identifier. */
716 pad[0] = MYRI_PAD_LEN;
717 pad[1] = 0xab;
718
719 /* Set the protocol type. For a packet of type ETH_P_802_3/2 we put the
720 * length in here instead.
721 */
722 if (type != ETH_P_802_3 && type != ETH_P_802_2)
723 eth->h_proto = htons(type);
724 else
725 eth->h_proto = htons(len);
726
727 /* Set the source hardware address. */
728 if (saddr)
729 memcpy(eth->h_source, saddr, dev->addr_len);
730 else
731 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
732
733 /* Anyway, the loopback-device should never use this function... */
734 if (dev->flags & IFF_LOOPBACK) {
735 int i;
736 for (i = 0; i < dev->addr_len; i++)
737 eth->h_dest[i] = 0;
738 return dev->hard_header_len;
739 }
740
741 if (daddr) {
742 memcpy(eth->h_dest, daddr, dev->addr_len);
743 return dev->hard_header_len;
744 }
745 return -dev->hard_header_len;
746}
747
748/* Rebuild the MyriNet MAC header. This is called after an ARP
749 * (or in future other address resolution) has completed on this
750 * sk_buff. We now let ARP fill in the other fields.
751 */
752static int myri_rebuild_header(struct sk_buff *skb)
753{
754 unsigned char *pad = (unsigned char *) skb->data;
755 struct ethhdr *eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
756 struct net_device *dev = skb->dev;
757
758#ifdef DEBUG_HEADER
759 DHDR(("myri_rebuild_header: pad[%02x,%02x] ", pad[0], pad[1]));
760 dump_ehdr(eth);
761#endif
762
763 /* Refill MyriNet padding identifiers, this is just being anal. */
764 pad[0] = MYRI_PAD_LEN;
765 pad[1] = 0xab;
766
767 switch (eth->h_proto)
768 {
769#ifdef CONFIG_INET
770 case cpu_to_be16(ETH_P_IP):
771 return arp_find(eth->h_dest, skb);
772#endif
773
774 default:
775 printk(KERN_DEBUG
776 "%s: unable to resolve type %X addresses.\n",
777 dev->name, (int)eth->h_proto);
778
779 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
780 return 0;
781 break;
782 }
783
784 return 0;
785}
786
787static int myri_header_cache(const struct neighbour *neigh, struct hh_cache *hh)
788{
789 unsigned short type = hh->hh_type;
790 unsigned char *pad;
791 struct ethhdr *eth;
792 const struct net_device *dev = neigh->dev;
793
794 pad = ((unsigned char *) hh->hh_data) +
795 HH_DATA_OFF(sizeof(*eth) + MYRI_PAD_LEN);
796 eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
797
798 if (type == htons(ETH_P_802_3))
799 return -1;
800
801 /* Refill MyriNet padding identifiers, this is just being anal. */
802 pad[0] = MYRI_PAD_LEN;
803 pad[1] = 0xab;
804
805 eth->h_proto = type;
806 memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
807 memcpy(eth->h_dest, neigh->ha, dev->addr_len);
808 hh->hh_len = 16;
809 return 0;
810}
811
812
813/* Called by Address Resolution module to notify changes in address. */
814void myri_header_cache_update(struct hh_cache *hh,
815 const struct net_device *dev,
816 const unsigned char * haddr)
817{
818 memcpy(((u8*)hh->hh_data) + HH_DATA_OFF(sizeof(struct ethhdr)),
819 haddr, dev->addr_len);
820}
821
822static int myri_change_mtu(struct net_device *dev, int new_mtu)
823{
824 if ((new_mtu < (ETH_HLEN + MYRI_PAD_LEN)) || (new_mtu > MYRINET_MTU))
825 return -EINVAL;
826 dev->mtu = new_mtu;
827 return 0;
828}
829
830static void myri_set_multicast(struct net_device *dev)
831{
832 /* Do nothing, all MyriCOM nodes transmit multicast frames
833 * as broadcast packets...
834 */
835}
836
837static inline void set_boardid_from_idprom(struct myri_eth *mp, int num)
838{
839 mp->eeprom.id[0] = 0;
840 mp->eeprom.id[1] = idprom->id_machtype;
841 mp->eeprom.id[2] = (idprom->id_sernum >> 16) & 0xff;
842 mp->eeprom.id[3] = (idprom->id_sernum >> 8) & 0xff;
843 mp->eeprom.id[4] = (idprom->id_sernum >> 0) & 0xff;
844 mp->eeprom.id[5] = num;
845}
846
847static inline void determine_reg_space_size(struct myri_eth *mp)
848{
849 switch(mp->eeprom.cpuvers) {
850 case CPUVERS_2_3:
851 case CPUVERS_3_0:
852 case CPUVERS_3_1:
853 case CPUVERS_3_2:
854 mp->reg_size = (3 * 128 * 1024) + 4096;
855 break;
856
857 case CPUVERS_4_0:
858 case CPUVERS_4_1:
859 mp->reg_size = ((4096<<1) + mp->eeprom.ramsz);
860 break;
861
862 case CPUVERS_4_2:
863 case CPUVERS_5_0:
864 default:
865 printk("myricom: AIEEE weird cpu version %04x assuming pre4.0\n",
866 mp->eeprom.cpuvers);
867 mp->reg_size = (3 * 128 * 1024) + 4096;
868 }
869}
870
871#ifdef DEBUG_DETECT
872static void dump_eeprom(struct myri_eth *mp)
873{
874 printk("EEPROM: clockval[%08x] cpuvers[%04x] "
875 "id[%02x,%02x,%02x,%02x,%02x,%02x]\n",
876 mp->eeprom.cval, mp->eeprom.cpuvers,
877 mp->eeprom.id[0], mp->eeprom.id[1], mp->eeprom.id[2],
878 mp->eeprom.id[3], mp->eeprom.id[4], mp->eeprom.id[5]);
879 printk("EEPROM: ramsz[%08x]\n", mp->eeprom.ramsz);
880 printk("EEPROM: fvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
881 mp->eeprom.fvers[0], mp->eeprom.fvers[1], mp->eeprom.fvers[2],
882 mp->eeprom.fvers[3], mp->eeprom.fvers[4], mp->eeprom.fvers[5],
883 mp->eeprom.fvers[6], mp->eeprom.fvers[7]);
884 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
885 mp->eeprom.fvers[8], mp->eeprom.fvers[9], mp->eeprom.fvers[10],
886 mp->eeprom.fvers[11], mp->eeprom.fvers[12], mp->eeprom.fvers[13],
887 mp->eeprom.fvers[14], mp->eeprom.fvers[15]);
888 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
889 mp->eeprom.fvers[16], mp->eeprom.fvers[17], mp->eeprom.fvers[18],
890 mp->eeprom.fvers[19], mp->eeprom.fvers[20], mp->eeprom.fvers[21],
891 mp->eeprom.fvers[22], mp->eeprom.fvers[23]);
892 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
893 mp->eeprom.fvers[24], mp->eeprom.fvers[25], mp->eeprom.fvers[26],
894 mp->eeprom.fvers[27], mp->eeprom.fvers[28], mp->eeprom.fvers[29],
895 mp->eeprom.fvers[30], mp->eeprom.fvers[31]);
896 printk("EEPROM: mvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
897 mp->eeprom.mvers[0], mp->eeprom.mvers[1], mp->eeprom.mvers[2],
898 mp->eeprom.mvers[3], mp->eeprom.mvers[4], mp->eeprom.mvers[5],
899 mp->eeprom.mvers[6], mp->eeprom.mvers[7]);
900 printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
901 mp->eeprom.mvers[8], mp->eeprom.mvers[9], mp->eeprom.mvers[10],
902 mp->eeprom.mvers[11], mp->eeprom.mvers[12], mp->eeprom.mvers[13],
903 mp->eeprom.mvers[14], mp->eeprom.mvers[15]);
904 printk("EEPROM: dlval[%04x] brd_type[%04x] bus_type[%04x] prod_code[%04x]\n",
905 mp->eeprom.dlval, mp->eeprom.brd_type, mp->eeprom.bus_type,
906 mp->eeprom.prod_code);
907 printk("EEPROM: serial_num[%08x]\n", mp->eeprom.serial_num);
908}
909#endif
910
911static const struct header_ops myri_header_ops = {
912 .create = myri_header,
913 .rebuild = myri_rebuild_header,
914 .cache = myri_header_cache,
915 .cache_update = myri_header_cache_update,
916};
917
918static const struct net_device_ops myri_ops = {
919 .ndo_open = myri_open,
920 .ndo_stop = myri_close,
921 .ndo_start_xmit = myri_start_xmit,
922 .ndo_set_multicast_list = myri_set_multicast,
923 .ndo_tx_timeout = myri_tx_timeout,
924 .ndo_change_mtu = myri_change_mtu,
925 .ndo_set_mac_address = eth_mac_addr,
926 .ndo_validate_addr = eth_validate_addr,
927};
928
929static int __devinit myri_sbus_probe(struct platform_device *op)
930{
931 struct device_node *dp = op->dev.of_node;
932 static unsigned version_printed;
933 struct net_device *dev;
934 struct myri_eth *mp;
935 const void *prop;
936 static int num;
937 int i, len;
938
939 DET(("myri_ether_init(%p,%d):\n", op, num));
940 dev = alloc_etherdev(sizeof(struct myri_eth));
941 if (!dev)
942 return -ENOMEM;
943
944 if (version_printed++ == 0)
945 printk(version);
946
947 SET_NETDEV_DEV(dev, &op->dev);
948
949 mp = netdev_priv(dev);
950 spin_lock_init(&mp->irq_lock);
951 mp->myri_op = op;
952
953 /* Clean out skb arrays. */
954 for (i = 0; i < (RX_RING_SIZE + 1); i++)
955 mp->rx_skbs[i] = NULL;
956
957 for (i = 0; i < TX_RING_SIZE; i++)
958 mp->tx_skbs[i] = NULL;
959
960 /* First check for EEPROM information. */
961 prop = of_get_property(dp, "myrinet-eeprom-info", &len);
962
963 if (prop)
964 memcpy(&mp->eeprom, prop, sizeof(struct myri_eeprom));
965 if (!prop) {
966 /* No eeprom property, must cook up the values ourselves. */
967 DET(("No EEPROM: "));
968 mp->eeprom.bus_type = BUS_TYPE_SBUS;
969 mp->eeprom.cpuvers =
970 of_getintprop_default(dp, "cpu_version", 0);
971 mp->eeprom.cval =
972 of_getintprop_default(dp, "clock_value", 0);
973 mp->eeprom.ramsz = of_getintprop_default(dp, "sram_size", 0);
974 if (!mp->eeprom.cpuvers)
975 mp->eeprom.cpuvers = CPUVERS_2_3;
976 if (mp->eeprom.cpuvers < CPUVERS_3_0)
977 mp->eeprom.cval = 0;
978 if (!mp->eeprom.ramsz)
979 mp->eeprom.ramsz = (128 * 1024);
980
981 prop = of_get_property(dp, "myrinet-board-id", &len);
982 if (prop)
983 memcpy(&mp->eeprom.id[0], prop, 6);
984 else
985 set_boardid_from_idprom(mp, num);
986
987 prop = of_get_property(dp, "fpga_version", &len);
988 if (prop)
989 memcpy(&mp->eeprom.fvers[0], prop, 32);
990 else
991 memset(&mp->eeprom.fvers[0], 0, 32);
992
993 if (mp->eeprom.cpuvers == CPUVERS_4_1) {
994 if (mp->eeprom.ramsz == (128 * 1024))
995 mp->eeprom.ramsz = (256 * 1024);
996 if ((mp->eeprom.cval == 0x40414041) ||
997 (mp->eeprom.cval == 0x90449044))
998 mp->eeprom.cval = 0x50e450e4;
999 }
1000 }
1001#ifdef DEBUG_DETECT
1002 dump_eeprom(mp);
1003#endif
1004
1005 for (i = 0; i < 6; i++)
1006 dev->dev_addr[i] = mp->eeprom.id[i];
1007
1008 determine_reg_space_size(mp);
1009
1010 /* Map in the MyriCOM register/localram set. */
1011 if (mp->eeprom.cpuvers < CPUVERS_4_0) {
1012 /* XXX Makes no sense, if control reg is non-existent this
1013 * XXX driver cannot function at all... maybe pre-4.0 is
1014 * XXX only a valid version for PCI cards? Ask feldy...
1015 */
1016 DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
1017 mp->regs = of_ioremap(&op->resource[0], 0,
1018 mp->reg_size, "MyriCOM Regs");
1019 if (!mp->regs) {
1020 printk("MyriCOM: Cannot map MyriCOM registers.\n");
1021 goto err;
1022 }
1023 mp->lanai = mp->regs + (256 * 1024);
1024 mp->lregs = mp->lanai + (0x10000 * 2);
1025 } else {
1026 DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
1027 mp->cregs = of_ioremap(&op->resource[0], 0,
1028 PAGE_SIZE, "MyriCOM Control Regs");
1029 mp->lregs = of_ioremap(&op->resource[0], (256 * 1024),
1030 PAGE_SIZE, "MyriCOM LANAI Regs");
1031 mp->lanai = of_ioremap(&op->resource[0], (512 * 1024),
1032 mp->eeprom.ramsz, "MyriCOM SRAM");
1033 }
1034 DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n",
1035 mp->cregs, mp->lregs, mp->lanai));
1036
1037 if (mp->eeprom.cpuvers >= CPUVERS_4_0)
1038 mp->shmem_base = 0xf000;
1039 else
1040 mp->shmem_base = 0x8000;
1041
1042 DET(("Shared memory base is %04x, ", mp->shmem_base));
1043
1044 mp->shmem = (struct myri_shmem __iomem *)
1045 (mp->lanai + (mp->shmem_base * 2));
1046 DET(("shmem mapped at %p\n", mp->shmem));
1047
1048 mp->rqack = &mp->shmem->channel.recvqa;
1049 mp->rq = &mp->shmem->channel.recvq;
1050 mp->sq = &mp->shmem->channel.sendq;
1051
1052 /* Reset the board. */
1053 DET(("Resetting LANAI\n"));
1054 myri_reset_off(mp->lregs, mp->cregs);
1055 myri_reset_on(mp->cregs);
1056
1057 /* Turn IRQ's off. */
1058 myri_disable_irq(mp->lregs, mp->cregs);
1059
1060 /* Reset once more. */
1061 myri_reset_on(mp->cregs);
1062
1063 /* Get the supported DVMA burst sizes from our SBUS. */
1064 mp->myri_bursts = of_getintprop_default(dp->parent,
1065 "burst-sizes", 0x00);
1066 if (!sbus_can_burst64())
1067 mp->myri_bursts &= ~(DMA_BURST64);
1068
1069 DET(("MYRI bursts %02x\n", mp->myri_bursts));
1070
1071 /* Encode SBUS interrupt level in second control register. */
1072 i = of_getintprop_default(dp, "interrupts", 0);
1073 if (i == 0)
1074 i = 4;
1075 DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
1076 i, (1 << i)));
1077
1078 sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
1079
1080 mp->dev = dev;
1081 dev->watchdog_timeo = 5*HZ;
1082 dev->irq = op->archdata.irqs[0];
1083 dev->netdev_ops = &myri_ops;
1084
1085 /* Register interrupt handler now. */
1086 DET(("Requesting MYRIcom IRQ line.\n"));
1087 if (request_irq(dev->irq, myri_interrupt,
1088 IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) {
1089 printk("MyriCOM: Cannot register interrupt handler.\n");
1090 goto err;
1091 }
1092
1093 dev->mtu = MYRINET_MTU;
1094 dev->header_ops = &myri_header_ops;
1095
1096 dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
1097
1098 /* Load code onto the LANai. */
1099 DET(("Loading LANAI firmware\n"));
1100 if (myri_load_lanai(mp)) {
1101 printk(KERN_ERR "MyriCOM: Cannot Load LANAI firmware.\n");
1102 goto err_free_irq;
1103 }
1104
1105 if (register_netdev(dev)) {
1106 printk("MyriCOM: Cannot register device.\n");
1107 goto err_free_irq;
1108 }
1109
1110 dev_set_drvdata(&op->dev, mp);
1111
1112 num++;
1113
1114 printk("%s: MyriCOM MyriNET Ethernet %pM\n",
1115 dev->name, dev->dev_addr);
1116
1117 return 0;
1118
1119err_free_irq:
1120 free_irq(dev->irq, dev);
1121err:
1122 /* This will also free the co-allocated private data*/
1123 free_netdev(dev);
1124 return -ENODEV;
1125}
1126
1127static int __devexit myri_sbus_remove(struct platform_device *op)
1128{
1129 struct myri_eth *mp = dev_get_drvdata(&op->dev);
1130 struct net_device *net_dev = mp->dev;
1131
1132 unregister_netdev(net_dev);
1133
1134 free_irq(net_dev->irq, net_dev);
1135
1136 if (mp->eeprom.cpuvers < CPUVERS_4_0) {
1137 of_iounmap(&op->resource[0], mp->regs, mp->reg_size);
1138 } else {
1139 of_iounmap(&op->resource[0], mp->cregs, PAGE_SIZE);
1140 of_iounmap(&op->resource[0], mp->lregs, (256 * 1024));
1141 of_iounmap(&op->resource[0], mp->lanai, (512 * 1024));
1142 }
1143
1144 free_netdev(net_dev);
1145
1146 dev_set_drvdata(&op->dev, NULL);
1147
1148 return 0;
1149}
1150
1151static const struct of_device_id myri_sbus_match[] = {
1152 {
1153 .name = "MYRICOM,mlanai",
1154 },
1155 {
1156 .name = "myri",
1157 },
1158 {},
1159};
1160
1161MODULE_DEVICE_TABLE(of, myri_sbus_match);
1162
1163static struct platform_driver myri_sbus_driver = {
1164 .driver = {
1165 .name = "myri",
1166 .owner = THIS_MODULE,
1167 .of_match_table = myri_sbus_match,
1168 },
1169 .probe = myri_sbus_probe,
1170 .remove = __devexit_p(myri_sbus_remove),
1171};
1172
1173static int __init myri_sbus_init(void)
1174{
1175 return platform_driver_register(&myri_sbus_driver);
1176}
1177
1178static void __exit myri_sbus_exit(void)
1179{
1180 platform_driver_unregister(&myri_sbus_driver);
1181}
1182
1183module_init(myri_sbus_init);
1184module_exit(myri_sbus_exit);
1185
1186MODULE_LICENSE("GPL");
1187MODULE_FIRMWARE(FWNAME);
diff --git a/drivers/net/myri_sbus.h b/drivers/net/myri_sbus.h
deleted file mode 100644
index 80a2fa5cf757..000000000000
--- a/drivers/net/myri_sbus.h
+++ /dev/null
@@ -1,311 +0,0 @@
1/* myri_sbus.h: Defines for MyriCOM MyriNET SBUS card driver.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6#ifndef _MYRI_SBUS_H
7#define _MYRI_SBUS_H
8
9/* LANAI Registers */
10#define LANAI_IPF0 0x00UL /* Context zero state registers.*/
11#define LANAI_CUR0 0x04UL
12#define LANAI_PREV0 0x08UL
13#define LANAI_DATA0 0x0cUL
14#define LANAI_DPF0 0x10UL
15#define LANAI_IPF1 0x14UL /* Context one state registers. */
16#define LANAI_CUR1 0x18UL
17#define LANAI_PREV1 0x1cUL
18#define LANAI_DATA1 0x20UL
19#define LANAI_DPF1 0x24UL
20#define LANAI_ISTAT 0x28UL /* Interrupt status. */
21#define LANAI_EIMASK 0x2cUL /* External IRQ mask. */
22#define LANAI_ITIMER 0x30UL /* IRQ timer. */
23#define LANAI_RTC 0x34UL /* Real Time Clock */
24#define LANAI_CSUM 0x38UL /* Checksum. */
25#define LANAI_DMAXADDR 0x3cUL /* SBUS DMA external address. */
26#define LANAI_DMALADDR 0x40UL /* SBUS DMA local address. */
27#define LANAI_DMACTR 0x44UL /* SBUS DMA counter. */
28#define LANAI_RXDMAPTR 0x48UL /* Receive DMA pointer. */
29#define LANAI_RXDMALIM 0x4cUL /* Receive DMA limit. */
30#define LANAI_TXDMAPTR 0x50UL /* Transmit DMA pointer. */
31#define LANAI_TXDMALIM 0x54UL /* Transmit DMA limit. */
32#define LANAI_TXDMALIMT 0x58UL /* Transmit DMA limit w/tail. */
33 /* 0x5cUL, reserved */
34#define LANAI_RBYTE 0x60UL /* Receive byte. */
35 /* 0x64-->0x6c, reserved */
36#define LANAI_RHALF 0x70UL /* Receive half-word. */
37 /* 0x72UL, reserved */
38#define LANAI_RWORD 0x74UL /* Receive word. */
39#define LANAI_SALIGN 0x78UL /* Send align. */
40#define LANAI_SBYTE 0x7cUL /* SingleSend send-byte. */
41#define LANAI_SHALF 0x80UL /* SingleSend send-halfword. */
42#define LANAI_SWORD 0x84UL /* SingleSend send-word. */
43#define LANAI_SSENDT 0x88UL /* SingleSend special. */
44#define LANAI_DMADIR 0x8cUL /* DMA direction. */
45#define LANAI_DMASTAT 0x90UL /* DMA status. */
46#define LANAI_TIMEO 0x94UL /* Timeout register. */
47#define LANAI_MYRINET 0x98UL /* XXX MAGIC myricom thing */
48#define LANAI_HWDEBUG 0x9cUL /* Hardware debugging reg. */
49#define LANAI_LEDS 0xa0UL /* LED control. */
50#define LANAI_VERS 0xa4UL /* Version register. */
51#define LANAI_LINKON 0xa8UL /* Link activation reg. */
52 /* 0xac-->0x104, reserved */
53#define LANAI_CVAL 0x108UL /* Clock value register. */
54#define LANAI_REG_SIZE 0x10cUL
55
56/* Interrupt status bits. */
57#define ISTAT_DEBUG 0x80000000
58#define ISTAT_HOST 0x40000000
59#define ISTAT_LAN7 0x00800000
60#define ISTAT_LAN6 0x00400000
61#define ISTAT_LAN5 0x00200000
62#define ISTAT_LAN4 0x00100000
63#define ISTAT_LAN3 0x00080000
64#define ISTAT_LAN2 0x00040000
65#define ISTAT_LAN1 0x00020000
66#define ISTAT_LAN0 0x00010000
67#define ISTAT_WRDY 0x00008000
68#define ISTAT_HRDY 0x00004000
69#define ISTAT_SRDY 0x00002000
70#define ISTAT_LINK 0x00001000
71#define ISTAT_FRES 0x00000800
72#define ISTAT_NRES 0x00000800
73#define ISTAT_WAKE 0x00000400
74#define ISTAT_OB2 0x00000200
75#define ISTAT_OB1 0x00000100
76#define ISTAT_TAIL 0x00000080
77#define ISTAT_WDOG 0x00000040
78#define ISTAT_TIME 0x00000020
79#define ISTAT_DMA 0x00000010
80#define ISTAT_SEND 0x00000008
81#define ISTAT_BUF 0x00000004
82#define ISTAT_RECV 0x00000002
83#define ISTAT_BRDY 0x00000001
84
85/* MYRI Registers */
86#define MYRI_RESETOFF 0x00UL
87#define MYRI_RESETON 0x04UL
88#define MYRI_IRQOFF 0x08UL
89#define MYRI_IRQON 0x0cUL
90#define MYRI_WAKEUPOFF 0x10UL
91#define MYRI_WAKEUPON 0x14UL
92#define MYRI_IRQREAD 0x18UL
93 /* 0x1c-->0x3ffc, reserved */
94#define MYRI_LOCALMEM 0x4000UL
95#define MYRI_REG_SIZE 0x25000UL
96
97/* Shared memory interrupt mask. */
98#define SHMEM_IMASK_RX 0x00000002
99#define SHMEM_IMASK_TX 0x00000001
100
101/* Just to make things readable. */
102#define KERNEL_CHANNEL 0
103
104/* The size of this must be >= 129 bytes. */
105struct myri_eeprom {
106 unsigned int cval;
107 unsigned short cpuvers;
108 unsigned char id[6];
109 unsigned int ramsz;
110 unsigned char fvers[32];
111 unsigned char mvers[16];
112 unsigned short dlval;
113 unsigned short brd_type;
114 unsigned short bus_type;
115 unsigned short prod_code;
116 unsigned int serial_num;
117 unsigned short _reserved[24];
118 unsigned int _unused[2];
119};
120
121/* EEPROM bus types, only SBUS is valid in this driver. */
122#define BUS_TYPE_SBUS 1
123
124/* EEPROM CPU revisions. */
125#define CPUVERS_2_3 0x0203
126#define CPUVERS_3_0 0x0300
127#define CPUVERS_3_1 0x0301
128#define CPUVERS_3_2 0x0302
129#define CPUVERS_4_0 0x0400
130#define CPUVERS_4_1 0x0401
131#define CPUVERS_4_2 0x0402
132#define CPUVERS_5_0 0x0500
133
134/* MYRI Control Registers */
135#define MYRICTRL_CTRL 0x00UL
136#define MYRICTRL_IRQLVL 0x02UL
137#define MYRICTRL_REG_SIZE 0x04UL
138
139/* Global control register defines. */
140#define CONTROL_ROFF 0x8000 /* Reset OFF. */
141#define CONTROL_RON 0x4000 /* Reset ON. */
142#define CONTROL_EIRQ 0x2000 /* Enable IRQ's. */
143#define CONTROL_DIRQ 0x1000 /* Disable IRQ's. */
144#define CONTROL_WON 0x0800 /* Wake-up ON. */
145
146#define MYRI_SCATTER_ENTRIES 8
147#define MYRI_GATHER_ENTRIES 16
148
149struct myri_sglist {
150 u32 addr;
151 u32 len;
152};
153
154struct myri_rxd {
155 struct myri_sglist myri_scatters[MYRI_SCATTER_ENTRIES]; /* DMA scatter list.*/
156 u32 csum; /* HW computed checksum. */
157 u32 ctx;
158 u32 num_sg; /* Total scatter entries. */
159};
160
161struct myri_txd {
162 struct myri_sglist myri_gathers[MYRI_GATHER_ENTRIES]; /* DMA scatter list. */
163 u32 num_sg; /* Total scatter entries. */
164 u16 addr[4]; /* XXX address */
165 u32 chan;
166 u32 len; /* Total length of packet. */
167 u32 csum_off; /* Where data to csum is. */
168 u32 csum_field; /* Where csum goes in pkt. */
169};
170
171#define MYRINET_MTU 8432
172#define RX_ALLOC_SIZE 8448
173#define MYRI_PAD_LEN 2
174#define RX_COPY_THRESHOLD 256
175
176/* These numbers are cast in stone, new firmware is needed if
177 * you want to change them.
178 */
179#define TX_RING_MAXSIZE 16
180#define RX_RING_MAXSIZE 16
181
182#define TX_RING_SIZE 16
183#define RX_RING_SIZE 16
184
185/* GRRR... */
186static __inline__ int NEXT_RX(int num)
187{
188 /* XXX >=??? */
189 if(++num > RX_RING_SIZE)
190 num = 0;
191 return num;
192}
193
194static __inline__ int PREV_RX(int num)
195{
196 if(--num < 0)
197 num = RX_RING_SIZE;
198 return num;
199}
200
201#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
202#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
203
204#define TX_BUFFS_AVAIL(head, tail) \
205 ((head) <= (tail) ? \
206 (head) + (TX_RING_SIZE - 1) - (tail) : \
207 (head) - (tail) - 1)
208
209struct sendq {
210 u32 tail;
211 u32 head;
212 u32 hdebug;
213 u32 mdebug;
214 struct myri_txd myri_txd[TX_RING_MAXSIZE];
215};
216
217struct recvq {
218 u32 head;
219 u32 tail;
220 u32 hdebug;
221 u32 mdebug;
222 struct myri_rxd myri_rxd[RX_RING_MAXSIZE + 1];
223};
224
225#define MYRI_MLIST_SIZE 8
226
227struct mclist {
228 u32 maxlen;
229 u32 len;
230 u32 cache;
231 struct pair {
232 u8 addr[8];
233 u32 val;
234 } mc_pairs[MYRI_MLIST_SIZE];
235 u8 bcast_addr[8];
236};
237
238struct myri_channel {
239 u32 state; /* State of the channel. */
240 u32 busy; /* Channel is busy. */
241 struct sendq sendq; /* Device tx queue. */
242 struct recvq recvq; /* Device rx queue. */
243 struct recvq recvqa; /* Device rx queue acked. */
244 u32 rbytes; /* Receive bytes. */
245 u32 sbytes; /* Send bytes. */
246 u32 rmsgs; /* Receive messages. */
247 u32 smsgs; /* Send messages. */
248 struct mclist mclist; /* Device multicast list. */
249};
250
251/* Values for per-channel state. */
252#define STATE_WFH 0 /* Waiting for HOST. */
253#define STATE_WFN 1 /* Waiting for NET. */
254#define STATE_READY 2 /* Ready. */
255
256struct myri_shmem {
257 u8 addr[8]; /* Board's address. */
258 u32 nchan; /* Number of channels. */
259 u32 burst; /* SBUS dma burst enable. */
260 u32 shakedown; /* DarkkkkStarrr Crashesss... */
261 u32 send; /* Send wanted. */
262 u32 imask; /* Interrupt enable mask. */
263 u32 mlevel; /* Map level. */
264 u32 debug[4]; /* Misc. debug areas. */
265 struct myri_channel channel; /* Only one channel on a host. */
266};
267
268struct myri_eth {
269 /* These are frequently accessed, keep together
270 * to obtain good cache hit rates.
271 */
272 spinlock_t irq_lock;
273 struct myri_shmem __iomem *shmem; /* Shared data structures. */
274 void __iomem *cregs; /* Control register space. */
275 struct recvq __iomem *rqack; /* Where we ack rx's. */
276 struct recvq __iomem *rq; /* Where we put buffers. */
277 struct sendq __iomem *sq; /* Where we stuff tx's. */
278 struct net_device *dev; /* Linux/NET dev struct. */
279 int tx_old; /* To speed up tx cleaning. */
280 void __iomem *lregs; /* Quick ptr to LANAI regs. */
281 struct sk_buff *rx_skbs[RX_RING_SIZE+1];/* RX skb's */
282 struct sk_buff *tx_skbs[TX_RING_SIZE]; /* TX skb's */
283
284 /* These are less frequently accessed. */
285 void __iomem *regs; /* MyriCOM register space. */
286 void __iomem *lanai; /* View 2 of register space. */
287 unsigned int myri_bursts; /* SBUS bursts. */
288 struct myri_eeprom eeprom; /* Local copy of EEPROM. */
289 unsigned int reg_size; /* Size of register space. */
290 unsigned int shmem_base; /* Offset to shared ram. */
291 struct platform_device *myri_op; /* Our OF device struct. */
292};
293
294/* We use this to acquire receive skb's that we can DMA directly into. */
295#define ALIGNED_RX_SKB_ADDR(addr) \
296 ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
297static inline struct sk_buff *myri_alloc_skb(unsigned int length, gfp_t gfp_flags)
298{
299 struct sk_buff *skb;
300
301 skb = alloc_skb(length + 64, gfp_flags);
302 if(skb) {
303 int offset = ALIGNED_RX_SKB_ADDR(skb->data);
304
305 if(offset)
306 skb_reserve(skb, offset);
307 }
308 return skb;
309}
310
311#endif /* !(_MYRI_SBUS_H) */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-02 19:36:04 -0500