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authorArnd Bergmann <arnd@arndb.de>2013-03-18 10:46:44 -0400
committerArnd Bergmann <arnd@arndb.de>2013-03-18 10:46:44 -0400
commit1a02bdffa61b47f422343c62d9bbf5708bc8772d (patch)
tree20ebd9257e5d42d8004cf0d4deb5bfcfb86b4abc
parentef9c20ac96eda63734c59449f302b0ac5d418d09 (diff)
parent3e762c86b337f6990cdbd71890921b4dd9351ed9 (diff)
Merge tag 'cleanup_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/cleanup
From Jason Cooper <jason@lakedaemon.net>: mvebu cleanup for v3.10 - plat-orion: prep for mvebu-mbus driver * tag 'cleanup_for_v3.10' of git://git.infradead.org/users/jcooper/linux: arm: mach-orion5x: use mv_mbus_dram_info() in PCI code arm: plat-orion: use mv_mbus_dram_info() in PCIe code arm: plat-orion: only build addr-map.c when needed Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/mach-orion5x/pci.c7
-rw-r--r--arch/arm/plat-orion/Makefile6
-rw-r--r--arch/arm/plat-orion/pcie.c10
3 files changed, 15 insertions, 8 deletions
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index d9c7c3bf0d9c..973db98a3c27 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -402,8 +402,9 @@ static void __init orion5x_pci_master_slave_enable(void)
402 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); 402 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
403} 403}
404 404
405static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram) 405static void __init orion5x_setup_pci_wins(void)
406{ 406{
407 const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
407 u32 win_enable; 408 u32 win_enable;
408 int bus; 409 int bus;
409 int i; 410 int i;
@@ -420,7 +421,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
420 bus = orion5x_pci_local_bus_nr(); 421 bus = orion5x_pci_local_bus_nr();
421 422
422 for (i = 0; i < dram->num_cs; i++) { 423 for (i = 0; i < dram->num_cs; i++) {
423 struct mbus_dram_window *cs = dram->cs + i; 424 const struct mbus_dram_window *cs = dram->cs + i;
424 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); 425 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
425 u32 reg; 426 u32 reg;
426 u32 val; 427 u32 val;
@@ -467,7 +468,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
467 /* 468 /*
468 * Point PCI unit MBUS decode windows to DRAM space. 469 * Point PCI unit MBUS decode windows to DRAM space.
469 */ 470 */
470 orion5x_setup_pci_wins(&orion_mbus_dram_info); 471 orion5x_setup_pci_wins();
471 472
472 /* 473 /*
473 * Master + Slave enable 474 * Master + Slave enable
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index a82cecb84948..ad97400ba3ad 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -3,7 +3,11 @@
3# 3#
4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 4ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
5 5
6obj-y += addr-map.o 6obj-$(CONFIG_ARCH_MVEBU) += addr-map.o
7obj-$(CONFIG_ARCH_KIRKWOOD) += addr-map.o
8obj-$(CONFIG_ARCH_DOVE) += addr-map.o
9obj-$(CONFIG_ARCH_ORION5X) += addr-map.o
10obj-$(CONFIG_ARCH_MV78XX0) += addr-map.o
7 11
8orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o 12orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
9obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o 13obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index f20a321088a2..8b8c06d2e9c4 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks 120 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
121 * WIN[0-3] -> DRAM bank[0-3] 121 * WIN[0-3] -> DRAM bank[0-3]
122 */ 122 */
123static void __init orion_pcie_setup_wins(void __iomem *base, 123static void __init orion_pcie_setup_wins(void __iomem *base)
124 struct mbus_dram_target_info *dram)
125{ 124{
125 const struct mbus_dram_target_info *dram;
126 u32 size; 126 u32 size;
127 int i; 127 int i;
128 128
129 dram = mv_mbus_dram_info();
130
129 /* 131 /*
130 * First, disable and clear BARs and windows. 132 * First, disable and clear BARs and windows.
131 */ 133 */
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
150 */ 152 */
151 size = 0; 153 size = 0;
152 for (i = 0; i < dram->num_cs; i++) { 154 for (i = 0; i < dram->num_cs; i++) {
153 struct mbus_dram_window *cs = dram->cs + i; 155 const struct mbus_dram_window *cs = dram->cs + i;
154 156
155 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); 157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
156 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); 158 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
184 /* 186 /*
185 * Point PCIe unit MBUS decode windows to DRAM space. 187 * Point PCIe unit MBUS decode windows to DRAM space.
186 */ 188 */
187 orion_pcie_setup_wins(base, &orion_mbus_dram_info); 189 orion_pcie_setup_wins(base);
188 190
189 /* 191 /*
190 * Master + slave enable. 192 * Master + slave enable.