drm/radeon: rework crtc pll setup to better support PPLL sharing

We need the calculate the pixel clock before allocating a PPLL
in order to insure the clocks really match.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 150 insertions, 103 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 2f7cc9e3b175..cf8ac5a5d8ca 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -533,11 +533,9 @@ union adjust_pixel_clock {
 };
 
 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
-                               struct drm_display_mode *mode,
-                               struct radeon_pll *pll,
-                               bool ss_enabled,
-                               struct radeon_atom_ss *ss)
+                               struct drm_display_mode *mode)
 {
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
         struct drm_device *dev = crtc->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct drm_encoder *encoder = NULL;
@@ -550,32 +548,32 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
         bool is_duallink = false;
 
         /* reset the pll flags */
-        pll->flags = 0;
+        radeon_crtc->pll_flags = 0;
 
         if (ASIC_IS_AVIVO(rdev)) {
                 if ((rdev->family == CHIP_RS600) ||
                     (rdev->family == CHIP_RS690) ||
                     (rdev->family == CHIP_RS740))
-                        pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
-                                       RADEON_PLL_PREFER_CLOSEST_LOWER);
+                        radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
+                                RADEON_PLL_PREFER_CLOSEST_LOWER);
 
                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
-                        pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                        radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
                 else
-                        pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+                        radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 
                 if (rdev->family < CHIP_RV770)
-                        pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
+                        radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
                 /* use frac fb div on APUs */
                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
-                        pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+                        radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
         } else {
-                pll->flags |= RADEON_PLL_LEGACY;
+                radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 
                 if (mode->clock > 200000)       /* range limits??? */
-                        pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                        radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
                 else
-                        pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+                        radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
         }
 
         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
@@ -598,12 +596,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 
                         /* use recommended ref_div for ss */
                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
-                                if (ss_enabled) {
-                                        if (ss->refdiv) {
-                                                pll->flags |= RADEON_PLL_USE_REF_DIV;
-                                                pll->reference_div = ss->refdiv;
+                                if (radeon_crtc->ss_enabled) {
+                                        if (radeon_crtc->ss.refdiv) {
+                                                radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
+                                                radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
                                                 if (ASIC_IS_AVIVO(rdev))
-                                                        pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+                                                        radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
                                         }
                                 }
                         }
@@ -613,14 +611,14 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
                                         adjusted_clock = mode->clock * 2;
                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
-                                        pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
                                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
-                                        pll->flags |= RADEON_PLL_IS_LCD;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
                         } else {
                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
-                                        pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
-                                        pll->flags |= RADEON_PLL_USE_REF_DIV;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
                         }
                         break;
                 }
@@ -650,7 +648,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
                                 args.v1.ucEncodeMode = encoder_mode;
-                                if (ss_enabled && ss->percentage)
+                                if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
                                         args.v1.ucConfig |=
                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 
@@ -663,7 +661,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
                                 args.v3.sInput.ucEncodeMode = encoder_mode;
                                 args.v3.sInput.ucDispPllConfig = 0;
-                                if (ss_enabled && ss->percentage)
+                                if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
                                         args.v3.sInput.ucDispPllConfig |=
                                                 DISPPLL_CONFIG_SS_ENABLE;
                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
@@ -695,14 +693,14 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                                    index, (uint32_t *)&args);
                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
                                 if (args.v3.sOutput.ucRefDiv) {
-                                        pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
-                                        pll->flags |= RADEON_PLL_USE_REF_DIV;
-                                        pll->reference_div = args.v3.sOutput.ucRefDiv;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
+                                        radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
                                 }
                                 if (args.v3.sOutput.ucPostDiv) {
-                                        pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
-                                        pll->flags |= RADEON_PLL_USE_POST_DIV;
-                                        pll->post_div = args.v3.sOutput.ucPostDiv;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+                                        radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
+                                        radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
                                 }
                                 break;
                         default:
@@ -910,21 +908,17 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 }