aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2012-08-13 10:56:29 -0400
committerArnd Bergmann <arnd@arndb.de>2012-08-13 10:56:29 -0400
commit19ec6caca2da706f11646249ba280177fec359fa (patch)
tree6064421bc4924e7debdc8576a187cbdec4b8c352
parent0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (diff)
parentdd9bf78040fa0da4cecc228e1682b9682b8cb180 (diff)
Merge branch 'cleanup/io-pci' into next/cleanups
From Rob Herring <robherring2@gmail.com>: This is the 2nd part of mach/io.h removals. This series removes io.h on platforms with PCI by creating a fixed virtual I/O mapping and a common __io() macro. This version has changed a bit to accommodate Tegra converting its PCIe host to a platform driver. Now the virtual space is only reserved during early boot before .map_io() is called. The mapping is not created until calling pci_ioremap_io which can be done at any point after vmalloc is initialized. I've gone back to fixed 64K windows for each PCI bus. This allows removing all the i/o resource setup from the individually platforms and placing it within the common ARM PCI code. I've only tested versatilepb under qemu (with the model hacked up to actually enable i/o space), so any testing is appreciated. iop3xx and mv78xx0 have some risk of breaking as the PCI bus addresses are moved to 0 from matching the cpu host bus addesss. * cleanup/io-pci: ARM: iop3xx: use fixed PCI i/o mapping ARM: mv78xx0: use fixed pci i/o mapping ARM: iop13xx: use fixed PCI i/o mapping iop13xx: use more regular PCI I/O space handling ARM: orion5x: use fixed PCI i/o mapping ARM: kirkwood: use fixed PCI i/o mapping ARM: dove: use fixed PCI i/o mapping ARM: footbridge: use fixed PCI i/o mapping ARM: shark: use fixed PCI i/o mapping ARM: integrator: remove trailing whitespace on pci_v3.c ARM: integrator: use fixed PCI i/o mapping ARM: tegra: use fixed PCI i/o mapping ARM: versatile: use fixed PCI i/o mapping ARM: move PCI i/o resource setup into common code ARM: Add fixed PCI i/o mapping i2c: iop3xx: use standard gpiolib functions i2c: iop3xx: clean-up trailing whitespace Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/arm/memory.txt3
-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/include/asm/hardware/iop3xx.h12
-rw-r--r--arch/arm/include/asm/io.h8
-rw-r--r--arch/arm/include/asm/mach/map.h8
-rw-r--r--arch/arm/include/asm/mach/pci.h13
-rw-r--r--arch/arm/kernel/bios32.c54
-rw-r--r--arch/arm/mach-dove/common.c10
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h8
-rw-r--r--arch/arm/mach-dove/include/mach/io.h19
-rw-r--r--arch/arm/mach-dove/pcie.c43
-rw-r--r--arch/arm/mach-footbridge/common.c12
-rw-r--r--arch/arm/mach-footbridge/dc21285.c16
-rw-r--r--arch/arm/mach-footbridge/include/mach/debug-macro.S3
-rw-r--r--arch/arm/mach-footbridge/include/mach/io.h12
-rw-r--r--arch/arm/mach-integrator/include/mach/io.h33
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h4
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c9
-rw-r--r--arch/arm/mach-integrator/pci_v3.c50
-rw-r--r--arch/arm/mach-iop13xx/include/mach/io.h28
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iop13xx.h28
-rw-r--r--arch/arm/mach-iop13xx/io.c27
-rw-r--r--arch/arm/mach-iop13xx/pci.c37
-rw-r--r--arch/arm/mach-iop13xx/setup.c10
-rw-r--r--arch/arm/mach-iop32x/include/mach/io.h19
-rw-r--r--arch/arm/mach-iop33x/include/mach/io.h19
-rw-r--r--arch/arm/mach-kirkwood/common.c10
-rw-r--r--arch/arm/mach-kirkwood/include/mach/io.h24
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h8
-rw-r--r--arch/arm/mach-kirkwood/pcie.c44
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c3
-rw-r--r--arch/arm/mach-mv78xx0/common.c5
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/io.h24
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/mv78xx0.h21
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c110
-rw-r--r--arch/arm/mach-orion5x/common.c10
-rw-r--r--arch/arm/mach-orion5x/include/mach/io.h22
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h20
-rw-r--r--arch/arm/mach-orion5x/pci.c56
-rw-r--r--arch/arm/mach-shark/core.c18
-rw-r--r--arch/arm/mach-shark/include/mach/debug-macro.S7
-rw-r--r--arch/arm/mach-shark/include/mach/entry-macro.S3
-rw-r--r--arch/arm/mach-shark/include/mach/io.h18
-rw-r--r--arch/arm/mach-shark/pci.c5
-rw-r--r--arch/arm/mach-tegra/include/mach/io.h46
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h3
-rw-r--r--arch/arm/mach-tegra/pcie.c95
-rw-r--r--arch/arm/mach-versatile/core.c5
-rw-r--r--arch/arm/mach-versatile/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-versatile/include/mach/io.h27
-rw-r--r--arch/arm/mach-versatile/pci.c22
-rw-r--r--arch/arm/mm/ioremap.c14
-rw-r--r--arch/arm/mm/mmu.c54
-rw-r--r--arch/arm/plat-iop/pci.c25
-rw-r--r--arch/arm/plat-iop/setup.c5
-rw-r--r--drivers/i2c/busses/i2c-iop3xx.c121
56 files changed, 414 insertions, 910 deletions
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index 208a2d465b92..4bfb9ffbdbc1 100644
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -51,6 +51,9 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned
51ff000000 ffbfffff Reserved for future expansion of DMA 51ff000000 ffbfffff Reserved for future expansion of DMA
52 mapping region. 52 mapping region.
53 53
54fee00000 feffffff Mapping of PCI I/O space. This is a static
55 mapping within the vmalloc space.
56
54VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space. 57VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
55 Memory returned by vmalloc/ioremap will 58 Memory returned by vmalloc/ioremap will
56 be dynamically placed in this region. 59 be dynamically placed in this region.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91c7cdc6fe5..e246e8d372a9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -285,7 +285,6 @@ config ARCH_INTEGRATOR
285 select GENERIC_CLOCKEVENTS 285 select GENERIC_CLOCKEVENTS
286 select PLAT_VERSATILE 286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ 287 select PLAT_VERSATILE_FPGA_IRQ
288 select NEED_MACH_IO_H
289 select NEED_MACH_MEMORY_H 288 select NEED_MACH_MEMORY_H
290 select SPARSE_IRQ 289 select SPARSE_IRQ
291 select MULTI_IRQ_HANDLER 290 select MULTI_IRQ_HANDLER
@@ -318,7 +317,6 @@ config ARCH_VERSATILE
318 select ICST 317 select ICST
319 select GENERIC_CLOCKEVENTS 318 select GENERIC_CLOCKEVENTS
320 select ARCH_WANT_OPTIONAL_GPIOLIB 319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select NEED_MACH_IO_H if PCI
322 select PLAT_VERSATILE 320 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLOCK 321 select PLAT_VERSATILE_CLOCK
324 select PLAT_VERSATILE_CLCD 322 select PLAT_VERSATILE_CLCD
@@ -462,7 +460,7 @@ config ARCH_FOOTBRIDGE
462 select FOOTBRIDGE 460 select FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS 461 select GENERIC_CLOCKEVENTS
464 select HAVE_IDE 462 select HAVE_IDE
465 select NEED_MACH_IO_H 463 select NEED_MACH_IO_H if !MMU
466 select NEED_MACH_MEMORY_H 464 select NEED_MACH_MEMORY_H
467 help 465 help
468 Support for systems based on the DC21285 companion chip 466 Support for systems based on the DC21285 companion chip
@@ -519,7 +517,6 @@ config ARCH_IOP13XX
519 select PCI 517 select PCI
520 select ARCH_SUPPORTS_MSI 518 select ARCH_SUPPORTS_MSI
521 select VMSPLIT_1G 519 select VMSPLIT_1G
522 select NEED_MACH_IO_H
523 select NEED_MACH_MEMORY_H 520 select NEED_MACH_MEMORY_H
524 select NEED_RET_TO_USER 521 select NEED_RET_TO_USER
525 help 522 help
@@ -529,7 +526,6 @@ config ARCH_IOP32X
529 bool "IOP32x-based" 526 bool "IOP32x-based"
530 depends on MMU 527 depends on MMU
531 select CPU_XSCALE 528 select CPU_XSCALE
532 select NEED_MACH_IO_H
533 select NEED_RET_TO_USER 529 select NEED_RET_TO_USER
534 select PLAT_IOP 530 select PLAT_IOP
535 select PCI 531 select PCI
@@ -542,7 +538,6 @@ config ARCH_IOP33X
542 bool "IOP33x-based" 538 bool "IOP33x-based"
543 depends on MMU 539 depends on MMU
544 select CPU_XSCALE 540 select CPU_XSCALE
545 select NEED_MACH_IO_H
546 select NEED_RET_TO_USER 541 select NEED_RET_TO_USER
547 select PLAT_IOP 542 select PLAT_IOP
548 select PCI 543 select PCI
@@ -582,7 +577,6 @@ config ARCH_DOVE
582 select PCI 577 select PCI
583 select ARCH_REQUIRE_GPIOLIB 578 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS 579 select GENERIC_CLOCKEVENTS
585 select NEED_MACH_IO_H
586 select PLAT_ORION 580 select PLAT_ORION
587 help 581 help
588 Support for the Marvell Dove SoC 88AP510 582 Support for the Marvell Dove SoC 88AP510
@@ -593,7 +587,6 @@ config ARCH_KIRKWOOD
593 select PCI 587 select PCI
594 select ARCH_REQUIRE_GPIOLIB 588 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS 589 select GENERIC_CLOCKEVENTS
596 select NEED_MACH_IO_H
597 select PLAT_ORION 590 select PLAT_ORION
598 help 591 help
599 Support for the following Marvell Kirkwood series SoCs: 592 Support for the following Marvell Kirkwood series SoCs:
@@ -620,7 +613,6 @@ config ARCH_MV78XX0
620 select PCI 613 select PCI
621 select ARCH_REQUIRE_GPIOLIB 614 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS 615 select GENERIC_CLOCKEVENTS
623 select NEED_MACH_IO_H
624 select PLAT_ORION 616 select PLAT_ORION
625 help 617 help
626 Support for the following Marvell MV78xx0 series SoCs: 618 Support for the following Marvell MV78xx0 series SoCs:
@@ -633,7 +625,6 @@ config ARCH_ORION5X
633 select PCI 625 select PCI
634 select ARCH_REQUIRE_GPIOLIB 626 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS 627 select GENERIC_CLOCKEVENTS
636 select NEED_MACH_IO_H
637 select PLAT_ORION 628 select PLAT_ORION
638 help 629 help
639 Support for the following Marvell Orion 5x series SoCs: 630 Support for the following Marvell Orion 5x series SoCs:
@@ -689,7 +680,6 @@ config ARCH_TEGRA
689 select HAVE_CLK 680 select HAVE_CLK
690 select HAVE_SMP 681 select HAVE_SMP
691 select MIGHT_HAVE_CACHE_L2X0 682 select MIGHT_HAVE_CACHE_L2X0
692 select NEED_MACH_IO_H if PCI
693 select ARCH_HAS_CPUFREQ 683 select ARCH_HAS_CPUFREQ
694 select USE_OF 684 select USE_OF
695 help 685 help
@@ -918,7 +908,6 @@ config ARCH_SHARK
918 select PCI 908 select PCI
919 select ARCH_USES_GETTIMEOFFSET 909 select ARCH_USES_GETTIMEOFFSET
920 select NEED_MACH_MEMORY_H 910 select NEED_MACH_MEMORY_H
921 select NEED_MACH_IO_H
922 help 911 help
923 Support for the StrongARM based Digital DNARD machine, also known 912 Support for the StrongARM based Digital DNARD machine, also known
924 as "Shark" (<http://www.shark-linux.de/shark.html>). 913 as "Shark" (<http://www.shark-linux.de/shark.html>).
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 2ff2c75a4639..02fe2fbe2477 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -217,18 +217,8 @@ extern int iop3xx_get_init_atu(void);
217#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 217#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
218#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 218#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
219 219
220#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
221#define IOP3XX_PCI_LOWER_IO_PA 0x90000000 220#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
222#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 221#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
223#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
224#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
225 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
226#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
227 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
228#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
229 IOP3XX_PCI_LOWER_IO_PA) +\
230 IOP3XX_PCI_LOWER_IO_VA)
231
232 222
233#ifndef __ASSEMBLY__ 223#ifndef __ASSEMBLY__
234 224
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669fec0a..8f4db67533e5 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -113,11 +113,19 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
113#define __iowmb() do { } while (0) 113#define __iowmb() do { } while (0)
114#endif 114#endif
115 115
116/* PCI fixed i/o mapping */
117#define PCI_IO_VIRT_BASE 0xfee00000
118
119extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
120
116/* 121/*
117 * Now, pick up the machine-defined IO definitions 122 * Now, pick up the machine-defined IO definitions
118 */ 123 */
119#ifdef CONFIG_NEED_MACH_IO_H 124#ifdef CONFIG_NEED_MACH_IO_H
120#include <mach/io.h> 125#include <mach/io.h>
126#elif defined(CONFIG_PCI)
127#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
128#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
121#else 129#else
122#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) 130#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
123#endif 131#endif
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index a6efcdd6fd25..195ac2f9d3d3 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -9,6 +9,9 @@
9 * 9 *
10 * Page table mapping constructs and function prototypes 10 * Page table mapping constructs and function prototypes
11 */ 11 */
12#ifndef __ASM_MACH_MAP_H
13#define __ASM_MACH_MAP_H
14
12#include <asm/io.h> 15#include <asm/io.h>
13 16
14struct map_desc { 17struct map_desc {
@@ -34,6 +37,8 @@ struct map_desc {
34 37
35#ifdef CONFIG_MMU 38#ifdef CONFIG_MMU
36extern void iotable_init(struct map_desc *, int); 39extern void iotable_init(struct map_desc *, int);
40extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
41 void *caller);
37 42
38struct mem_type; 43struct mem_type;
39extern const struct mem_type *get_mem_type(unsigned int type); 44extern const struct mem_type *get_mem_type(unsigned int type);
@@ -44,4 +49,7 @@ extern int ioremap_page(unsigned long virt, unsigned long phys,
44 const struct mem_type *mtype); 49 const struct mem_type *mtype);
45#else 50#else
46#define iotable_init(map,num) do { } while (0) 51#define iotable_init(map,num) do { } while (0)
52#define vm_reserve_area_early(a,s,c) do { } while (0)
53#endif
54
47#endif 55#endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 26c511fddf8f..db9fedb57f2c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_MACH_PCI_H 11#ifndef __ASM_MACH_PCI_H
12#define __ASM_MACH_PCI_H 12#define __ASM_MACH_PCI_H
13 13
14#include <linux/ioport.h>
15
14struct pci_sys_data; 16struct pci_sys_data;
15struct pci_ops; 17struct pci_ops;
16struct pci_bus; 18struct pci_bus;
@@ -42,6 +44,8 @@ struct pci_sys_data {
42 unsigned long io_offset; /* bus->cpu IO mapping offset */ 44 unsigned long io_offset; /* bus->cpu IO mapping offset */
43 struct pci_bus *bus; /* PCI bus */ 45 struct pci_bus *bus; /* PCI bus */
44 struct list_head resources; /* root bus resources (apertures) */ 46 struct list_head resources; /* root bus resources (apertures) */
47 struct resource io_res;
48 char io_res_name[12];
45 /* Bridge swizzling */ 49 /* Bridge swizzling */
46 u8 (*swizzle)(struct pci_dev *, u8 *); 50 u8 (*swizzle)(struct pci_dev *, u8 *);
47 /* IRQ mapping */ 51 /* IRQ mapping */
@@ -55,6 +59,15 @@ struct pci_sys_data {
55void pci_common_init(struct hw_pci *); 59void pci_common_init(struct hw_pci *);
56 60
57/* 61/*
62 * Setup early fixed I/O mapping.
63 */
64#if defined(CONFIG_PCI)
65extern void pci_map_io_early(unsigned long pfn);
66#else
67static inline void pci_map_io_early(unsigned long pfn) {}
68#endif
69
70/*
58 * PCI controllers 71 * PCI controllers
59 */ 72 */
60extern struct pci_ops iop3xx_ops; 73extern struct pci_ops iop3xx_ops;
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2b2f25e7fef5..b244696de1a3 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -13,6 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14 14
15#include <asm/mach-types.h> 15#include <asm/mach-types.h>
16#include <asm/mach/map.h>
16#include <asm/mach/pci.h> 17#include <asm/mach/pci.h>
17 18
18static int debug_pci; 19static int debug_pci;
@@ -423,6 +424,38 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
423 return irq; 424 return irq;
424} 425}
425 426
427static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
428{
429 int ret;
430 struct pci_host_bridge_window *window;
431
432 if (list_empty(&sys->resources)) {
433 pci_add_resource_offset(&sys->resources,
434 &iomem_resource, sys->mem_offset);
435 }
436
437 list_for_each_entry(window, &sys->resources, list) {
438 if (resource_type(window->res) == IORESOURCE_IO)
439 return 0;
440 }
441
442 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
443 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
444 sys->io_res.flags = IORESOURCE_IO;
445 sys->io_res.name = sys->io_res_name;
446 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
447
448 ret = request_resource(&ioport_resource, &sys->io_res);
449 if (ret) {
450 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
451 return ret;
452 }
453 pci_add_resource_offset(&sys->resources, &sys->io_res,
454 sys->io_offset);
455
456 return 0;
457}
458
426static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) 459static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
427{ 460{
428 struct pci_sys_data *sys = NULL; 461 struct pci_sys_data *sys = NULL;
@@ -445,11 +478,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
445 ret = hw->setup(nr, sys); 478 ret = hw->setup(nr, sys);
446 479
447 if (ret > 0) { 480 if (ret > 0) {
448 if (list_empty(&sys->resources)) { 481 ret = pcibios_init_resources(nr, sys);
449 pci_add_resource_offset(&sys->resources, 482 if (ret) {
450 &ioport_resource, sys->io_offset); 483 kfree(sys);
451 pci_add_resource_offset(&sys->resources, 484 break;
452 &iomem_resource, sys->mem_offset);
453 } 485 }
454 486
455 if (hw->scan) 487 if (hw->scan)
@@ -627,3 +659,15 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
627 659
628 return 0; 660 return 0;
629} 661}
662
663void __init pci_map_io_early(unsigned long pfn)
664{
665 struct map_desc pci_io_desc = {
666 .virtual = PCI_IO_VIRT_BASE,
667 .type = MT_DEVICE,
668 .length = SZ_64K,
669 };
670
671 pci_io_desc.pfn = pfn;
672 iotable_init(&pci_io_desc, 1);
673}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 4db5de54b6a7..ed4fa5f316ea 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -49,16 +49,6 @@ static struct map_desc dove_io_desc[] __initdata = {
49 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 49 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
50 .length = DOVE_NB_REGS_SIZE, 50 .length = DOVE_NB_REGS_SIZE,
51 .type = MT_DEVICE, 51 .type = MT_DEVICE,
52 }, {
53 .virtual = DOVE_PCIE0_IO_VIRT_BASE,
54 .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
55 .length = DOVE_PCIE0_IO_SIZE,
56 .type = MT_DEVICE,
57 }, {
58 .virtual = DOVE_PCIE1_IO_VIRT_BASE,
59 .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
60 .length = DOVE_PCIE1_IO_SIZE,
61 .type = MT_DEVICE,
62 }, 52 },
63}; 53};
64 54
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index d52b0ef313b7..c91e3004a47b 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -50,14 +50,12 @@
50#define DOVE_NB_REGS_SIZE SZ_8M 50#define DOVE_NB_REGS_SIZE SZ_8M
51 51
52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
53#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000
54#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 53#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
55#define DOVE_PCIE0_IO_SIZE SZ_1M 54#define DOVE_PCIE0_IO_SIZE SZ_64K
56 55
57#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 56#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
58#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 57#define DOVE_PCIE1_IO_BUS_BASE 0x00010000
59#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 58#define DOVE_PCIE1_IO_SIZE SZ_64K
60#define DOVE_PCIE1_IO_SIZE SZ_1M
61 59
62/* 60/*
63 * Dove Core Registers Map 61 * Dove Core Registers Map
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
deleted file mode 100644
index 29c8b85355a5..000000000000
--- a/arch/arm/mach-dove/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-dove/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "dove.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
17 DOVE_PCIE0_IO_VIRT_BASE))
18
19#endif
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 47921b0cdc65..355332d502cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -26,9 +26,8 @@ struct pcie_port {
26 u8 root_bus_nr; 26 u8 root_bus_nr;
27 void __iomem *base; 27 void __iomem *base;
28 spinlock_t conf_lock; 28 spinlock_t conf_lock;
29 char io_space_name[16];
30 char mem_space_name[16]; 29 char mem_space_name[16];
31 struct resource res[2]; 30 struct resource res;
32}; 31};
33 32
34static struct pcie_port pcie_port[2]; 33static struct pcie_port pcie_port[2];
@@ -53,24 +52,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
53 52
54 orion_pcie_setup(pp->base); 53 orion_pcie_setup(pp->base);
55 54
56 /* 55 if (pp->index == 0)
57 * IORESOURCE_IO 56 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
58 */ 57 else
59 snprintf(pp->io_space_name, sizeof(pp->io_space_name), 58 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
60 "PCIe %d I/O", pp->index);
61 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
62 pp->res[0].name = pp->io_space_name;
63 if (pp->index == 0) {
64 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
65 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
66 } else {
67 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
68 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
69 }
70 pp->res[0].flags = IORESOURCE_IO;
71 if (request_resource(&ioport_resource, &pp->res[0]))
72 panic("Request PCIe IO resource failed\n");
73 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
74 59
75 /* 60 /*
76 * IORESOURCE_MEM 61 * IORESOURCE_MEM
@@ -78,18 +63,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
78 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 63 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
79 "PCIe %d MEM", pp->index); 64 "PCIe %d MEM", pp->index);
80 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 65 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
81 pp->res[1].name = pp->mem_space_name; 66 pp->res.name = pp->mem_space_name;
82 if (pp->index == 0) { 67 if (pp->index == 0) {
83 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; 68 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
84 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; 69 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
85 } else { 70 } else {
86 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; 71 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
87 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; 72 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
88 } 73 }
89 pp->res[1].flags = IORESOURCE_MEM; 74 pp->res.flags = IORESOURCE_MEM;
90 if (request_resource(&iomem_resource, &pp->res[1])) 75 if (request_resource(&iomem_resource, &pp->res))
91 panic("Request PCIe Memory resource failed\n"); 76 panic("Request PCIe Memory resource failed\n");
92 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); 77 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
93 78
94 return 1; 79 return 1;
95} 80}
@@ -210,7 +195,7 @@ static void __init add_pcie_port(int index, unsigned long base)
210 pp->root_bus_nr = -1; 195 pp->root_bus_nr = -1;
211 pp->base = (void __iomem *)base; 196 pp->base = (void __iomem *)base;
212 spin_lock_init(&pp->conf_lock); 197 spin_lock_init(&pp->conf_lock);
213 memset(pp->res, 0, sizeof(pp->res)); 198 memset(&pp->res, 0, sizeof(pp->res));
214 } else { 199 } else {
215 printk(KERN_INFO "link down, ignoring\n"); 200 printk(KERN_INFO "link down, ignoring\n");
216 } 201 }
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 3e6aaa6361da..a42b369bc439 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -15,7 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18 18
19#include <asm/pgtable.h> 19#include <asm/pgtable.h>
20#include <asm/page.h> 20#include <asm/page.h>
21#include <asm/irq.h> 21#include <asm/irq.h>
@@ -26,6 +26,7 @@
26 26
27#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/pci.h>
29 30
30#include "common.h" 31#include "common.h"
31 32
@@ -175,11 +176,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
175 .pfn = __phys_to_pfn(DC21285_PCI_IACK), 176 .pfn = __phys_to_pfn(DC21285_PCI_IACK),
176 .length = PCIIACK_SIZE, 177 .length = PCIIACK_SIZE,
177 .type = MT_DEVICE, 178 .type = MT_DEVICE,
178 }, {
179 .virtual = PCIO_BASE,
180 .pfn = __phys_to_pfn(DC21285_PCI_IO),
181 .length = PCIO_SIZE,
182 .type = MT_DEVICE,
183 }, 179 },
184#endif 180#endif
185}; 181};
@@ -196,8 +192,10 @@ void __init footbridge_map_io(void)
196 * Now, work out what we've got to map in addition on this 192 * Now, work out what we've got to map in addition on this
197 * platform. 193 * platform.
198 */ 194 */
199 if (footbridge_cfn_mode()) 195 if (footbridge_cfn_mode()) {
200 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); 196 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
197 pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
198 }
201} 199}
202 200
203void footbridge_restart(char mode, const char *cmd) 201void footbridge_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 9d62e3381024..a7cd2cf5e08d 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
276 276
277 sys->mem_offset = DC21285_PCI_MEM; 277 sys->mem_offset = DC21285_PCI_MEM;
278 278
279 pci_add_resource_offset(&sys->resources, 279 pci_ioremap_io(0, DC21285_PCI_IO);
280 &ioport_resource, sys->io_offset); 280
281 pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); 281 pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
282 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 282 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
283 283
@@ -298,7 +298,7 @@ void __init dc21285_preinit(void)
298 mem_size = (unsigned int)high_memory - PAGE_OFFSET; 298 mem_size = (unsigned int)high_memory - PAGE_OFFSET;
299 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) 299 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
300 if (mem_mask >= mem_size) 300 if (mem_mask >= mem_size)
301 break; 301 break;
302 302
303 /* 303 /*
304 * These registers need to be set up whether we're the 304 * These registers need to be set up whether we're the
@@ -350,14 +350,6 @@ void __init dc21285_preinit(void)
350 "PCI data parity", NULL); 350 "PCI data parity", NULL);
351 351
352 if (cfn_mode) { 352 if (cfn_mode) {
353 static struct resource csrio;
354
355 csrio.flags = IORESOURCE_IO;
356 csrio.name = "Footbridge";
357
358 allocate_resource(&ioport_resource, &csrio, 128,
359 0xff00, 0xffff, 128, NULL, NULL);
360
361 /* 353 /*
362 * Map our SDRAM at a known address in PCI space, just in case 354 * Map our SDRAM at a known address in PCI space, just in case
363 * the firmware had other ideas. Using a nonzero base is 355 * the firmware had other ideas. Using a nonzero base is
@@ -365,7 +357,7 @@ void __init dc21285_preinit(void)
365 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). 357 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
366 */ 358 */
367 *CSR_PCICSRBASE = 0xf4000000; 359 *CSR_PCICSRBASE = 0xf4000000;
368 *CSR_PCICSRIOBASE = csrio.start; 360 *CSR_PCICSRIOBASE = 0;
369 *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); 361 *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
370 *CSR_PCIROMBASE = 0; 362 *CSR_PCIROMBASE = 0;
371 *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 363 *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index e5acde25ffc5..c169f0c99b2a 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -17,7 +17,8 @@
17 /* For NetWinder debugging */ 17 /* For NetWinder debugging */
18 .macro addruart, rp, rv, tmp 18 .macro addruart, rp, rv, tmp
19 mov \rp, #0x000003f8 19 mov \rp, #0x000003f8
20 orr \rv, \rp, #0xff000000 @ virtual 20 orr \rv, \rp, #0xfe000000 @ virtual
21 orr \rv, \rv, #0x00e00000 @ virtual
21 orr \rp, \rp, #0x7c000000 @ physical 22 orr \rp, \rp, #0x7c000000 @ physical
22 .endm 23 .endm
23 24
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index aba531eebbc6..aba46388cc0c 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -14,18 +14,10 @@
14#ifndef __ASM_ARM_ARCH_IO_H 14#ifndef __ASM_ARM_ARCH_IO_H
15#define __ASM_ARM_ARCH_IO_H 15#define __ASM_ARM_ARCH_IO_H
16 16
17#ifdef CONFIG_MMU
18#define MMU_IO(a, b) (a)
19#else
20#define MMU_IO(a, b) (b)
21#endif
22
23#define PCIO_SIZE 0x00100000
24#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000)
25
26/* 17/*
27 * Translation of various region addresses to virtual addresses 18 * Translation of various i/o addresses to host addresses for !CONFIG_MMU
28 */ 19 */
20#define PCIO_BASE 0x7c000000
29#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) 21#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
30 22
31#endif 23#endif
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
deleted file mode 100644
index 8de70de3dd0a..000000000000
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-integrator/include/mach/io.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23/*
24 * WARNING: this has to mirror definitions in platform.h
25 */
26#define PCI_MEMORY_VADDR 0xe8000000
27#define PCI_CONFIG_VADDR 0xec000000
28#define PCI_V3_VADDR 0xed000000
29#define PCI_IO_VADDR 0xee000000
30
31#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
32
33#endif
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index ec467baade09..4c0347526851 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -324,6 +324,10 @@
324 */ 324 */
325#define PHYS_PCI_V3_BASE 0x62000000 325#define PHYS_PCI_V3_BASE 0x62000000
326 326
327#define PCI_MEMORY_VADDR 0xe8000000
328#define PCI_CONFIG_VADDR 0xec000000
329#define PCI_V3_VADDR 0xed000000
330
327/* ------------------------------------------------------------------------ 331/* ------------------------------------------------------------------------
328 * Integrator Interrupt Controllers 332 * Integrator Interrupt Controllers
329 * ------------------------------------------------------------------------ 333 * ------------------------------------------------------------------------
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 7b1055c8e0b9..3c1dc4369c2b 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -50,6 +50,7 @@
50#include <asm/mach/arch.h> 50#include <asm/mach/arch.h>
51#include <asm/mach/irq.h> 51#include <asm/mach/irq.h>
52#include <asm/mach/map.h> 52#include <asm/mach/map.h>
53#include <asm/mach/pci.h>
53#include <asm/mach/time.h> 54#include <asm/mach/time.h>
54 55
55#include <plat/fpga-irq.h> 56#include <plat/fpga-irq.h>
@@ -73,7 +74,7 @@
73 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) 74 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
74 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) 75 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
75 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) 76 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
76 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) 77 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
77 * ef000000 Cache flush 78 * ef000000 Cache flush
78 * f1000000 10000000 Core module registers 79 * f1000000 10000000 Core module registers
79 * f1100000 11000000 System controller registers 80 * f1100000 11000000 System controller registers
@@ -147,11 +148,6 @@ static struct map_desc ap_io_desc[] __initdata = {
147 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), 148 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
148 .length = SZ_64K, 149 .length = SZ_64K,
149 .type = MT_DEVICE 150 .type = MT_DEVICE
150 }, {
151 .virtual = PCI_IO_VADDR,
152 .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
153 .length = SZ_64K,
154 .type = MT_DEVICE
155 } 151 }
156}; 152};
157 153
@@ -159,6 +155,7 @@ static void __init ap_map_io(void)
159{ 155{
160 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); 156 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
161 vga_base = PCI_MEMORY_VADDR; 157 vga_base = PCI_MEMORY_VADDR;
158 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
162} 159}
163 160
164#define INTEGRATOR_SC_VALID_INT 0x003fffff 161#define INTEGRATOR_SC_VALID_INT 0x003fffff
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b866880e82ac..495f181fc937 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -41,61 +41,61 @@
41/* 41/*
42 * The V3 PCI interface chip in Integrator provides several windows from 42 * The V3 PCI interface chip in Integrator provides several windows from
43 * local bus memory into the PCI memory areas. Unfortunately, there 43 * local bus memory into the PCI memory areas. Unfortunately, there
44 * are not really enough windows for our usage, therefore we reuse 44 * are not really enough windows for our usage, therefore we reuse
45 * one of the windows for access to PCI configuration space. The 45 * one of the windows for access to PCI configuration space. The
46 * memory map is as follows: 46 * memory map is as follows:
47 * 47 *
48 * Local Bus Memory Usage 48 * Local Bus Memory Usage
49 * 49 *
50 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable 50 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
51 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable 51 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
52 * 60000000 - 60FFFFFF PCI IO. 16M 52 * 60000000 - 60FFFFFF PCI IO. 16M
53 * 61000000 - 61FFFFFF PCI Configuration. 16M 53 * 61000000 - 61FFFFFF PCI Configuration. 16M
54 * 54 *
55 * There are three V3 windows, each described by a pair of V3 registers. 55 * There are three V3 windows, each described by a pair of V3 registers.
56 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. 56 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
57 * Base0 and Base1 can be used for any type of PCI memory access. Base2 57 * Base0 and Base1 can be used for any type of PCI memory access. Base2
58 * can be used either for PCI I/O or for I20 accesses. By default, uHAL 58 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
59 * uses this only for PCI IO space. 59 * uses this only for PCI IO space.
60 * 60 *
61 * Normally these spaces are mapped using the following base registers: 61 * Normally these spaces are mapped using the following base registers:
62 * 62 *
63 * Usage Local Bus Memory Base/Map registers used 63 * Usage Local Bus Memory Base/Map registers used
64 * 64 *
65 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 65 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
66 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 66 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
67 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 67 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
68 * Cfg 61000000 - 61FFFFFF 68 * Cfg 61000000 - 61FFFFFF
69 * 69 *
70 * This means that I20 and PCI configuration space accesses will fail. 70 * This means that I20 and PCI configuration space accesses will fail.
71 * When PCI configuration accesses are needed (via the uHAL PCI 71 * When PCI configuration accesses are needed (via the uHAL PCI
72 * configuration space primitives) we must remap the spaces as follows: 72 * configuration space primitives) we must remap the spaces as follows:
73 * 73 *
74 * Usage Local Bus Memory Base/Map registers used 74 * Usage Local Bus Memory Base/Map registers used
75 * 75 *
76 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 76 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
77 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 77 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
78 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 78 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
79 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 79 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
80 * 80 *
81 * To make this work, the code depends on overlapping windows working. 81 * To make this work, the code depends on overlapping windows working.
82 * The V3 chip translates an address by checking its range within 82 * The V3 chip translates an address by checking its range within
83 * each of the BASE/MAP pairs in turn (in ascending register number 83 * each of the BASE/MAP pairs in turn (in ascending register number
84 * order). It will use the first matching pair. So, for example, 84 * order). It will use the first matching pair. So, for example,
85 * if the same address is mapped by both LB_BASE0/LB_MAP0 and 85 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
86 * LB_BASE1/LB_MAP1, the V3 will use the translation from 86 * LB_BASE1/LB_MAP1, the V3 will use the translation from
87 * LB_BASE0/LB_MAP0. 87 * LB_BASE0/LB_MAP0.
88 * 88 *
89 * To allow PCI Configuration space access, the code enlarges the 89 * To allow PCI Configuration space access, the code enlarges the
90 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes 90 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
91 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can 91 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
92 * be remapped for use by configuration cycles. 92 * be remapped for use by configuration cycles.
93 * 93 *
94 * At the end of the PCI Configuration space accesses, 94 * At the end of the PCI Configuration space accesses,
95 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window 95 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
96 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to 96 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
97 * reveal the now restored LB_BASE1/LB_MAP1 window. 97 * reveal the now restored LB_BASE1/LB_MAP1 window.
98 * 98 *
99 * NOTE: We do not set up I2O mapping. I suspect that this is only 99 * NOTE: We do not set up I2O mapping. I suspect that this is only
100 * for an intelligent (target) device. Using I2O disables most of 100 * for an intelligent (target) device. Using I2O disables most of
101 * the mappings into PCI memory. 101 * the mappings into PCI memory.
@@ -127,8 +127,8 @@
127 * 127 *
128 * returns: configuration address to play on the PCI bus 128 * returns: configuration address to play on the PCI bus
129 * 129 *
130 * To generate the appropriate PCI configuration cycles in the PCI 130 * To generate the appropriate PCI configuration cycles in the PCI
131 * configuration address space, you present the V3 with the following pattern 131 * configuration address space, you present the V3 with the following pattern
132 * (which is very nearly a type 1 (except that the lower two bits are 00 and 132 * (which is very nearly a type 1 (except that the lower two bits are 00 and
133 * not 01). In order for this mapping to work you need to set up one of 133 * not 01). In order for this mapping to work you need to set up one of
134 * the local to PCI aperatures to 16Mbytes in length translating to 134 * the local to PCI aperatures to 16Mbytes in length translating to
@@ -138,7 +138,7 @@
138 * 138 *
139 * Type 0: 139 * Type 0:
140 * 140 *
141 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 141 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
142 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 142 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
143 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 143 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
144 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| 144 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
@@ -150,7 +150,7 @@
150 * 150 *
151 * Type 1: 151 * Type 1:
152 * 152 *
153 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 153 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
154 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 154 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
155 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 155 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
156 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| 156 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
@@ -161,7 +161,7 @@
161 * 15:11 Device number (5 bits) 161 * 15:11 Device number (5 bits)
162 * 10:8 function number 162 * 10:8 function number
163 * 7:2 register number 163 * 7:2 register number
164 * 164 *
165 */ 165 */
166static DEFINE_RAW_SPINLOCK(v3_lock); 166static DEFINE_RAW_SPINLOCK(v3_lock);
167 167
@@ -374,12 +374,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
374 } 374 }
375 375
376 /* 376 /*
377 * the IO resource for this bus
378 * the mem resource for this bus 377 * the mem resource for this bus
379 * the prefetch mem resource for this bus 378 * the prefetch mem resource for this bus
380 */ 379 */
381 pci_add_resource_offset(&sys->resources,
382 &ioport_resource, sys->io_offset);
383 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); 380 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
384 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); 381 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
385 382
@@ -498,7 +495,6 @@ void __init pci_v3_preinit(void)
498 unsigned int temp; 495 unsigned int temp;
499 int ret; 496 int ret;
500 497
501 pcibios_min_io = 0x6000;
502 pcibios_min_mem = 0x00100000; 498 pcibios_min_mem = 0x00100000;
503 499
504 /* 500 /*
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index f13188518025..000000000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) __iop13xx_io(a)
25
26extern void __iomem * __iop13xx_io(unsigned long io_addr);
27
28#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e190dcd7d72d..e10e101645dd 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,21 +69,11 @@ extern unsigned long get_iop_tick_rate(void);
69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window 69 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
70 * 70 *
71 * IO MAP 71 * IO MAP
72 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window 72 * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
73 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window 73 * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
74 */ 74 */
75#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
76#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL 75#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
77#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
78#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ 76#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
79#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
80#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
83 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
84#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
85 (IOP13XX_PCIX_LOWER_IO_PA\
86 - IOP13XX_PCIX_LOWER_IO_VA))
87 77
88#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL 78#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
89#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL 79#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
@@ -103,20 +93,8 @@ extern unsigned long get_iop_tick_rate(void);
103 IOP13XX_PCIX_LOWER_MEM_BA) 93 IOP13XX_PCIX_LOWER_MEM_BA)
104 94
105/* PCI-E ranges */ 95/* PCI-E ranges */
106#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
107#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL 96#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
108#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL 97#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
109#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
110#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
111#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
112 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
113#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
114 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
115#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
116 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
117#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
118 (IOP13XX_PCIE_LOWER_IO_PA\
119 - IOP13XX_PCIE_LOWER_IO_VA))
120 98
121#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL 99#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
122#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL 100#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 3c364198db9c..851dc8f2b6b5 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,25 +23,6 @@
23 23
24#include "pci.h" 24#include "pci.h"
25 25
26void * __iomem __iop13xx_io(unsigned long io_addr)
27{
28 void __iomem * io_virt;
29
30 switch (io_addr) {
31 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
32 io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
33 break;
34 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
35 io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
36 break;
37 default:
38 BUG();
39 }
40
41 return io_virt;
42}
43EXPORT_SYMBOL(__iop13xx_io);
44
45static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, 26static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
46 size_t size, unsigned int mtype, void *caller) 27 size_t size, unsigned int mtype, void *caller)
47{ 28{
@@ -67,12 +48,6 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
67 (cookie - IOP13XX_PBI_LOWER_MEM_RA), 48 (cookie - IOP13XX_PBI_LOWER_MEM_RA),
68 size, mtype, __builtin_return_address(0)); 49 size, mtype, __builtin_return_address(0));
69 break; 50 break;
70 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
71 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
72 break;
73 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
74 retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
75 break;
76 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: 51 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
77 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); 52 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
78 break; 53 break;
@@ -99,8 +74,6 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
99 goto skip; 74 goto skip;
100 75
101 switch ((u32) addr) { 76 switch ((u32) addr) {
102 case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
103 case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
104 case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: 77 case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
105 goto skip; 78 goto skip;
106 } 79 }
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 861cb12ef436..91f731a2957b 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -970,7 +970,6 @@ void __init iop13xx_pci_init(void)
970 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); 970 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
971 971
972 /* Setup the Min Address for PCI memory... */ 972 /* Setup the Min Address for PCI memory... */
973 pcibios_min_io = 0;
974 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 973 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
975 974
976 /* if Linux is given control of an ATU 975 /* if Linux is given control of an ATU
@@ -1003,7 +1002,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1003 if (nr > 1) 1002 if (nr > 1)
1004 return 0; 1003 return 0;
1005 1004
1006 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); 1005 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1007 if (!res) 1006 if (!res)
1008 panic("PCI: unable to alloc resources"); 1007 panic("PCI: unable to alloc resources");
1009 1008
@@ -1042,17 +1041,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1042 << IOP13XX_ATUX_PCIXSR_FUNC_NUM; 1041 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1043 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); 1042 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1044 1043
1045 res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; 1044 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1046 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1047 res[0].name = "IQ81340 ATUX PCI I/O Space";
1048 res[0].flags = IORESOURCE_IO;
1049 1045
1050 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; 1046 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1051 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; 1047 res->end = IOP13XX_PCIX_UPPER_MEM_RA;
1052 res[1].name = "IQ81340 ATUX PCI Memory Space"; 1048 res->name = "IQ81340 ATUX PCI Memory Space";
1053 res[1].flags = IORESOURCE_MEM; 1049 res->flags = IORESOURCE_MEM;
1054 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; 1050 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1055 sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
1056 break; 1051 break;
1057 case IOP13XX_INIT_ATU_ATUE: 1052 case IOP13XX_INIT_ATU_ATUE:
1058 /* Note: the function number field in the PCSR is ro */ 1053 /* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1058,13 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1063 1058
1064 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); 1059 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1065 1060
1066 res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; 1061 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1067 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1068 res[0].name = "IQ81340 ATUE PCI I/O Space";
1069 res[0].flags = IORESOURCE_IO;
1070 1062
1071 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; 1063 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1072 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; 1064 res->end = IOP13XX_PCIE_UPPER_MEM_RA;
1073 res[1].name = "IQ81340 ATUE PCI Memory Space"; 1065 res->name = "IQ81340 ATUE PCI Memory Space";
1074 res[1].flags = IORESOURCE_MEM; 1066 res->flags = IORESOURCE_MEM;
1075 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; 1067 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1076 sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
1077 sys->map_irq = iop13xx_pcie_map_irq; 1068 sys->map_irq = iop13xx_pcie_map_irq;
1078 break; 1069 break;
1079 default: 1070 default:
@@ -1081,11 +1072,9 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1081 return 0; 1072 return 0;
1082 } 1073 }
1083 1074
1084 request_resource(&ioport_resource, &res[0]); 1075 request_resource(&iomem_resource, res);
1085 request_resource(&iomem_resource, &res[1]);
1086 1076
1087 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 1077 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1088 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
1089 1078
1090 return 1; 1079 return 1;
1091} 1080}
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1fa6c2c..4a7f20d7fb6e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -40,16 +40,6 @@ static struct map_desc iop13xx_std_desc[] __initdata = {
40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), 40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
41 .length = IOP13XX_PMMR_SIZE, 41 .length = IOP13XX_PMMR_SIZE,
42 .type = MT_DEVICE, 42 .type = MT_DEVICE,
43 }, { /* PCIE IO space */
44 .virtual = IOP13XX_PCIE_LOWER_IO_VA,
45 .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
46 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
47 .type = MT_DEVICE,
48 }, { /* PCIX IO space */
49 .virtual = IOP13XX_PCIX_LOWER_IO_VA,
50 .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
51 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
52 .type = MT_DEVICE,
53 }, 43 },
54}; 44};
55 45
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
deleted file mode 100644
index e2ada265bb8d..000000000000
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/include/mach/io.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __IO_H
12#define __IO_H
13
14#include <asm/hardware/iop3xx.h>
15
16#define IO_SPACE_LIMIT 0xffffffff
17#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
18
19#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
deleted file mode 100644
index f7c1b6595660..000000000000
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/io.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __IO_H
12#define __IO_H
13
14#include <asm/hardware/iop3xx.h>
15
16#define IO_SPACE_LIMIT 0xffffffff
17#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
18
19#endif
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c4b64adcbfce..31d9f400ed82 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -42,16 +42,6 @@
42 ****************************************************************************/ 42 ****************************************************************************/
43static struct map_desc kirkwood_io_desc[] __initdata = { 43static struct map_desc kirkwood_io_desc[] __initdata = {
44 { 44 {
45 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
46 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
47 .length = KIRKWOOD_PCIE_IO_SIZE,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
51 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
52 .length = KIRKWOOD_PCIE1_IO_SIZE,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = KIRKWOOD_REGS_VIRT_BASE, 45 .virtual = KIRKWOOD_REGS_VIRT_BASE,
56 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), 46 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
57 .length = KIRKWOOD_REGS_SIZE, 47 .length = KIRKWOOD_REGS_SIZE,
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
deleted file mode 100644
index 5d0ab61700d2..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "kirkwood.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
19 + KIRKWOOD_PCIE_IO_VIRT_BASE);
20}
21
22#define __io(a) __io(a)
23
24#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index c5b68510776b..af4f0000dcef 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -37,14 +37,12 @@
37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K 37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
38 38
39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
40#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 40#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000
41#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 41#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K
42#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
43 42
44#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 43#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
45#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
46#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 44#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
47#define KIRKWOOD_PCIE_IO_SIZE SZ_1M 45#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
48 46
49#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 47#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
50#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 48#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 6e8b2efa3c35..532d8acb38f9 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -56,7 +56,7 @@ struct pcie_port {
56 void __iomem *base; 56 void __iomem *base;
57 spinlock_t conf_lock; 57 spinlock_t conf_lock;
58 int irq; 58 int irq;
59 struct resource res[2]; 59 struct resource res;
60}; 60};
61 61
62static int pcie_port_map[2]; 62static int pcie_port_map[2];
@@ -137,20 +137,12 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
137 pp->irq = IRQ_KIRKWOOD_PCIE; 137 pp->irq = IRQ_KIRKWOOD_PCIE;
138 138
139 /* 139 /*
140 * IORESOURCE_IO
141 */
142 pp->res[0].name = "PCIe 0 I/O Space";
143 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
144 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
145 pp->res[0].flags = IORESOURCE_IO;
146
147 /*
148 * IORESOURCE_MEM 140 * IORESOURCE_MEM
149 */ 141 */
150 pp->res[1].name = "PCIe 0 MEM"; 142 pp->res.name = "PCIe 0 MEM";
151 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; 143 pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
152 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; 144 pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
153 pp->res[1].flags = IORESOURCE_MEM; 145 pp->res.flags = IORESOURCE_MEM;
154} 146}
155 147
156static void __init pcie1_ioresources_init(struct pcie_port *pp) 148static void __init pcie1_ioresources_init(struct pcie_port *pp)
@@ -159,20 +151,12 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp)
159 pp->irq = IRQ_KIRKWOOD_PCIE1; 151 pp->irq = IRQ_KIRKWOOD_PCIE1;
160 152
161 /* 153 /*
162 * IORESOURCE_IO
163 */
164 pp->res[0].name = "PCIe 1 I/O Space";
165 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
166 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
167 pp->res[0].flags = IORESOURCE_IO;
168
169 /*
170 * IORESOURCE_MEM 154 * IORESOURCE_MEM
171 */ 155 */
172 pp->res[1].name = "PCIe 1 MEM"; 156 pp->res.name = "PCIe 1 MEM";
173 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; 157 pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
174 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; 158 pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
175 pp->res[1].flags = IORESOURCE_MEM; 159 pp->res.flags = IORESOURCE_MEM;
176} 160}
177 161
178static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) 162static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -197,23 +181,21 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
197 case 0: 181 case 0:
198 kirkwood_enable_pcie_clk("0"); 182 kirkwood_enable_pcie_clk("0");
199 pcie0_ioresources_init(pp); 183 pcie0_ioresources_init(pp);
184 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
200 break; 185 break;
201 case 1: 186 case 1:
202 kirkwood_enable_pcie_clk("1"); 187 kirkwood_enable_pcie_clk("1");
203 pcie1_ioresources_init(pp); 188 pcie1_ioresources_init(pp);
189 pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
204 break; 190 break;
205 default: 191 default:
206 panic("PCIe setup: invalid controller %d", index); 192 panic("PCIe setup: invalid controller %d", index);
207 } 193 }
208 194
209 if (request_resource(&ioport_resource, &pp->res[0])) 195 if (request_resource(&iomem_resource, &pp->res))
210 panic("Request PCIe%d IO resource failed\n", index);
211 if (request_resource(&iomem_resource, &pp->res[1]))
212 panic("Request PCIe%d Memory resource failed\n", index); 196 panic("Request PCIe%d Memory resource failed\n", index);
213 197
214 sys->io_offset = 0; 198 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
215 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
216 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
217 199
218 /* 200 /*
219 * Generic PCIe unit setup. 201 * Generic PCIe unit setup.
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 62b53d710efd..7764d9386f2a 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -13,6 +13,7 @@
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/addr-map.h> 15#include <plat/addr-map.h>
16#include <mach/mv78xx0.h>
16#include "common.h" 17#include "common.h"
17 18
18/* 19/*
@@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
81 int maj, int min) 82 int maj, int min)
82{ 83{
83 orion_setup_cpu_win(&addr_map_cfg, window, base, size, 84 orion_setup_cpu_win(&addr_map_cfg, window, base, size,
84 TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); 85 TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
85} 86}
86 87
87void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, 88void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index b4c53b846c9c..20826449e61b 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -135,11 +135,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = {
135 .length = MV78XX0_CORE_REGS_SIZE, 135 .length = MV78XX0_CORE_REGS_SIZE,
136 .type = MT_DEVICE, 136 .type = MT_DEVICE,
137 }, { 137 }, {
138 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
139 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
140 .length = MV78XX0_PCIE_IO_SIZE * 8,
141 .type = MT_DEVICE,
142 }, {
143 .virtual = MV78XX0_REGS_VIRT_BASE, 138 .virtual = MV78XX0_REGS_VIRT_BASE,
144 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 139 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
145 .length = MV78XX0_REGS_SIZE, 140 .length = MV78XX0_REGS_SIZE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
deleted file mode 100644
index c7d9d00d8fc1..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-mv78xx0/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "mv78xx0.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
19 + MV78XX0_PCIE_IO_VIRT_BASE(0));
20}
21
22#define __io(a) __io(a)
23
24#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c52a0b..bd03fed1128e 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -29,15 +29,15 @@
29 * 29 *
30 * virt phys size 30 * virt phys size
31 * fe400000 f102x000 16K core-specific peripheral registers 31 * fe400000 f102x000 16K core-specific peripheral registers
32 * fe700000 f0800000 1M PCIe #0 I/O space 32 * fee00000 f0800000 64K PCIe #0 I/O space
33 * fe800000 f0900000 1M PCIe #1 I/O space 33 * fee10000 f0900000 64K PCIe #1 I/O space
34 * fe900000 f0a00000 1M PCIe #2 I/O space 34 * fee20000 f0a00000 64K PCIe #2 I/O space
35 * fea00000 f0b00000 1M PCIe #3 I/O space 35 * fee30000 f0b00000 64K PCIe #3 I/O space
36 * feb00000 f0c00000 1M PCIe #4 I/O space 36 * fee40000 f0c00000 64K PCIe #4 I/O space
37 * fec00000 f0d00000 1M PCIe #5 I/O space 37 * fee50000 f0d00000 64K PCIe #5 I/O space
38 * fed00000 f0e00000 1M PCIe #6 I/O space 38 * fee60000 f0e00000 64K PCIe #6 I/O space
39 * fee00000 f0f00000 1M PCIe #7 I/O space 39 * fee70000 f0f00000 64K PCIe #7 I/O space
40 * fef00000 f1000000 1M on-chip peripheral registers 40 * fd000000 f1000000 1M on-chip peripheral registers
41 */ 41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
@@ -46,11 +46,10 @@
46#define MV78XX0_CORE_REGS_SIZE SZ_16K 46#define MV78XX0_CORE_REGS_SIZE SZ_16K
47 47
48#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 48#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
49#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
50#define MV78XX0_PCIE_IO_SIZE SZ_1M 49#define MV78XX0_PCIE_IO_SIZE SZ_1M
51 50
52#define MV78XX0_REGS_PHYS_BASE 0xf1000000 51#define MV78XX0_REGS_PHYS_BASE 0xf1000000
53#define MV78XX0_REGS_VIRT_BASE 0xfef00000 52#define MV78XX0_REGS_VIRT_BASE 0xfd000000
54#define MV78XX0_REGS_SIZE SZ_1M 53#define MV78XX0_REGS_SIZE SZ_1M
55 54
56#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 2e56e86b6d68..26a059b4f472 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -15,6 +15,7 @@
15#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
16#include <plat/pcie.h> 16#include <plat/pcie.h>
17#include <plat/addr-map.h> 17#include <plat/addr-map.h>
18#include <mach/mv78xx0.h>
18#include "common.h" 19#include "common.h"
19 20
20struct pcie_port { 21struct pcie_port {
@@ -23,16 +24,13 @@ struct pcie_port {
23 u8 root_bus_nr; 24 u8 root_bus_nr;
24 void __iomem *base; 25 void __iomem *base;
25 spinlock_t conf_lock; 26 spinlock_t conf_lock;
26 char io_space_name[16];
27 char mem_space_name[16]; 27 char mem_space_name[16];
28 struct resource res[2]; 28 struct resource res;
29}; 29};
30 30
31static struct pcie_port pcie_port[8]; 31static struct pcie_port pcie_port[8];
32static int num_pcie_ports; 32static int num_pcie_ports;
33static struct resource pcie_io_space; 33static struct resource pcie_io_space;
34static struct resource pcie_mem_space;
35
36 34
37void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) 35void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
38{ 36{
@@ -40,102 +38,59 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
40 *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); 38 *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
41} 39}
42 40
41u32 pcie_port_size[8] = {
42 0,
43 0x30000000,
44 0x10000000,
45 0x10000000,
46 0x08000000,
47 0x08000000,
48 0x08000000,
49 0x04000000,
50};
51
43static void __init mv78xx0_pcie_preinit(void) 52static void __init mv78xx0_pcie_preinit(void)
44{ 53{
45 int i; 54 int i;
46 u32 size_each; 55 u32 size_each;
47 u32 start; 56 u32 start;
48 int win; 57 int win = 0;
49 58
50 pcie_io_space.name = "PCIe I/O Space"; 59 pcie_io_space.name = "PCIe I/O Space";
51 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); 60 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
52 pcie_io_space.end = 61 pcie_io_space.end =
53 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; 62 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
54 pcie_io_space.flags = IORESOURCE_IO; 63 pcie_io_space.flags = IORESOURCE_MEM;
55 if (request_resource(&iomem_resource, &pcie_io_space)) 64 if (request_resource(&iomem_resource, &pcie_io_space))
56 panic("can't allocate PCIe I/O space"); 65 panic("can't allocate PCIe I/O space");
57 66
58 pcie_mem_space.name = "PCIe MEM Space"; 67 if (num_pcie_ports > 7)
59 pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; 68 panic("invalid number of PCIe ports");
60 pcie_mem_space.end = 69
61 MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; 70 size_each = pcie_port_size[num_pcie_ports];
62 pcie_mem_space.flags = IORESOURCE_MEM;
63 if (request_resource(&iomem_resource, &pcie_mem_space))
64 panic("can't allocate PCIe MEM space");
65 71
72 start = MV78XX0_PCIE_MEM_PHYS_BASE;
66 for (i = 0; i < num_pcie_ports; i++) { 73 for (i = 0; i < num_pcie_ports; i++) {
67 struct pcie_port *pp = pcie_port + i; 74 struct pcie_port *pp = pcie_port + i;
68 75
69 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
70 "PCIe %d.%d I/O", pp->maj, pp->min);
71 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
72 pp->res[0].name = pp->io_space_name;
73 pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
74 pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
75 pp->res[0].flags = IORESOURCE_IO;
76
77 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
78 "PCIe %d.%d MEM", pp->maj, pp->min); 77 "PCIe %d.%d MEM", pp->maj, pp->min);
79 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 78 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
80 pp->res[1].name = pp->mem_space_name; 79 pp->res.name = pp->mem_space_name;
81 pp->res[1].flags = IORESOURCE_MEM; 80 pp->res.flags = IORESOURCE_MEM;
82 } 81 pp->res.start = start;
83 82 pp->res.end = start + size_each - 1;
84 switch (num_pcie_ports) {
85 case 0:
86 size_each = 0;
87 break;
88
89 case 1:
90 size_each = 0x30000000;
91 break;
92
93 case 2 ... 3:
94 size_each = 0x10000000;
95 break;
96
97 case 4 ... 6:
98 size_each = 0x08000000;
99 break;
100
101 case 7:
102 size_each = 0x04000000;
103 break;
104
105 default:
106 panic("invalid number of PCIe ports");
107 }
108
109 start = MV78XX0_PCIE_MEM_PHYS_BASE;
110 for (i = 0; i < num_pcie_ports; i++) {
111 struct pcie_port *pp = pcie_port + i;
112
113 pp->res[1].start = start;
114 pp->res[1].end = start + size_each - 1;
115 start += size_each; 83 start += size_each;
116 }
117
118 for (i = 0; i < num_pcie_ports; i++) {
119 struct pcie_port *pp = pcie_port + i;
120 84
121 if (request_resource(&pcie_io_space, &pp->res[0])) 85 if (request_resource(&iomem_resource, &pp->res))
122 panic("can't allocate PCIe I/O sub-space");
123
124 if (request_resource(&pcie_mem_space, &pp->res[1]))
125 panic("can't allocate PCIe MEM sub-space"); 86 panic("can't allocate PCIe MEM sub-space");
126 }
127 87
128 win = 0; 88 mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
129 for (i = 0; i < num_pcie_ports; i++) { 89 resource_size(&pp->res),
130 struct pcie_port *pp = pcie_port + i; 90 pp->maj, pp->min);
131 91
132 mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, 92 mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
133 resource_size(&pp->res[0]),
134 pp->maj, pp->min); 93 pp->maj, pp->min);
135
136 mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
137 resource_size(&pp->res[1]),
138 pp->maj, pp->min);
139 } 94 }
140} 95}
141 96
@@ -156,8 +111,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
156 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 111 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
157 orion_pcie_setup(pp->base); 112 orion_pcie_setup(pp->base);
158 113
159 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); 114 pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
160 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); 115
116 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
161 117
162 return 1; 118 return 1;
163} 119}
@@ -281,7 +237,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
281 pp->root_bus_nr = -1; 237 pp->root_bus_nr = -1;
282 pp->base = (void __iomem *)base; 238 pp->base = (void __iomem *)base;
283 spin_lock_init(&pp->conf_lock); 239 spin_lock_init(&pp->conf_lock);
284 memset(pp->res, 0, sizeof(pp->res)); 240 memset(&pp->res, 0, sizeof(pp->res));
285 } else { 241 } else {
286 printk("link down, ignoring\n"); 242 printk("link down, ignoring\n");
287 } 243 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 9148b229d0de..70f7d712d6f4 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -47,16 +47,6 @@ static struct map_desc orion5x_io_desc[] __initdata = {
47 .length = ORION5X_REGS_SIZE, 47 .length = ORION5X_REGS_SIZE,
48 .type = MT_DEVICE, 48 .type = MT_DEVICE,
49 }, { 49 }, {
50 .virtual = ORION5X_PCIE_IO_VIRT_BASE,
51 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
52 .length = ORION5X_PCIE_IO_SIZE,
53 .type = MT_DEVICE,
54 }, {
55 .virtual = ORION5X_PCI_IO_VIRT_BASE,
56 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
57 .length = ORION5X_PCI_IO_SIZE,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = ORION5X_PCIE_WA_VIRT_BASE, 50 .virtual = ORION5X_PCIE_WA_VIRT_BASE,
61 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 51 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
62 .length = ORION5X_PCIE_WA_SIZE, 52 .length = ORION5X_PCIE_WA_SIZE,
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
deleted file mode 100644
index 1aa5d0a50a0b..000000000000
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * arch/arm/mach-orion5x/include/mach/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include <mach/orion5x.h>
13#include <asm/sizes.h>
14
15#define IO_SPACE_LIMIT SZ_2M
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
19}
20
21#define __io(a) __io(a)
22#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 683e085ce162..1b60131b7f60 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -31,31 +31,29 @@
31 * fc000000 device bus mappings (cs0/cs1) 31 * fc000000 device bus mappings (cs0/cs1)
32 * 32 *
33 * virt phys size 33 * virt phys size
34 * fdd00000 f1000000 1M on-chip peripheral registers 34 * fe000000 f1000000 1M on-chip peripheral registers
35 * fde00000 f2000000 1M PCIe I/O space 35 * fee00000 f2000000 64K PCIe I/O space
36 * fdf00000 f2100000 1M PCI I/O space 36 * fee10000 f2100000 64K PCI I/O space
37 * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) 37 * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
38 ****************************************************************************/ 38 ****************************************************************************/
39#define ORION5X_REGS_PHYS_BASE 0xf1000000 39#define ORION5X_REGS_PHYS_BASE 0xf1000000
40#define ORION5X_REGS_VIRT_BASE 0xfdd00000 40#define ORION5X_REGS_VIRT_BASE 0xfe000000
41#define ORION5X_REGS_SIZE SZ_1M 41#define ORION5X_REGS_SIZE SZ_1M
42 42
43#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 43#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
44#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
45#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 44#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
46#define ORION5X_PCIE_IO_SIZE SZ_1M 45#define ORION5X_PCIE_IO_SIZE SZ_64K
47 46
48#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 47#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
49#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 48#define ORION5X_PCI_IO_BUS_BASE 0x00010000
50#define ORION5X_PCI_IO_BUS_BASE 0x00100000 49#define ORION5X_PCI_IO_SIZE SZ_64K
51#define ORION5X_PCI_IO_SIZE SZ_1M
52 50
53#define ORION5X_SRAM_PHYS_BASE (0xf2200000) 51#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
54#define ORION5X_SRAM_SIZE SZ_8K 52#define ORION5X_SRAM_SIZE SZ_8K
55 53
56/* Relevant only for Orion-1/Orion-NAS */ 54/* Relevant only for Orion-1/Orion-NAS */
57#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 55#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
58#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 56#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000
59#define ORION5X_PCIE_WA_SIZE SZ_16M 57#define ORION5X_PCIE_WA_SIZE SZ_16M
60 58
61#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 59#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index cb19e1661bb3..6921d49b988d 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -162,35 +162,25 @@ static int __init pcie_setup(struct pci_sys_data *sys)
162 pcie_ops.read = pcie_rd_conf_wa; 162 pcie_ops.read = pcie_rd_conf_wa;
163 } 163 }
164 164
165 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
166
165 /* 167 /*
166 * Request resources. 168 * Request resources.
167 */ 169 */
168 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 170 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
169 if (!res) 171 if (!res)
170 panic("pcie_setup unable to alloc resources"); 172 panic("pcie_setup unable to alloc resources");
171 173
172 /* 174 /*
173 * IORESOURCE_IO
174 */
175 sys->io_offset = 0;
176 res[0].name = "PCIe I/O Space";
177 res[0].flags = IORESOURCE_IO;
178 res[0].start = ORION5X_PCIE_IO_BUS_BASE;
179 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
180 if (request_resource(&ioport_resource, &res[0]))
181 panic("Request PCIe IO resource failed\n");
182 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
183
184 /*
185 * IORESOURCE_MEM 175 * IORESOURCE_MEM
186 */ 176 */
187 res[1].name = "PCIe Memory Space"; 177 res->name = "PCIe Memory Space";
188 res[1].flags = IORESOURCE_MEM; 178 res->flags = IORESOURCE_MEM;
189 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE; 179 res->start = ORION5X_PCIE_MEM_PHYS_BASE;
190 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 180 res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
191 if (request_resource(&iomem_resource, &res[1])) 181 if (request_resource(&iomem_resource, res))
192 panic("Request PCIe Memory resource failed\n"); 182 panic("Request PCIe Memory resource failed\n");
193 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 183 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
194 184
195 return 1; 185 return 1;
196} 186}
@@ -489,35 +479,25 @@ static int __init pci_setup(struct pci_sys_data *sys)
489 */ 479 */
490 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER); 480 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
491 481
482 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
483
492 /* 484 /*
493 * Request resources 485 * Request resources
494 */ 486 */
495 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL); 487 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
496 if (!res) 488 if (!res)
497 panic("pci_setup unable to alloc resources"); 489 panic("pci_setup unable to alloc resources");
498 490
499 /* 491 /*
500 * IORESOURCE_IO
501 */
502 sys->io_offset = 0;
503 res[0].name = "PCI I/O Space";
504 res[0].flags = IORESOURCE_IO;
505 res[0].start = ORION5X_PCI_IO_BUS_BASE;
506 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
507 if (request_resource(&ioport_resource, &res[0]))
508 panic("Request PCI IO resource failed\n");
509 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
510
511 /*
512 * IORESOURCE_MEM 492 * IORESOURCE_MEM
513 */ 493 */
514 res[1].name = "PCI Memory Space"; 494 res->name = "PCI Memory Space";
515 res[1].flags = IORESOURCE_MEM; 495 res->flags = IORESOURCE_MEM;
516 res[1].start = ORION5X_PCI_MEM_PHYS_BASE; 496 res->start = ORION5X_PCI_MEM_PHYS_BASE;
517 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 497 res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
518 if (request_resource(&iomem_resource, &res[1])) 498 if (request_resource(&iomem_resource, res))
519 panic("Request PCI Memory resource failed\n"); 499 panic("Request PCI Memory resource failed\n");
520 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 500 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
521 501
522 return 1; 502 return 1;
523} 503}
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 2704bcd869cd..d35b94ef73b7 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -21,9 +21,6 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23 23
24#define IO_BASE 0xe0000000
25#define IO_SIZE 0x08000000
26#define IO_START 0x40000000
27#define ROMCARD_SIZE 0x08000000 24#define ROMCARD_SIZE 0x08000000
28#define ROMCARD_START 0x10000000 25#define ROMCARD_START 0x10000000
29 26
@@ -104,20 +101,6 @@ arch_initcall(shark_init);
104 101
105extern void shark_init_irq(void); 102extern void shark_init_irq(void);
106 103
107static struct map_desc shark_io_desc[] __initdata = {
108 {
109 .virtual = IO_BASE,
110 .pfn = __phys_to_pfn(IO_START),
111 .length = IO_SIZE,
112 .type = MT_DEVICE
113 }
114};
115
116static void __init shark_map_io(void)
117{
118 iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
119}
120
121#define IRQ_TIMER 0 104#define IRQ_TIMER 0
122#define HZ_TIME ((1193180 + HZ/2) / HZ) 105#define HZ_TIME ((1193180 + HZ/2) / HZ)
123 106
@@ -158,7 +141,6 @@ static void shark_init_early(void)
158MACHINE_START(SHARK, "Shark") 141MACHINE_START(SHARK, "Shark")
159 /* Maintainer: Alexander Schulz */ 142 /* Maintainer: Alexander Schulz */
160 .atag_offset = 0x3000, 143 .atag_offset = 0x3000,
161 .map_io = shark_map_io,
162 .init_early = shark_init_early, 144 .init_early = shark_init_early,
163 .init_irq = shark_init_irq, 145 .init_irq = shark_init_irq,
164 .timer = &shark_timer, 146 .timer = &shark_timer,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 20eb2bf2a42b..d129119a3f69 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -12,9 +12,10 @@
12*/ 12*/
13 13
14 .macro addruart, rp, rv, tmp 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0xe0000000 15 mov \rp, #0x3f8
16 orr \rp, \rp, #0x000003f8 16 orr \rv, \rp, #0xfe000000
17 mov \rv, \rp 17 orr \rv, \rv, #0x00e00000
18 orr \rp, \rp, #0x40000000
18 .endm 19 .endm
19 20
20 .macro senduart,rd,rx 21 .macro senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 5901b09fc96a..c9e49f049532 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -8,7 +8,8 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 .macro get_irqnr_preamble, base, tmp 10 .macro get_irqnr_preamble, base, tmp
11 mov \base, #0xe0000000 11 mov \base, #0xfe000000
12 orr \base, \base, #0x00e00000
12 .endm 13 .endm
13 14
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
deleted file mode 100644
index 1a45fc01ff1d..000000000000
--- a/arch/arm/mach-shark/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * arch/arm/mach-shark/include/mach/io.h
3 *
4 * by Alexander Schulz
5 *
6 * derived from:
7 * arch/arm/mach-ebsa110/include/mach/io.h
8 * Copyright (C) 1997,1998 Russell King
9 */
10
11#ifndef __ASM_ARM_ARCH_IO_H
12#define __ASM_ARM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16#define __io(a) ((void __iomem *)(0xe0000000 + (a)))
17
18#endif
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index 9089407d5326..b8b4ab323a3e 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -8,12 +8,15 @@
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/pci.h> 9#include <linux/pci.h>
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/io.h>
11#include <video/vga.h> 12#include <video/vga.h>
12 13
13#include <asm/irq.h> 14#include <asm/irq.h>
14#include <asm/mach/pci.h> 15#include <asm/mach/pci.h>
15#include <asm/mach-types.h> 16#include <asm/mach-types.h>
16 17
18#define IO_START 0x40000000
19
17static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 20static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
18{ 21{
19 if (dev->bus->number == 0) 22 if (dev->bus->number == 0)
@@ -44,6 +47,8 @@ static int __init shark_pci_init(void)
44 pcibios_min_mem = 0x50000000; 47 pcibios_min_mem = 0x50000000;
45 vga_base = 0xe8000000; 48 vga_base = 0xe8000000;
46 49
50 pci_ioremap_io(0, IO_START);
51
47 pci_common_init(&shark_pci); 52 pci_common_init(&shark_pci);
48 53
49 return 0; 54 return 0;
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644
index fe700f9ce7dc..000000000000
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/io.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IO_H
22#define __MACH_TEGRA_IO_H
23
24#define IO_SPACE_LIMIT 0xffff
25
26#ifndef __ASSEMBLER__
27
28#ifdef CONFIG_TEGRA_PCI
29extern void __iomem *tegra_pcie_io_base;
30
31static inline void __iomem *__io(unsigned long addr)
32{
33 return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
34}
35#else
36static inline void __iomem *__io(unsigned long addr)
37{
38 return (void __iomem *)addr;
39}
40#endif
41
42#define __io(a) __io(a)
43
44#endif
45
46#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 7e76da73121c..fee3a94c4549 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -303,6 +303,9 @@
303#define IO_APB_VIRT IOMEM(0xFE300000) 303#define IO_APB_VIRT IOMEM(0xFE300000)
304#define IO_APB_SIZE SZ_1M 304#define IO_APB_SIZE SZ_1M
305 305
306#define TEGRA_PCIE_BASE 0x80000000
307#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
308
306#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 309#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
307#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 310#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
308 311
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d3ad5150d660..3463fb5b79c7 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -171,8 +171,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
171 * 0x90000000 - 0x9fffffff - non-prefetchable memory 171 * 0x90000000 - 0x9fffffff - non-prefetchable memory
172 * 0xa0000000 - 0xbfffffff - prefetchable memory 172 * 0xa0000000 - 0xbfffffff - prefetchable memory
173 */ 173 */
174#define TEGRA_PCIE_BASE 0x80000000
175
176#define PCIE_REGS_SZ SZ_16K 174#define PCIE_REGS_SZ SZ_16K
177#define PCIE_CFG_OFF PCIE_REGS_SZ 175#define PCIE_CFG_OFF PCIE_REGS_SZ
178#define PCIE_CFG_SZ SZ_1M 176#define PCIE_CFG_SZ SZ_1M
@@ -180,8 +178,6 @@ static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
180#define PCIE_EXT_CFG_SZ SZ_1M 178#define PCIE_EXT_CFG_SZ SZ_1M
181#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) 179#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
182 180
183#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M)
184#define MMIO_SIZE SZ_64K
185#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) 181#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
186#define MEM_SIZE_0 SZ_128M 182#define MEM_SIZE_0 SZ_128M
187#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0) 183#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
@@ -204,10 +200,9 @@ struct tegra_pcie_port {
204 200
205 bool link_up; 201 bool link_up;
206 202
207 char io_space_name[16];
208 char mem_space_name[16]; 203 char mem_space_name[16];
209 char prefetch_space_name[20]; 204 char prefetch_space_name[20];
210 struct resource res[3]; 205 struct resource res[2];
211}; 206};
212 207
213struct tegra_pcie_info { 208struct tegra_pcie_info {
@@ -223,17 +218,7 @@ struct tegra_pcie_info {
223 struct clk *pll_e; 218 struct clk *pll_e;
224}; 219};
225 220
226static struct tegra_pcie_info tegra_pcie = { 221static struct tegra_pcie_info tegra_pcie;
227 .res_mmio = {
228 .name = "PCI IO",
229 .start = MMIO_BASE,
230 .end = MMIO_BASE + MMIO_SIZE - 1,
231 .flags = IORESOURCE_MEM,
232 },
233};
234
235void __iomem *tegra_pcie_io_base;
236EXPORT_SYMBOL(tegra_pcie_io_base);
237 222
238static inline void afi_writel(u32 value, unsigned long offset) 223static inline void afi_writel(u32 value, unsigned long offset)
239{ 224{
@@ -391,24 +376,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
391 pp = tegra_pcie.port + nr; 376 pp = tegra_pcie.port + nr;
392 pp->root_bus_nr = sys->busnr; 377 pp->root_bus_nr = sys->busnr;
393 378
394 /* 379 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
395 * IORESOURCE_IO
396 */
397 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
398 "PCIe %d I/O", pp->index);
399 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
400 pp->res[0].name = pp->io_space_name;
401 if (pp->index == 0) {
402 pp->res[0].start = PCIBIOS_MIN_IO;
403 pp->res[0].end = pp->res[0].start + SZ_32K - 1;
404 } else {
405 pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
406 pp->res[0].end = IO_SPACE_LIMIT;
407 }
408 pp->res[0].flags = IORESOURCE_IO;
409 if (request_resource(&ioport_resource, &pp->res[0]))
410 panic("Request PCIe IO resource failed\n");
411 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
412 380
413 /* 381 /*
414 * IORESOURCE_MEM 382 * IORESOURCE_MEM
@@ -416,18 +384,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
416 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 384 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
417 "PCIe %d MEM", pp->index); 385 "PCIe %d MEM", pp->index);
418 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; 386 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
419 pp->res[1].name = pp->mem_space_name; 387 pp->res[0].name = pp->mem_space_name;
420 if (pp->index == 0) { 388 if (pp->index == 0) {
421 pp->res[1].start = MEM_BASE_0; 389 pp->res[0].start = MEM_BASE_0;
422 pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1; 390 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
423 } else { 391 } else {
424 pp->res[1].start = MEM_BASE_1; 392 pp->res[0].start = MEM_BASE_1;
425 pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1; 393 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
426 } 394 }
427 pp->res[1].flags = IORESOURCE_MEM; 395 pp->res[0].flags = IORESOURCE_MEM;
428 if (request_resource(&iomem_resource, &pp->res[1])) 396 if (request_resource(&iomem_resource, &pp->res[0]))
429 panic("Request PCIe Memory resource failed\n"); 397 panic("Request PCIe Memory resource failed\n");
430 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); 398 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
431 399
432 /* 400 /*
433 * IORESOURCE_MEM | IORESOURCE_PREFETCH 401 * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -435,18 +403,18 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
435 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name), 403 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
436 "PCIe %d PREFETCH MEM", pp->index); 404 "PCIe %d PREFETCH MEM", pp->index);
437 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0; 405 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
438 pp->res[2].name = pp->prefetch_space_name; 406 pp->res[1].name = pp->prefetch_space_name;
439 if (pp->index == 0) { 407 if (pp->index == 0) {
440 pp->res[2].start = PREFETCH_MEM_BASE_0; 408 pp->res[1].start = PREFETCH_MEM_BASE_0;
441 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1; 409 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
442 } else { 410 } else {
443 pp->res[2].start = PREFETCH_MEM_BASE_1; 411 pp->res[1].start = PREFETCH_MEM_BASE_1;
444 pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1; 412 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
445 } 413 }
446 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 414 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (request_resource(&iomem_resource, &pp->res[2])) 415 if (request_resource(&iomem_resource, &pp->res[1]))
448 panic("Request PCIe Prefetch Memory resource failed\n"); 416 panic("Request PCIe Prefetch Memory resource failed\n");
449 pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset); 417 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
450 418
451 return 1; 419 return 1;
452} 420}
@@ -541,8 +509,8 @@ static void tegra_pcie_setup_translations(void)
541 509
542 /* Bar 2: downstream IO bar */ 510 /* Bar 2: downstream IO bar */
543 fpci_bar = ((__u32)0xfdfc << 16); 511 fpci_bar = ((__u32)0xfdfc << 16);
544 size = MMIO_SIZE; 512 size = SZ_128K;
545 axi_address = MMIO_BASE; 513 axi_address = TEGRA_PCIE_IO_BASE;
546 afi_writel(axi_address, AFI_AXI_BAR2_START); 514 afi_writel(axi_address, AFI_AXI_BAR2_START);
547 afi_writel(size >> 12, AFI_AXI_BAR2_SZ); 515 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
548 afi_writel(fpci_bar, AFI_FPCI_BAR2); 516 afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -776,7 +744,6 @@ static void tegra_pcie_clocks_put(void)
776 744
777static int __init tegra_pcie_get_resources(void) 745static int __init tegra_pcie_get_resources(void)
778{ 746{
779 struct resource *res_mmio = &tegra_pcie.res_mmio;
780 int err; 747 int err;
781 748
782 err = tegra_pcie_clocks_get(); 749 err = tegra_pcie_clocks_get();
@@ -798,34 +765,16 @@ static int __init tegra_pcie_get_resources(void)
798 goto err_map_reg; 765 goto err_map_reg;
799 } 766 }
800 767
801 err = request_resource(&iomem_resource, res_mmio);
802 if (err) {
803 pr_err("PCIE: Failed to request resources: %d\n", err);
804 goto err_req_io;
805 }
806
807 tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
808 resource_size(res_mmio));
809 if (tegra_pcie_io_base == NULL) {
810 pr_err("PCIE: Failed to map IO\n");
811 err = -ENOMEM;
812 goto err_map_io;
813 }
814
815 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, 768 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
816 IRQF_SHARED, "PCIE", &tegra_pcie); 769 IRQF_SHARED, "PCIE", &tegra_pcie);
817 if (err) { 770 if (err) {
818 pr_err("PCIE: Failed to register IRQ: %d\n", err); 771 pr_err("PCIE: Failed to register IRQ: %d\n", err);
819 goto err_irq; 772 goto err_req_io;
820 } 773 }
821 set_irq_flags(INT_PCIE_INTR, IRQF_VALID); 774 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
822 775
823 return 0; 776 return 0;
824 777
825err_irq:
826 iounmap(tegra_pcie_io_base);
827err_map_io:
828 release_resource(&tegra_pcie.res_mmio);
829err_req_io: 778err_req_io:
830 iounmap(tegra_pcie.regs); 779 iounmap(tegra_pcie.regs);
831err_map_reg: 780err_map_reg:
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index cd8ea3588f93..ca7902c6ed18 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -169,11 +169,6 @@ static struct map_desc versatile_io_desc[] __initdata = {
169 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), 169 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
170 .length = VERSATILE_PCI_CFG_BASE_SIZE, 170 .length = VERSATILE_PCI_CFG_BASE_SIZE,
171 .type = MT_DEVICE 171 .type = MT_DEVICE
172 }, {
173 .virtual = (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
174 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
175 .length = IO_SPACE_LIMIT,
176 .type = MT_DEVICE
177 }, 172 },
178#endif 173#endif
179}; 174};
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 408e58da46c6..3e5d425e2a92 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -29,7 +29,6 @@
29 */ 29 */
30#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul 30#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
31#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul 31#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
32#define VERSATILE_PCI_VIRT_MEM_BASE0 (void __iomem *)PCIO_BASE
33 32
34/* macro to get at MMIO space when running virtually */ 33/* macro to get at MMIO space when running virtually */
35#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) 34#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
deleted file mode 100644
index 0406513be7d8..000000000000
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-versatile/include/mach/io.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#define PCIO_BASE 0xeb000000ul
24
25#define __io(a) ((a) + PCIO_BASE)
26
27#endif
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index e95bf84cc837..2f84f4094f13 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -169,13 +169,6 @@ static struct pci_ops pci_versatile_ops = {
169 .write = versatile_write_config, 169 .write = versatile_write_config,
170}; 170};
171 171
172static struct resource io_port = {
173 .name = "PCI",
174 .start = 0,
175 .end = IO_SPACE_LIMIT,
176 .flags = IORESOURCE_IO,
177};
178
179static struct resource io_mem = { 172static struct resource io_mem = {
180 .name = "PCI I/O space", 173 .name = "PCI I/O space",
181 .start = VERSATILE_PCI_MEM_BASE0, 174 .start = VERSATILE_PCI_MEM_BASE0,
@@ -207,12 +200,6 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
207 "memory region (%d)\n", ret); 200 "memory region (%d)\n", ret);
208 goto out; 201 goto out;
209 } 202 }
210 ret = request_resource(&ioport_resource, &io_port);
211 if (ret) {
212 printk(KERN_ERR "PCI: unable to allocate I/O "
213 "port region (%d)\n", ret);
214 goto out;
215 }
216 ret = request_resource(&iomem_resource, &non_mem); 203 ret = request_resource(&iomem_resource, &non_mem);
217 if (ret) { 204 if (ret) {
218 printk(KERN_ERR "PCI: unable to allocate non-prefetchable " 205 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -227,11 +214,9 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
227 } 214 }
228 215
229 /* 216 /*
230 * the IO resource for this bus
231 * the mem resource for this bus 217 * the mem resource for this bus
232 * the prefetch mem resource for this bus 218 * the prefetch mem resource for this bus
233 */ 219 */
234 pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
235 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); 220 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
236 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); 221 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
237 222
@@ -260,9 +245,11 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
260 goto out; 245 goto out;
261 } 246 }
262 247
248 ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
249 if (ret)
250 goto out;
251
263 if (nr == 0) { 252 if (nr == 0) {
264 sys->mem_offset = 0;
265 sys->io_offset = 0;
266 ret = pci_versatile_setup_resources(sys); 253 ret = pci_versatile_setup_resources(sys);
267 if (ret < 0) { 254 if (ret < 0) {
268 printk("pci_versatile_setup: resources... oops?\n"); 255 printk("pci_versatile_setup: resources... oops?\n");
@@ -319,7 +306,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
319 306
320void __init pci_versatile_preinit(void) 307void __init pci_versatile_preinit(void)
321{ 308{
322 pcibios_min_io = 0x44000000;
323 pcibios_min_mem = 0x50000000; 309 pcibios_min_mem = 0x50000000;
324 310
325 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); 311 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 566750fa57d4..9d869f93a3da 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -36,6 +36,7 @@
36#include <asm/system_info.h> 36#include <asm/system_info.h>
37 37
38#include <asm/mach/map.h> 38#include <asm/mach/map.h>
39#include <asm/mach/pci.h>
39#include "mm.h" 40#include "mm.h"
40 41
41int ioremap_page(unsigned long virt, unsigned long phys, 42int ioremap_page(unsigned long virt, unsigned long phys,
@@ -383,3 +384,16 @@ void __arm_iounmap(volatile void __iomem *io_addr)
383 arch_iounmap(io_addr); 384 arch_iounmap(io_addr);
384} 385}
385EXPORT_SYMBOL(__arm_iounmap); 386EXPORT_SYMBOL(__arm_iounmap);
387
388#ifdef CONFIG_PCI
389int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
390{
391 BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT);
392
393 return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
394 PCI_IO_VIRT_BASE + offset + SZ_64K,
395 phys_addr,
396 __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
397}
398EXPORT_SYMBOL_GPL(pci_ioremap_io);
399#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4c2d0451e84a..512b2c042ce1 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,6 +31,7 @@
31 31
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34#include <asm/mach/pci.h>
34 35
35#include "mm.h" 36#include "mm.h"
36 37
@@ -216,7 +217,7 @@ static struct mem_type mem_types[] = {
216 .prot_l1 = PMD_TYPE_TABLE, 217 .prot_l1 = PMD_TYPE_TABLE,
217 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 218 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
218 .domain = DOMAIN_IO, 219 .domain = DOMAIN_IO,
219 }, 220 },
220 [MT_DEVICE_WC] = { /* ioremap_wc */ 221 [MT_DEVICE_WC] = { /* ioremap_wc */
221 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 222 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
222 .prot_l1 = PMD_TYPE_TABLE, 223 .prot_l1 = PMD_TYPE_TABLE,
@@ -777,14 +778,27 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
777 create_mapping(md); 778 create_mapping(md);
778 vm->addr = (void *)(md->virtual & PAGE_MASK); 779 vm->addr = (void *)(md->virtual & PAGE_MASK);
779 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 780 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
780 vm->phys_addr = __pfn_to_phys(md->pfn); 781 vm->phys_addr = __pfn_to_phys(md->pfn);
781 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 782 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
782 vm->flags |= VM_ARM_MTYPE(md->type); 783 vm->flags |= VM_ARM_MTYPE(md->type);
783 vm->caller = iotable_init; 784 vm->caller = iotable_init;
784 vm_area_add_early(vm++); 785 vm_area_add_early(vm++);
785 } 786 }
786} 787}
787 788
789void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
790 void *caller)
791{
792 struct vm_struct *vm;
793
794 vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
795 vm->addr = (void *)addr;
796 vm->size = size;
797 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
798 vm->caller = caller;
799 vm_area_add_early(vm);
800}
801
788#ifndef CONFIG_ARM_LPAE 802#ifndef CONFIG_ARM_LPAE
789 803
790/* 804/*
@@ -802,14 +816,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr)
802 816
803static void __init pmd_empty_section_gap(unsigned long addr) 817static void __init pmd_empty_section_gap(unsigned long addr)
804{ 818{
805 struct vm_struct *vm; 819 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
806
807 vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
808 vm->addr = (void *)addr;
809 vm->size = SECTION_SIZE;
810 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
811 vm->caller = pmd_empty_section_gap;
812 vm_area_add_early(vm);
813} 820}
814 821
815static void __init fill_pmd_gaps(void) 822static void __init fill_pmd_gaps(void)
@@ -858,6 +865,28 @@ static void __init fill_pmd_gaps(void)
858#define fill_pmd_gaps() do { } while (0) 865#define fill_pmd_gaps() do { } while (0)
859#endif 866#endif
860 867
868#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
869static void __init pci_reserve_io(void)
870{
871 struct vm_struct *vm;
872 unsigned long addr;
873
874 /* we're still single threaded hence no lock needed here */
875 for (vm = vmlist; vm; vm = vm->next) {
876 if (!(vm->flags & VM_ARM_STATIC_MAPPING))
877 continue;
878 addr = (unsigned long)vm->addr;
879 addr &= ~(SZ_2M - 1);
880 if (addr == PCI_IO_VIRT_BASE)
881 return;
882
883 }
884 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
885}
886#else
887#define pci_reserve_io() do { } while (0)
888#endif
889
861static void * __initdata vmalloc_min = 890static void * __initdata vmalloc_min =
862 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 891 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
863 892
@@ -1141,6 +1170,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
1141 mdesc->map_io(); 1170 mdesc->map_io();
1142 fill_pmd_gaps(); 1171 fill_pmd_gaps();
1143 1172
1173 /* Reserve fixed i/o space in VMALLOC region */
1174 pci_reserve_io();
1175
1144 /* 1176 /*
1145 * Finally flush the caches and tlb to ensure that we're in a 1177 * Finally flush the caches and tlb to ensure that we're in a
1146 * consistent state wrt the writebuffer. This also ensures that 1178 * consistent state wrt the writebuffer. This also ensures that
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 8daae9b230ea..362474b5c40d 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -192,30 +192,24 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
192 if (nr != 0) 192 if (nr != 0)
193 return 0; 193 return 0;
194 194
195 res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL); 195 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
196 if (!res) 196 if (!res)
197 panic("PCI: unable to alloc resources"); 197 panic("PCI: unable to alloc resources");
198 198
199 res[0].start = IOP3XX_PCI_LOWER_IO_PA; 199 res->start = IOP3XX_PCI_LOWER_MEM_PA;
200 res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1; 200 res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
201 res[0].name = "IOP3XX PCI I/O Space"; 201 res->name = "IOP3XX PCI Memory Space";
202 res[0].flags = IORESOURCE_IO; 202 res->flags = IORESOURCE_MEM;
203 request_resource(&ioport_resource, &res[0]); 203 request_resource(&iomem_resource, res);
204
205 res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
206 res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
207 res[1].name = "IOP3XX PCI Memory Space";
208 res[1].flags = IORESOURCE_MEM;
209 request_resource(&iomem_resource, &res[1]);
210 204
211 /* 205 /*
212 * Use whatever translation is already setup. 206 * Use whatever translation is already setup.
213 */ 207 */
214 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; 208 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
215 sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
216 209
217 pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); 210 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
218 pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); 211
212 pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
219 213
220 return 1; 214 return 1;
221} 215}
@@ -367,7 +361,6 @@ void __init iop3xx_pci_preinit_cond(void)
367 361
368void __init iop3xx_pci_preinit(void) 362void __init iop3xx_pci_preinit(void)
369{ 363{
370 pcibios_min_io = 0;
371 pcibios_min_mem = 0; 364 pcibios_min_mem = 0;
372 365
373 iop3xx_atu_disable(); 366 iop3xx_atu_disable();
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
index bade586fed0f..5b217f460f18 100644
--- a/arch/arm/plat-iop/setup.c
+++ b/arch/arm/plat-iop/setup.c
@@ -25,11 +25,6 @@ static struct map_desc iop3xx_std_desc[] __initdata = {
25 .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), 25 .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
26 .length = IOP3XX_PERIPHERAL_SIZE, 26 .length = IOP3XX_PERIPHERAL_SIZE,
27 .type = MT_UNCACHED, 27 .type = MT_UNCACHED,
28 }, { /* PCI IO space */
29 .virtual = IOP3XX_PCI_LOWER_IO_VA,
30 .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
31 .length = IOP3XX_PCI_IO_WINDOW_SIZE,
32 .type = MT_DEVICE,
33 }, 28 },
34}; 29};
35 30
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 93f147a96b62..2f99613fd677 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -4,13 +4,13 @@
4/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd 4/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com> 5 * <Peter dot Milne at D hyphen TACQ dot com>
6 * 6 *
7 * With acknowledgements to i2c-algo-ibm_ocp.c by 7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com 8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
9 * 9 *
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund: 10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
11 * 11 *
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund 12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
13 * 13 *
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>, 14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com> 15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
16 * 16 *
@@ -39,14 +39,15 @@
39#include <linux/platform_device.h> 39#include <linux/platform_device.h>
40#include <linux/i2c.h> 40#include <linux/i2c.h>
41#include <linux/io.h> 41#include <linux/io.h>
42#include <linux/gpio.h>
42 43
43#include "i2c-iop3xx.h" 44#include "i2c-iop3xx.h"
44 45
45/* global unit counter */ 46/* global unit counter */
46static int i2c_id; 47static int i2c_id;
47 48
48static inline unsigned char 49static inline unsigned char
49iic_cook_addr(struct i2c_msg *msg) 50iic_cook_addr(struct i2c_msg *msg)
50{ 51{
51 unsigned char addr; 52 unsigned char addr;
52 53
@@ -55,38 +56,38 @@ iic_cook_addr(struct i2c_msg *msg)
55 if (msg->flags & I2C_M_RD) 56 if (msg->flags & I2C_M_RD)
56 addr |= 1; 57 addr |= 1;
57 58
58 return addr; 59 return addr;
59} 60}
60 61
61static void 62static void
62iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap) 63iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
63{ 64{
64 /* Follows devman 9.3 */ 65 /* Follows devman 9.3 */
65 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET); 66 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
66 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET); 67 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
67 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); 68 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
68} 69}
69 70
70static void 71static void
71iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) 72iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
72{ 73{
73 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; 74 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
74 75
75 /* 76 /*
76 * Every time unit enable is asserted, GPOD needs to be cleared 77 * Every time unit enable is asserted, GPOD needs to be cleared
77 * on IOP3XX to avoid data corruption on the bus. 78 * on IOP3XX to avoid data corruption on the bus.
78 */ 79 */
79#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X) 80#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
80 if (iop3xx_adap->id == 0) { 81 if (iop3xx_adap->id == 0) {
81 gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW); 82 gpio_set_value(7, 0);
82 gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW); 83 gpio_set_value(6, 0);
83 } else { 84 } else {
84 gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW); 85 gpio_set_value(5, 0);
85 gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW); 86 gpio_set_value(4, 0);
86 } 87 }
87#endif 88#endif
88 /* NB SR bits not same position as CR IE bits :-( */ 89 /* NB SR bits not same position as CR IE bits :-( */
89 iop3xx_adap->SR_enabled = 90 iop3xx_adap->SR_enabled =
90 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD | 91 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
91 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY; 92 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
92 93
@@ -96,23 +97,23 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
96 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 97 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
97} 98}
98 99
99static void 100static void
100iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap) 101iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
101{ 102{
102 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 103 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
103 104
104 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 105 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
105 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN); 106 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
106 107
107 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 108 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
108} 109}
109 110
110/* 111/*
111 * NB: the handler has to clear the source of the interrupt! 112 * NB: the handler has to clear the source of the interrupt!
112 * Then it passes the SR flags of interest to BH via adap data 113 * Then it passes the SR flags of interest to BH via adap data
113 */ 114 */
114static irqreturn_t 115static irqreturn_t
115iop3xx_i2c_irq_handler(int this_irq, void *dev_id) 116iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
116{ 117{
117 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id; 118 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
118 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); 119 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
@@ -126,7 +127,7 @@ iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
126} 127}
127 128
128/* check all error conditions, clear them , report most important */ 129/* check all error conditions, clear them , report most important */
129static int 130static int
130iop3xx_i2c_error(u32 sr) 131iop3xx_i2c_error(u32 sr)
131{ 132{
132 int rc = 0; 133 int rc = 0;
@@ -135,12 +136,12 @@ iop3xx_i2c_error(u32 sr)
135 if ( !rc ) rc = -I2C_ERR_BERR; 136 if ( !rc ) rc = -I2C_ERR_BERR;
136 } 137 }
137 if ((sr & IOP3XX_ISR_ALD)) { 138 if ((sr & IOP3XX_ISR_ALD)) {
138 if ( !rc ) rc = -I2C_ERR_ALD; 139 if ( !rc ) rc = -I2C_ERR_ALD;
139 } 140 }
140 return rc; 141 return rc;
141} 142}
142 143
143static inline u32 144static inline u32
144iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) 145iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
145{ 146{
146 unsigned long flags; 147 unsigned long flags;
@@ -161,8 +162,8 @@ iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
161typedef int (* compare_func)(unsigned test, unsigned mask); 162typedef int (* compare_func)(unsigned test, unsigned mask);
162/* returns 1 on correct comparison */ 163/* returns 1 on correct comparison */
163 164
164static int 165static int
165iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 166iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
166 unsigned flags, unsigned* status, 167 unsigned flags, unsigned* status,
167 compare_func compare) 168 compare_func compare)
168{ 169{
@@ -192,47 +193,47 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
192} 193}
193 194
194/* 195/*
195 * Concrete compare_funcs 196 * Concrete compare_funcs
196 */ 197 */
197static int 198static int
198all_bits_clear(unsigned test, unsigned mask) 199all_bits_clear(unsigned test, unsigned mask)
199{ 200{
200 return (test & mask) == 0; 201 return (test & mask) == 0;
201} 202}
202 203
203static int 204static int
204any_bits_set(unsigned test, unsigned mask) 205any_bits_set(unsigned test, unsigned mask)
205{ 206{
206 return (test & mask) != 0; 207 return (test & mask) != 0;
207} 208}
208 209
209static int 210static int
210iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 211iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
211{ 212{
212 return iop3xx_i2c_wait_event( 213 return iop3xx_i2c_wait_event(
213 iop3xx_adap, 214 iop3xx_adap,
214 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 215 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
215 status, any_bits_set); 216 status, any_bits_set);
216} 217}
217 218
218static int 219static int
219iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 220iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
220{ 221{
221 return iop3xx_i2c_wait_event( 222 return iop3xx_i2c_wait_event(
222 iop3xx_adap, 223 iop3xx_adap,
223 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 224 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
224 status, any_bits_set); 225 status, any_bits_set);
225} 226}
226 227
227static int 228static int
228iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 229iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
229{ 230{
230 return iop3xx_i2c_wait_event( 231 return iop3xx_i2c_wait_event(
231 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear); 232 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
232} 233}
233 234
234static int 235static int
235iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 236iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
236 struct i2c_msg* msg) 237 struct i2c_msg* msg)
237{ 238{
238 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 239 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -247,7 +248,7 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
247 } 248 }
248 249
249 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); 250 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
250 251
251 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); 252 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
252 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; 253 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
253 254
@@ -257,8 +258,8 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
257 return rc; 258 return rc;
258} 259}
259 260
260static int 261static int
261iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 262iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
262 int stop) 263 int stop)
263{ 264{
264 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 265 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -277,10 +278,10 @@ iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
277 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status); 278 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
278 279
279 return rc; 280 return rc;
280} 281}
281 282
282static int 283static int
283iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 284iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
284 int stop) 285 int stop)
285{ 286{
286 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 287 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -304,19 +305,19 @@ iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
304 return rc; 305 return rc;
305} 306}
306 307
307static int 308static int
308iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count) 309iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
309{ 310{
310 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 311 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
311 int ii; 312 int ii;
312 int rc = 0; 313 int rc = 0;
313 314
314 for (ii = 0; rc == 0 && ii != count; ++ii) 315 for (ii = 0; rc == 0 && ii != count; ++ii)
315 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1); 316 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
316 return rc; 317 return rc;
317} 318}
318 319
319static int 320static int
320iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) 321iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
321{ 322{
322 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 323 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -325,7 +326,7 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
325 326
326 for (ii = 0; rc == 0 && ii != count; ++ii) 327 for (ii = 0; rc == 0 && ii != count; ++ii)
327 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1); 328 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
328 329
329 return rc; 330 return rc;
330} 331}
331 332
@@ -336,8 +337,8 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
336 * Each transfer (i.e. a read or a write) is separated by a repeated start 337 * Each transfer (i.e. a read or a write) is separated by a repeated start
337 * condition. 338 * condition.
338 */ 339 */
339static int 340static int
340iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 341iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
341{ 342{
342 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 343 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
343 int rc; 344 int rc;
@@ -357,8 +358,8 @@ iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
357/* 358/*
358 * master_xfer() - main read/write entry 359 * master_xfer() - main read/write entry
359 */ 360 */
360static int 361static int
361iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 362iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
362 int num) 363 int num)
363{ 364{
364 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 365 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -375,14 +376,14 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
375 } 376 }
376 377
377 iop3xx_i2c_transaction_cleanup(iop3xx_adap); 378 iop3xx_i2c_transaction_cleanup(iop3xx_adap);
378 379
379 if(ret) 380 if(ret)
380 return ret; 381 return ret;
381 382
382 return im; 383 return im;
383} 384}
384 385
385static u32 386static u32
386iop3xx_i2c_func(struct i2c_adapter *adap) 387iop3xx_i2c_func(struct i2c_adapter *adap)
387{ 388{
388 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 389 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -393,11 +394,11 @@ static const struct i2c_algorithm iop3xx_i2c_algo = {
393 .functionality = iop3xx_i2c_func, 394 .functionality = iop3xx_i2c_func,
394}; 395};
395 396
396static int 397static int
397iop3xx_i2c_remove(struct platform_device *pdev) 398iop3xx_i2c_remove(struct platform_device *pdev)
398{ 399{
399 struct i2c_adapter *padapter = platform_get_drvdata(pdev); 400 struct i2c_adapter *padapter = platform_get_drvdata(pdev);
400 struct i2c_algo_iop3xx_data *adapter_data = 401 struct i2c_algo_iop3xx_data *adapter_data =
401 (struct i2c_algo_iop3xx_data *)padapter->algo_data; 402 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
402 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 403 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); 404 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
@@ -419,7 +420,7 @@ iop3xx_i2c_remove(struct platform_device *pdev)
419 return 0; 420 return 0;
420} 421}
421 422
422static int 423static int
423iop3xx_i2c_probe(struct platform_device *pdev) 424iop3xx_i2c_probe(struct platform_device *pdev)
424{ 425{
425 struct resource *res; 426 struct resource *res;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 05:15:35 -0400