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authorBen Widawsky <benjamin.widawsky@intel.com>2012-09-21 20:01:20 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-26 03:24:36 -0400
commit199adf40ae29a563ba0afe924e12802271defcc8 (patch)
treeaa7a2ef58b34145470ed9b0187bdc9e76ae7875d
parentadf00b26d18e1b3570451296e03bcb20e4798cdd (diff)
drm/i915: s/cacheing/caching/
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c4
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h8
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c20
-rw-r--r--include/drm/i915_drm.h20
4 files changed, 26 insertions, 26 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 491394fd94cd..ffbc9156c792 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1868,8 +1868,8 @@ struct drm_ioctl_desc i915_ioctls[] = {
1868 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 1868 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1869 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 1869 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1870 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 1870 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1871 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHEING, i915_gem_set_cacheing_ioctl, DRM_UNLOCKED), 1871 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1872 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHEING, i915_gem_get_cacheing_ioctl, DRM_UNLOCKED), 1872 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1873 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), 1873 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1874 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1874 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1875 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 1875 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index af5ceb46e7bd..4f2831aa5fed 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1301,10 +1301,10 @@ int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1301 struct drm_file *file_priv); 1301 struct drm_file *file_priv);
1302int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1302int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1303 struct drm_file *file_priv); 1303 struct drm_file *file_priv);
1304int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data, 1304int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1305 struct drm_file *file); 1305 struct drm_file *file);
1306int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data, 1306int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1307 struct drm_file *file); 1307 struct drm_file *file);
1308int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1308int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1309 struct drm_file *file_priv); 1309 struct drm_file *file_priv);
1310int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1310int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2f76905ab2b0..365a7dc8a4a8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3185,10 +3185,10 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3185 return 0; 3185 return 0;
3186} 3186}
3187 3187
3188int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data, 3188int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3189 struct drm_file *file) 3189 struct drm_file *file)
3190{ 3190{
3191 struct drm_i915_gem_cacheing *args = data; 3191 struct drm_i915_gem_caching *args = data;
3192 struct drm_i915_gem_object *obj; 3192 struct drm_i915_gem_object *obj;
3193 int ret; 3193 int ret;
3194 3194
@@ -3202,7 +3202,7 @@ int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data,
3202 goto unlock; 3202 goto unlock;
3203 } 3203 }
3204 3204
3205 args->cacheing = obj->cache_level != I915_CACHE_NONE; 3205 args->caching = obj->cache_level != I915_CACHE_NONE;
3206 3206
3207 drm_gem_object_unreference(&obj->base); 3207 drm_gem_object_unreference(&obj->base);
3208unlock: 3208unlock:
@@ -3210,10 +3210,10 @@ unlock:
3210 return ret; 3210 return ret;
3211} 3211}
3212 3212
3213int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data, 3213int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3214 struct drm_file *file) 3214 struct drm_file *file)
3215{ 3215{
3216 struct drm_i915_gem_cacheing *args = data; 3216 struct drm_i915_gem_caching *args = data;
3217 struct drm_i915_gem_object *obj; 3217 struct drm_i915_gem_object *obj;
3218 enum i915_cache_level level; 3218 enum i915_cache_level level;
3219 int ret; 3219 int ret;
@@ -3222,11 +3222,11 @@ int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data,
3222 if (ret) 3222 if (ret)
3223 return ret; 3223 return ret;
3224 3224
3225 switch (args->cacheing) { 3225 switch (args->caching) {
3226 case I915_CACHEING_NONE: 3226 case I915_CACHING_NONE:
3227 level = I915_CACHE_NONE; 3227 level = I915_CACHE_NONE;
3228 break; 3228 break;
3229 case I915_CACHEING_CACHED: 3229 case I915_CACHING_CACHED:
3230 level = I915_CACHE_LLC; 3230 level = I915_CACHE_LLC;
3231 break; 3231 break;
3232 default: 3232 default:
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index c8833009f37b..e737607e055e 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -203,8 +203,8 @@ typedef struct _drm_i915_sarea {
203#define DRM_I915_GEM_WAIT 0x2c 203#define DRM_I915_GEM_WAIT 0x2c
204#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 204#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
205#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 205#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
206#define DRM_I915_GEM_SET_CACHEING 0x2f 206#define DRM_I915_GEM_SET_CACHING 0x2f
207#define DRM_I915_GEM_GET_CACHEING 0x30 207#define DRM_I915_GEM_GET_CACHING 0x30
208#define DRM_I915_REG_READ 0x31 208#define DRM_I915_REG_READ 0x31
209 209
210#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 210#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -230,8 +230,8 @@ typedef struct _drm_i915_sarea {
230#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 230#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
231#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 231#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
232#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 232#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
233#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) 233#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
234#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) 234#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
235#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 235#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
236#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 236#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
237#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 237#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
@@ -715,21 +715,21 @@ struct drm_i915_gem_busy {
715 __u32 busy; 715 __u32 busy;
716}; 716};
717 717
718#define I915_CACHEING_NONE 0 718#define I915_CACHING_NONE 0
719#define I915_CACHEING_CACHED 1 719#define I915_CACHING_CACHED 1
720 720
721struct drm_i915_gem_cacheing { 721struct drm_i915_gem_caching {
722 /** 722 /**
723 * Handle of the buffer to set/get the cacheing level of. */ 723 * Handle of the buffer to set/get the caching level of. */
724 __u32 handle; 724 __u32 handle;
725 725
726 /** 726 /**
727 * Cacheing level to apply or return value 727 * Cacheing level to apply or return value
728 * 728 *
729 * bits0-15 are for generic cacheing control (i.e. the above defined 729 * bits0-15 are for generic caching control (i.e. the above defined
730 * values). bits16-31 are reserved for platform-specific variations 730 * values). bits16-31 are reserved for platform-specific variations
731 * (e.g. l3$ caching on gen7). */ 731 * (e.g. l3$ caching on gen7). */
732 __u32 cacheing; 732 __u32 caching;
733}; 733};
734 734
735#define I915_TILING_NONE 0 735#define I915_TILING_NONE 0