diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2014-09-14 23:45:30 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-11-12 11:56:35 -0500 |
commit | 1955f107a7bf5c9f718bf5025a24f5ff1607d7b2 (patch) | |
tree | 25c53127ceb9140513ce3cb8b087860afc8225b6 | |
parent | 2271e2e2a2525f826549f1aa19db36e0b80082fe (diff) |
drm/radeon: rework CI dpm thermal setup
In preparation for fan control.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/ci_dpm.c | 70 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ppsmc.h | 4 |
2 files changed, 53 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 11a55e9dad7f..51bf7980bd6a 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c | |||
@@ -814,7 +814,7 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, | |||
814 | } | 814 | } |
815 | } | 815 | } |
816 | 816 | ||
817 | static int ci_set_thermal_temperature_range(struct radeon_device *rdev, | 817 | static int ci_thermal_set_temperature_range(struct radeon_device *rdev, |
818 | int min_temp, int max_temp) | 818 | int min_temp, int max_temp) |
819 | { | 819 | { |
820 | int low_temp = 0 * 1000; | 820 | int low_temp = 0 * 1000; |
@@ -850,6 +850,35 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev, | |||
850 | return 0; | 850 | return 0; |
851 | } | 851 | } |
852 | 852 | ||
853 | static int ci_thermal_enable_alert(struct radeon_device *rdev, | ||
854 | bool enable) | ||
855 | { | ||
856 | u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); | ||
857 | PPSMC_Result result; | ||
858 | |||
859 | if (enable) { | ||
860 | thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | ||
861 | rdev->irq.dpm_thermal = false; | ||
862 | result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable); | ||
863 | if (result != PPSMC_Result_OK) { | ||
864 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); | ||
865 | return -EINVAL; | ||
866 | } | ||
867 | } else { | ||
868 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; | ||
869 | rdev->irq.dpm_thermal = true; | ||
870 | result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable); | ||
871 | if (result != PPSMC_Result_OK) { | ||
872 | DRM_DEBUG_KMS("Could not disable thermal interrupts.\n"); | ||
873 | return -EINVAL; | ||
874 | } | ||
875 | } | ||
876 | |||
877 | WREG32_SMC(CG_THERMAL_INT, thermal_int); | ||
878 | |||
879 | return 0; | ||
880 | } | ||
881 | |||
853 | #if 0 | 882 | #if 0 |
854 | static int ci_read_smc_soft_register(struct radeon_device *rdev, | 883 | static int ci_read_smc_soft_register(struct radeon_device *rdev, |
855 | u16 reg_offset, u32 *value) | 884 | u16 reg_offset, u32 *value) |
@@ -4682,29 +4711,30 @@ int ci_dpm_enable(struct radeon_device *rdev) | |||
4682 | return 0; | 4711 | return 0; |
4683 | } | 4712 | } |
4684 | 4713 | ||
4685 | int ci_dpm_late_enable(struct radeon_device *rdev) | 4714 | static int ci_set_temperature_range(struct radeon_device *rdev) |
4686 | { | 4715 | { |
4687 | int ret; | 4716 | int ret; |
4688 | 4717 | ||
4689 | if (rdev->irq.installed && | 4718 | ret = ci_thermal_enable_alert(rdev, false); |
4690 | r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { | 4719 | if (ret) |
4691 | #if 0 | 4720 | return ret; |
4692 | PPSMC_Result result; | 4721 | ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); |
4693 | #endif | 4722 | if (ret) |
4694 | ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); | 4723 | return ret; |
4695 | if (ret) { | 4724 | ret = ci_thermal_enable_alert(rdev, true); |
4696 | DRM_ERROR("ci_set_thermal_temperature_range failed\n"); | 4725 | if (ret) |
4697 | return ret; | 4726 | return ret; |
4698 | } | ||
4699 | rdev->irq.dpm_thermal = true; | ||
4700 | radeon_irq_set(rdev); | ||
4701 | #if 0 | ||
4702 | result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); | ||
4703 | 4727 | ||
4704 | if (result != PPSMC_Result_OK) | 4728 | return ret; |
4705 | DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); | 4729 | } |
4706 | #endif | 4730 | |
4707 | } | 4731 | int ci_dpm_late_enable(struct radeon_device *rdev) |
4732 | { | ||
4733 | int ret; | ||
4734 | |||
4735 | ret = ci_set_temperature_range(rdev); | ||
4736 | if (ret) | ||
4737 | return ret; | ||
4708 | 4738 | ||
4709 | ci_dpm_powergate_uvd(rdev, true); | 4739 | ci_dpm_powergate_uvd(rdev, true); |
4710 | 4740 | ||
diff --git a/drivers/gpu/drm/radeon/ppsmc.h b/drivers/gpu/drm/radeon/ppsmc.h index 5670b8291285..11c0e4d5c0bf 100644 --- a/drivers/gpu/drm/radeon/ppsmc.h +++ b/drivers/gpu/drm/radeon/ppsmc.h | |||
@@ -106,6 +106,7 @@ typedef uint8_t PPSMC_Result; | |||
106 | #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) | 106 | #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) |
107 | #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) | 107 | #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) |
108 | #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) | 108 | #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) |
109 | #define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) | ||
109 | #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) | 110 | #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) |
110 | #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) | 111 | #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) |
111 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) | 112 | #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) |
@@ -157,10 +158,11 @@ typedef uint8_t PPSMC_Result; | |||
157 | #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) | 158 | #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) |
158 | #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) | 159 | #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) |
159 | #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) | 160 | #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) |
160 | #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) | 161 | #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a) |
161 | #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) | 162 | #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) |
162 | #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) | 163 | #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) |
163 | #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) | 164 | #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) |
165 | #define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) | ||
164 | #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) | 166 | #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) |
165 | #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) | 167 | #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) |
166 | #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) | 168 | #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) |