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authorAbhijeet Dharmapurikar <adharmap@codeaurora.org>2010-05-20 18:20:23 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-06-04 16:37:16 -0400
commit18c79d76ece432a48c985ea404800f8ee154ada2 (patch)
tree864f598be56999e4437e01a413d1c72beb78d75e
parentad8456361fa19068cf49b50a4f98e41b73c08e76 (diff)
msm_serial: fix serial on trout
Set the mnd counter based on uartclk. This fixes a problem on 7x30 where the uartclk is 19.2Mhz rather than the usual 4.8Mhz. Trout incorrectly reports uartclk to be running at 19.2Mhz It is actually running at 4.8Mhz. For trout force mnd counter values as if uartclk was fed by tcxo/4. Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> [dwalker@codeaurora.org: inlined, moved into header, added comments.] Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/serial/msm_serial.c21
-rw-r--r--drivers/serial/msm_serial.h56
2 files changed, 59 insertions, 18 deletions
diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c
index ecdc0facf7ee..f8c816e7725d 100644
--- a/drivers/serial/msm_serial.c
+++ b/drivers/serial/msm_serial.c
@@ -41,19 +41,6 @@ struct msm_port {
41 unsigned int imr; 41 unsigned int imr;
42}; 42};
43 43
44#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
45
46static inline void msm_write(struct uart_port *port, unsigned int val,
47 unsigned int off)
48{
49 __raw_writel(val, port->membase + off);
50}
51
52static inline unsigned int msm_read(struct uart_port *port, unsigned int off)
53{
54 return __raw_readl(port->membase + off);
55}
56
57static void msm_stop_tx(struct uart_port *port) 44static void msm_stop_tx(struct uart_port *port)
58{ 45{
59 struct msm_port *msm_port = UART_TO_MSM(port); 46 struct msm_port *msm_port = UART_TO_MSM(port);
@@ -320,11 +307,7 @@ static void msm_init_clock(struct uart_port *port)
320 struct msm_port *msm_port = UART_TO_MSM(port); 307 struct msm_port *msm_port = UART_TO_MSM(port);
321 308
322 clk_enable(msm_port->clk); 309 clk_enable(msm_port->clk);
323 310 msm_serial_set_mnd_regs(port);
324 msm_write(port, 0xC0, UART_MREG);
325 msm_write(port, 0xB2, UART_NREG);
326 msm_write(port, 0x7D, UART_DREG);
327 msm_write(port, 0x1C, UART_MNDREG);
328} 311}
329 312
330static int msm_startup(struct uart_port *port) 313static int msm_startup(struct uart_port *port)
@@ -706,6 +689,8 @@ static int __init msm_serial_probe(struct platform_device *pdev)
706 if (unlikely(IS_ERR(msm_port->clk))) 689 if (unlikely(IS_ERR(msm_port->clk)))
707 return PTR_ERR(msm_port->clk); 690 return PTR_ERR(msm_port->clk);
708 port->uartclk = clk_get_rate(msm_port->clk); 691 port->uartclk = clk_get_rate(msm_port->clk);
692 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
693
709 694
710 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 695 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 if (unlikely(!resource)) 696 if (unlikely(!resource))
diff --git a/drivers/serial/msm_serial.h b/drivers/serial/msm_serial.h
index 689f1fa0e84e..f6ca9ca79e98 100644
--- a/drivers/serial/msm_serial.h
+++ b/drivers/serial/msm_serial.h
@@ -114,4 +114,60 @@
114#define UART_MISR 0x0010 114#define UART_MISR 0x0010
115#define UART_ISR 0x0014 115#define UART_ISR 0x0014
116 116
117#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
118
119static inline
120void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
121{
122 __raw_writel(val, port->membase + off);
123}
124
125static inline
126unsigned int msm_read(struct uart_port *port, unsigned int off)
127{
128 return __raw_readl(port->membase + off);
129}
130
131/*
132 * Setup the MND registers to use the TCXO clock.
133 */
134static inline void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
135{
136 msm_write(port, 0x06, UART_MREG);
137 msm_write(port, 0xF1, UART_NREG);
138 msm_write(port, 0x0F, UART_DREG);
139 msm_write(port, 0x1A, UART_MNDREG);
140}
141
142/*
143 * Setup the MND registers to use the TCXO clock divided by 4.
144 */
145static inline void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
146{
147 msm_write(port, 0x18, UART_MREG);
148 msm_write(port, 0xF6, UART_NREG);
149 msm_write(port, 0x0F, UART_DREG);
150 msm_write(port, 0x0A, UART_MNDREG);
151}
152
153static inline
154void msm_serial_set_mnd_regs_from_uartclk(struct uart_port *port)
155{
156 if (port->uartclk == 19200000)
157 msm_serial_set_mnd_regs_tcxo(port);
158 else
159 msm_serial_set_mnd_regs_tcxoby4(port);
160}
161
162/*
163 * TROUT has a specific defect that makes it report it's uartclk
164 * as 19.2Mhz (TCXO) when it's actually 4.8Mhz (TCXO/4). This special
165 * cases TROUT to use the right clock.
166 */
167#ifdef CONFIG_MACH_TROUT
168#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_tcxoby4
169#else
170#define msm_serial_set_mnd_regs msm_serial_set_mnd_regs_from_uartclk
171#endif
172
117#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */ 173#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */