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authorAlex Deucher <alexander.deucher@amd.com>2014-10-01 09:25:27 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-03-19 12:26:38 -0400
commit18b53e905756930d6d4e691e1e1c3b43dba0c973 (patch)
tree27c46efa97ac823fecbe9e034ac42d2817a8e4d1
parent4ce4728b5113245c731ac3baef36dce0482cce0c (diff)
drm/radeon: add get_allowed_info_register function for r1xx-r5xx
Just a stub. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 466a7715e286..558be7a88b2f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -136,6 +136,11 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
136 } 136 }
137} 137}
138 138
139static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
140 u32 reg, u32 *val)
141{
142 return -EINVAL;
143}
139 144
140/* helper to disable agp */ 145/* helper to disable agp */
141/** 146/**
@@ -199,6 +204,7 @@ static struct radeon_asic r100_asic = {
199 .mmio_hdp_flush = NULL, 204 .mmio_hdp_flush = NULL,
200 .gui_idle = &r100_gui_idle, 205 .gui_idle = &r100_gui_idle,
201 .mc_wait_for_idle = &r100_mc_wait_for_idle, 206 .mc_wait_for_idle = &r100_mc_wait_for_idle,
207 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
202 .gart = { 208 .gart = {
203 .tlb_flush = &r100_pci_gart_tlb_flush, 209 .tlb_flush = &r100_pci_gart_tlb_flush,
204 .get_page_entry = &r100_pci_gart_get_page_entry, 210 .get_page_entry = &r100_pci_gart_get_page_entry,
@@ -266,6 +272,7 @@ static struct radeon_asic r200_asic = {
266 .mmio_hdp_flush = NULL, 272 .mmio_hdp_flush = NULL,
267 .gui_idle = &r100_gui_idle, 273 .gui_idle = &r100_gui_idle,
268 .mc_wait_for_idle = &r100_mc_wait_for_idle, 274 .mc_wait_for_idle = &r100_mc_wait_for_idle,
275 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
269 .gart = { 276 .gart = {
270 .tlb_flush = &r100_pci_gart_tlb_flush, 277 .tlb_flush = &r100_pci_gart_tlb_flush,
271 .get_page_entry = &r100_pci_gart_get_page_entry, 278 .get_page_entry = &r100_pci_gart_get_page_entry,
@@ -361,6 +368,7 @@ static struct radeon_asic r300_asic = {
361 .mmio_hdp_flush = NULL, 368 .mmio_hdp_flush = NULL,
362 .gui_idle = &r100_gui_idle, 369 .gui_idle = &r100_gui_idle,
363 .mc_wait_for_idle = &r300_mc_wait_for_idle, 370 .mc_wait_for_idle = &r300_mc_wait_for_idle,
371 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
364 .gart = { 372 .gart = {
365 .tlb_flush = &r100_pci_gart_tlb_flush, 373 .tlb_flush = &r100_pci_gart_tlb_flush,
366 .get_page_entry = &r100_pci_gart_get_page_entry, 374 .get_page_entry = &r100_pci_gart_get_page_entry,
@@ -428,6 +436,7 @@ static struct radeon_asic r300_asic_pcie = {
428 .mmio_hdp_flush = NULL, 436 .mmio_hdp_flush = NULL,
429 .gui_idle = &r100_gui_idle, 437 .gui_idle = &r100_gui_idle,
430 .mc_wait_for_idle = &r300_mc_wait_for_idle, 438 .mc_wait_for_idle = &r300_mc_wait_for_idle,
439 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
431 .gart = { 440 .gart = {
432 .tlb_flush = &rv370_pcie_gart_tlb_flush, 441 .tlb_flush = &rv370_pcie_gart_tlb_flush,
433 .get_page_entry = &rv370_pcie_gart_get_page_entry, 442 .get_page_entry = &rv370_pcie_gart_get_page_entry,
@@ -495,6 +504,7 @@ static struct radeon_asic r420_asic = {
495 .mmio_hdp_flush = NULL, 504 .mmio_hdp_flush = NULL,
496 .gui_idle = &r100_gui_idle, 505 .gui_idle = &r100_gui_idle,
497 .mc_wait_for_idle = &r300_mc_wait_for_idle, 506 .mc_wait_for_idle = &r300_mc_wait_for_idle,
507 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
498 .gart = { 508 .gart = {
499 .tlb_flush = &rv370_pcie_gart_tlb_flush, 509 .tlb_flush = &rv370_pcie_gart_tlb_flush,
500 .get_page_entry = &rv370_pcie_gart_get_page_entry, 510 .get_page_entry = &rv370_pcie_gart_get_page_entry,
@@ -562,6 +572,7 @@ static struct radeon_asic rs400_asic = {
562 .mmio_hdp_flush = NULL, 572 .mmio_hdp_flush = NULL,
563 .gui_idle = &r100_gui_idle, 573 .gui_idle = &r100_gui_idle,
564 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 574 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
575 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
565 .gart = { 576 .gart = {
566 .tlb_flush = &rs400_gart_tlb_flush, 577 .tlb_flush = &rs400_gart_tlb_flush,
567 .get_page_entry = &rs400_gart_get_page_entry, 578 .get_page_entry = &rs400_gart_get_page_entry,
@@ -629,6 +640,7 @@ static struct radeon_asic rs600_asic = {
629 .mmio_hdp_flush = NULL, 640 .mmio_hdp_flush = NULL,
630 .gui_idle = &r100_gui_idle, 641 .gui_idle = &r100_gui_idle,
631 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 642 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
643 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
632 .gart = { 644 .gart = {
633 .tlb_flush = &rs600_gart_tlb_flush, 645 .tlb_flush = &rs600_gart_tlb_flush,
634 .get_page_entry = &rs600_gart_get_page_entry, 646 .get_page_entry = &rs600_gart_get_page_entry,
@@ -696,6 +708,7 @@ static struct radeon_asic rs690_asic = {
696 .mmio_hdp_flush = NULL, 708 .mmio_hdp_flush = NULL,
697 .gui_idle = &r100_gui_idle, 709 .gui_idle = &r100_gui_idle,
698 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 710 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
711 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
699 .gart = { 712 .gart = {
700 .tlb_flush = &rs400_gart_tlb_flush, 713 .tlb_flush = &rs400_gart_tlb_flush,
701 .get_page_entry = &rs400_gart_get_page_entry, 714 .get_page_entry = &rs400_gart_get_page_entry,
@@ -763,6 +776,7 @@ static struct radeon_asic rv515_asic = {
763 .mmio_hdp_flush = NULL, 776 .mmio_hdp_flush = NULL,
764 .gui_idle = &r100_gui_idle, 777 .gui_idle = &r100_gui_idle,
765 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 778 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
779 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
766 .gart = { 780 .gart = {
767 .tlb_flush = &rv370_pcie_gart_tlb_flush, 781 .tlb_flush = &rv370_pcie_gart_tlb_flush,
768 .get_page_entry = &rv370_pcie_gart_get_page_entry, 782 .get_page_entry = &rv370_pcie_gart_get_page_entry,
@@ -830,6 +844,7 @@ static struct radeon_asic r520_asic = {
830 .mmio_hdp_flush = NULL, 844 .mmio_hdp_flush = NULL,
831 .gui_idle = &r100_gui_idle, 845 .gui_idle = &r100_gui_idle,
832 .mc_wait_for_idle = &r520_mc_wait_for_idle, 846 .mc_wait_for_idle = &r520_mc_wait_for_idle,
847 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
833 .gart = { 848 .gart = {
834 .tlb_flush = &rv370_pcie_gart_tlb_flush, 849 .tlb_flush = &rv370_pcie_gart_tlb_flush,
835 .get_page_entry = &rv370_pcie_gart_get_page_entry, 850 .get_page_entry = &rv370_pcie_gart_get_page_entry,