aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPaul Bolle <pebolle@tiscali.nl>2012-06-13 03:47:19 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-06-21 13:43:04 -0400
commit17bd27bd78b59f7cbe0ff2cb8bb0e473260a9801 (patch)
tree2c5c49c8b775f307cc78111388ac99ed03c28ed2
parentc8dce0088a645c21cfb7e554390a4603e0e2139f (diff)
[media] stradis: remove unused V4L1 headers
Commit 39c3d488452ae206cfc8afda0db041ee55d01c3c ("[media] cpia, stradis: remove deprecated V4L1 drivers") removed the last file including these five headers. Apparently it was just an oversight to keep them in the tree. They can safely be removed now. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/video/cs8420.h50
-rw-r--r--drivers/media/video/ibmmpeg2.h94
-rw-r--r--drivers/media/video/saa7121.h132
-rw-r--r--drivers/media/video/saa7146.h112
-rw-r--r--drivers/media/video/saa7146reg.h283
5 files changed, 0 insertions, 671 deletions
diff --git a/drivers/media/video/cs8420.h b/drivers/media/video/cs8420.h
deleted file mode 100644
index 621c0c6678ea..000000000000
--- a/drivers/media/video/cs8420.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/* cs8420.h - cs8420 initializations
2 Copyright (C) 1999 Nathan Laredo (laredo@gnu.org)
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 */
19#ifndef __CS8420_H__
20#define __CS8420_H__
21
22/* Initialization Sequence */
23
24static __u8 init8420[] = {
25 1, 0x01, 2, 0x02, 3, 0x00, 4, 0x46,
26 5, 0x24, 6, 0x84, 18, 0x18, 19, 0x13,
27};
28
29#define INIT8420LEN (sizeof(init8420)/2)
30
31static __u8 mode8420pro[] = { /* professional output mode */
32 32, 0xa1, 33, 0x00, 34, 0x00, 35, 0x00,
33 36, 0x00, 37, 0x00, 38, 0x00, 39, 0x00,
34 40, 0x00, 41, 0x00, 42, 0x00, 43, 0x00,
35 44, 0x00, 45, 0x00, 46, 0x00, 47, 0x00,
36 48, 0x00, 49, 0x00, 50, 0x00, 51, 0x00,
37 52, 0x00, 53, 0x00, 54, 0x00, 55, 0x00,
38};
39#define MODE8420LEN (sizeof(mode8420pro)/2)
40
41static __u8 mode8420con[] = { /* consumer output mode */
42 32, 0x20, 33, 0x00, 34, 0x00, 35, 0x48,
43 36, 0x00, 37, 0x00, 38, 0x00, 39, 0x00,
44 40, 0x00, 41, 0x00, 42, 0x00, 43, 0x00,
45 44, 0x00, 45, 0x00, 46, 0x00, 47, 0x00,
46 48, 0x00, 49, 0x00, 50, 0x00, 51, 0x00,
47 52, 0x00, 53, 0x00, 54, 0x00, 55, 0x00,
48};
49
50#endif
diff --git a/drivers/media/video/ibmmpeg2.h b/drivers/media/video/ibmmpeg2.h
deleted file mode 100644
index 68e10387c498..000000000000
--- a/drivers/media/video/ibmmpeg2.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/* ibmmpeg2.h - IBM MPEGCD21 definitions */
2
3#ifndef __IBM_MPEG2__
4#define __IBM_MPEG2__
5
6/* Define all MPEG Decoder registers */
7/* Chip Control and Status */
8#define IBM_MP2_CHIP_CONTROL 0x200*2
9#define IBM_MP2_CHIP_MODE 0x201*2
10/* Timer Control and Status */
11#define IBM_MP2_SYNC_STC2 0x202*2
12#define IBM_MP2_SYNC_STC1 0x203*2
13#define IBM_MP2_SYNC_STC0 0x204*2
14#define IBM_MP2_SYNC_PTS2 0x205*2
15#define IBM_MP2_SYNC_PTS1 0x206*2
16#define IBM_MP2_SYNC_PTS0 0x207*2
17/* Video FIFO Control */
18#define IBM_MP2_FIFO 0x208*2
19#define IBM_MP2_FIFOW 0x100*2
20#define IBM_MP2_FIFO_STAT 0x209*2
21#define IBM_MP2_RB_THRESHOLD 0x22b*2
22/* Command buffer */
23#define IBM_MP2_COMMAND 0x20a*2
24#define IBM_MP2_CMD_DATA 0x20b*2
25#define IBM_MP2_CMD_STAT 0x20c*2
26#define IBM_MP2_CMD_ADDR 0x20d*2
27/* Internal Processor Control and Status */
28#define IBM_MP2_PROC_IADDR 0x20e*2
29#define IBM_MP2_PROC_IDATA 0x20f*2
30#define IBM_MP2_WR_PROT 0x235*2
31/* DRAM Access */
32#define IBM_MP2_DRAM_ADDR 0x210*2
33#define IBM_MP2_DRAM_DATA 0x212*2
34#define IBM_MP2_DRAM_CMD_STAT 0x213*2
35#define IBM_MP2_BLOCK_SIZE 0x23b*2
36#define IBM_MP2_SRC_ADDR 0x23c*2
37/* Onscreen Display */
38#define IBM_MP2_OSD_ADDR 0x214*2
39#define IBM_MP2_OSD_DATA 0x215*2
40#define IBM_MP2_OSD_MODE 0x217*2
41#define IBM_MP2_OSD_LINK_ADDR 0x229*2
42#define IBM_MP2_OSD_SIZE 0x22a*2
43/* Interrupt Control */
44#define IBM_MP2_HOST_INT 0x218*2
45#define IBM_MP2_MASK0 0x219*2
46#define IBM_MP2_HOST_INT1 0x23e*2
47#define IBM_MP2_MASK1 0x23f*2
48/* Audio Control */
49#define IBM_MP2_AUD_IADDR 0x21a*2
50#define IBM_MP2_AUD_IDATA 0x21b*2
51#define IBM_MP2_AUD_FIFO 0x21c*2
52#define IBM_MP2_AUD_FIFOW 0x101*2
53#define IBM_MP2_AUD_CTL 0x21d*2
54#define IBM_MP2_BEEP_CTL 0x21e*2
55#define IBM_MP2_FRNT_ATTEN 0x22d*2
56/* Display Control */
57#define IBM_MP2_DISP_MODE 0x220*2
58#define IBM_MP2_DISP_DLY 0x221*2
59#define IBM_MP2_VBI_CTL 0x222*2
60#define IBM_MP2_DISP_LBOR 0x223*2
61#define IBM_MP2_DISP_TBOR 0x224*2
62/* Polarity Control */
63#define IBM_MP2_INFC_CTL 0x22c*2
64
65/* control commands */
66#define IBM_MP2_PLAY 0
67#define IBM_MP2_PAUSE 1
68#define IBM_MP2_SINGLE_FRAME 2
69#define IBM_MP2_FAST_FORWARD 3
70#define IBM_MP2_SLOW_MOTION 4
71#define IBM_MP2_IMED_NORM_PLAY 5
72#define IBM_MP2_RESET_WINDOW 6
73#define IBM_MP2_FREEZE_FRAME 7
74#define IBM_MP2_RESET_VID_RATE 8
75#define IBM_MP2_CONFIG_DECODER 9
76#define IBM_MP2_CHANNEL_SWITCH 10
77#define IBM_MP2_RESET_AUD_RATE 11
78#define IBM_MP2_PRE_OP_CHN_SW 12
79#define IBM_MP2_SET_STILL_MODE 14
80
81/* Define Xilinx FPGA Internal Registers */
82
83/* general control register 0 */
84#define XILINX_CTL0 0x600
85/* genlock delay resister 1 */
86#define XILINX_GLDELAY 0x602
87/* send 16 bits to CS3310 port */
88#define XILINX_CS3310 0x604
89/* send 16 bits to CS3310 and complete */
90#define XILINX_CS3310_CMPLT 0x60c
91/* pulse width modulator control */
92#define XILINX_PWM 0x606
93
94#endif
diff --git a/drivers/media/video/saa7121.h b/drivers/media/video/saa7121.h
deleted file mode 100644
index 66967ae37494..000000000000
--- a/drivers/media/video/saa7121.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/* saa7121.h - saa7121 initializations
2 Copyright (C) 1999 Nathan Laredo (laredo@gnu.org)
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17
18 */
19#ifndef __SAA7121_H__
20#define __SAA7121_H__
21
22#define NTSC_BURST_START 0x19 /* 28 */
23#define NTSC_BURST_END 0x1d /* 29 */
24#define NTSC_CHROMA_PHASE 0x67 /* 5a */
25#define NTSC_GAINU 0x76 /* 5b */
26#define NTSC_GAINV 0xa5 /* 5c */
27#define NTSC_BLACK_LEVEL 0x2a /* 5d */
28#define NTSC_BLANKING_LEVEL 0x2e /* 5e */
29#define NTSC_VBI_BLANKING 0x2e /* 5f */
30#define NTSC_DAC_CONTROL 0x11 /* 61 */
31#define NTSC_BURST_AMP 0x3f /* 62 */
32#define NTSC_SUBC3 0x1f /* 63 */
33#define NTSC_SUBC2 0x7c /* 64 */
34#define NTSC_SUBC1 0xf0 /* 65 */
35#define NTSC_SUBC0 0x21 /* 66 */
36#define NTSC_HTRIG 0x72 /* 6c */
37#define NTSC_VTRIG 0x00 /* 6c */
38#define NTSC_MULTI 0x30 /* 6e */
39#define NTSC_CCTTX 0x11 /* 6f */
40#define NTSC_FIRST_ACTIVE 0x12 /* 7a */
41#define NTSC_LAST_ACTIVE 0x02 /* 7b */
42#define NTSC_MSB_VERTICAL 0x40 /* 7c */
43
44#define PAL_BURST_START 0x21 /* 28 */
45#define PAL_BURST_END 0x1d /* 29 */
46#define PAL_CHROMA_PHASE 0x3f /* 5a */
47#define PAL_GAINU 0x7d /* 5b */
48#define PAL_GAINV 0xaf /* 5c */
49#define PAL_BLACK_LEVEL 0x23 /* 5d */
50#define PAL_BLANKING_LEVEL 0x35 /* 5e */
51#define PAL_VBI_BLANKING 0x35 /* 5f */
52#define PAL_DAC_CONTROL 0x02 /* 61 */
53#define PAL_BURST_AMP 0x2f /* 62 */
54#define PAL_SUBC3 0xcb /* 63 */
55#define PAL_SUBC2 0x8a /* 64 */
56#define PAL_SUBC1 0x09 /* 65 */
57#define PAL_SUBC0 0x2a /* 66 */
58#define PAL_HTRIG 0x86 /* 6c */
59#define PAL_VTRIG 0x04 /* 6d */
60#define PAL_MULTI 0x20 /* 6e */
61#define PAL_CCTTX 0x15 /* 6f */
62#define PAL_FIRST_ACTIVE 0x16 /* 7a */
63#define PAL_LAST_ACTIVE 0x36 /* 7b */
64#define PAL_MSB_VERTICAL 0x40 /* 7c */
65
66/* Initialization Sequence */
67
68static __u8 init7121ntsc[] = {
69 0x26, 0x0, 0x27, 0x0,
70 0x28, NTSC_BURST_START, 0x29, NTSC_BURST_END,
71 0x2a, 0x0, 0x2b, 0x0, 0x2c, 0x0, 0x2d, 0x0,
72 0x2e, 0x0, 0x2f, 0x0, 0x30, 0x0, 0x31, 0x0,
73 0x32, 0x0, 0x33, 0x0, 0x34, 0x0, 0x35, 0x0,
74 0x36, 0x0, 0x37, 0x0, 0x38, 0x0, 0x39, 0x0,
75 0x3a, 0x03, 0x3b, 0x0, 0x3c, 0x0, 0x3d, 0x0,
76 0x3e, 0x0, 0x3f, 0x0, 0x40, 0x0, 0x41, 0x0,
77 0x42, 0x0, 0x43, 0x0, 0x44, 0x0, 0x45, 0x0,
78 0x46, 0x0, 0x47, 0x0, 0x48, 0x0, 0x49, 0x0,
79 0x4a, 0x0, 0x4b, 0x0, 0x4c, 0x0, 0x4d, 0x0,
80 0x4e, 0x0, 0x4f, 0x0, 0x50, 0x0, 0x51, 0x0,
81 0x52, 0x0, 0x53, 0x0, 0x54, 0x0, 0x55, 0x0,
82 0x56, 0x0, 0x57, 0x0, 0x58, 0x0, 0x59, 0x0,
83 0x5a, NTSC_CHROMA_PHASE, 0x5b, NTSC_GAINU,
84 0x5c, NTSC_GAINV, 0x5d, NTSC_BLACK_LEVEL,
85 0x5e, NTSC_BLANKING_LEVEL, 0x5f, NTSC_VBI_BLANKING,
86 0x60, 0x0, 0x61, NTSC_DAC_CONTROL,
87 0x62, NTSC_BURST_AMP, 0x63, NTSC_SUBC3,
88 0x64, NTSC_SUBC2, 0x65, NTSC_SUBC1,
89 0x66, NTSC_SUBC0, 0x67, 0x80, 0x68, 0x80,
90 0x69, 0x80, 0x6a, 0x80, 0x6b, 0x29,
91 0x6c, NTSC_HTRIG, 0x6d, NTSC_VTRIG,
92 0x6e, NTSC_MULTI, 0x6f, NTSC_CCTTX,
93 0x70, 0xc9, 0x71, 0x68, 0x72, 0x60, 0x73, 0x0,
94 0x74, 0x0, 0x75, 0x0, 0x76, 0x0, 0x77, 0x0,
95 0x78, 0x0, 0x79, 0x0, 0x7a, NTSC_FIRST_ACTIVE,
96 0x7b, NTSC_LAST_ACTIVE, 0x7c, NTSC_MSB_VERTICAL,
97 0x7d, 0x0, 0x7e, 0x0, 0x7f, 0x0
98};
99#define INIT7121LEN (sizeof(init7121ntsc)/2)
100
101static __u8 init7121pal[] = {
102 0x26, 0x0, 0x27, 0x0,
103 0x28, PAL_BURST_START, 0x29, PAL_BURST_END,
104 0x2a, 0x0, 0x2b, 0x0, 0x2c, 0x0, 0x2d, 0x0,
105 0x2e, 0x0, 0x2f, 0x0, 0x30, 0x0, 0x31, 0x0,
106 0x32, 0x0, 0x33, 0x0, 0x34, 0x0, 0x35, 0x0,
107 0x36, 0x0, 0x37, 0x0, 0x38, 0x0, 0x39, 0x0,
108 0x3a, 0x03, 0x3b, 0x0, 0x3c, 0x0, 0x3d, 0x0,
109 0x3e, 0x0, 0x3f, 0x0, 0x40, 0x0, 0x41, 0x0,
110 0x42, 0x0, 0x43, 0x0, 0x44, 0x0, 0x45, 0x0,
111 0x46, 0x0, 0x47, 0x0, 0x48, 0x0, 0x49, 0x0,
112 0x4a, 0x0, 0x4b, 0x0, 0x4c, 0x0, 0x4d, 0x0,
113 0x4e, 0x0, 0x4f, 0x0, 0x50, 0x0, 0x51, 0x0,
114 0x52, 0x0, 0x53, 0x0, 0x54, 0x0, 0x55, 0x0,
115 0x56, 0x0, 0x57, 0x0, 0x58, 0x0, 0x59, 0x0,
116 0x5a, PAL_CHROMA_PHASE, 0x5b, PAL_GAINU,
117 0x5c, PAL_GAINV, 0x5d, PAL_BLACK_LEVEL,
118 0x5e, PAL_BLANKING_LEVEL, 0x5f, PAL_VBI_BLANKING,
119 0x60, 0x0, 0x61, PAL_DAC_CONTROL,
120 0x62, PAL_BURST_AMP, 0x63, PAL_SUBC3,
121 0x64, PAL_SUBC2, 0x65, PAL_SUBC1,
122 0x66, PAL_SUBC0, 0x67, 0x80, 0x68, 0x80,
123 0x69, 0x80, 0x6a, 0x80, 0x6b, 0x29,
124 0x6c, PAL_HTRIG, 0x6d, PAL_VTRIG,
125 0x6e, PAL_MULTI, 0x6f, PAL_CCTTX,
126 0x70, 0xc9, 0x71, 0x68, 0x72, 0x60, 0x73, 0x0,
127 0x74, 0x0, 0x75, 0x0, 0x76, 0x0, 0x77, 0x0,
128 0x78, 0x0, 0x79, 0x0, 0x7a, PAL_FIRST_ACTIVE,
129 0x7b, PAL_LAST_ACTIVE, 0x7c, PAL_MSB_VERTICAL,
130 0x7d, 0x0, 0x7e, 0x0, 0x7f, 0x0
131};
132#endif
diff --git a/drivers/media/video/saa7146.h b/drivers/media/video/saa7146.h
deleted file mode 100644
index 9fadb331a40b..000000000000
--- a/drivers/media/video/saa7146.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 saa7146.h - definitions philips saa7146 based cards
3 Copyright (C) 1999 Nathan Laredo (laredo@gnu.org)
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20#ifndef __SAA7146__
21#define __SAA7146__
22
23#define SAA7146_VERSION_CODE 0x000101
24
25#include <linux/types.h>
26#include <linux/wait.h>
27
28#ifndef O_NONCAP
29#define O_NONCAP O_TRUNC
30#endif
31
32#define MAX_GBUFFERS 2
33#define FBUF_SIZE 0x190000
34
35#ifdef __KERNEL__
36
37struct saa7146_window
38{
39 int x, y;
40 ushort width, height;
41 ushort bpp, bpl;
42 ushort swidth, sheight;
43 short cropx, cropy;
44 ushort cropwidth, cropheight;
45 unsigned long vidadr;
46 int color_fmt;
47 ushort depth;
48};
49
50/* Per-open data for handling multiple opens on one device */
51struct device_open
52{
53 int isopen;
54 int noncapturing;
55 struct saa7146 *dev;
56};
57#define MAX_OPENS 3
58
59struct saa7146
60{
61 struct video_device video_dev;
62 struct video_picture picture;
63 struct video_audio audio_dev;
64 struct video_info vidinfo;
65 int user;
66 int cap;
67 int capuser;
68 int irqstate; /* irq routine is state driven */
69 int writemode;
70 int playmode;
71 unsigned int nr;
72 unsigned long irq; /* IRQ used by SAA7146 card */
73 unsigned short id;
74 unsigned char revision;
75 unsigned char boardcfg[64]; /* 64 bytes of config from eeprom */
76 unsigned long saa7146_adr; /* bus address of IO mem from PCI BIOS */
77 struct saa7146_window win;
78 unsigned char __iomem *saa7146_mem; /* pointer to mapped IO memory */
79 struct device_open open_data[MAX_OPENS];
80#define MAX_MARKS 16
81 /* for a/v sync */
82 int endmark[MAX_MARKS], endmarkhead, endmarktail;
83 u32 *dmaRPS1, *pageRPS1, *dmaRPS2, *pageRPS2, *dmavid1, *dmavid2,
84 *dmavid3, *dmaa1in, *dmaa1out, *dmaa2in, *dmaa2out,
85 *pagedebi, *pagevid1, *pagevid2, *pagevid3, *pagea1in,
86 *pagea1out, *pagea2in, *pagea2out;
87 wait_queue_head_t i2cq, debiq, audq, vidq;
88 u8 *vidbuf, *audbuf, *osdbuf, *dmadebi;
89 int audhead, vidhead, osdhead, audtail, vidtail, osdtail;
90 spinlock_t lock; /* the device lock */
91};
92#endif
93
94#ifdef _ALPHA_SAA7146
95#define saawrite(dat,adr) writel((dat), saa->saa7146_adr+(adr))
96#define saaread(adr) readl(saa->saa7146_adr+(adr))
97#else
98#define saawrite(dat,adr) writel((dat), saa->saa7146_mem+(adr))
99#define saaread(adr) readl(saa->saa7146_mem+(adr))
100#endif
101
102#define saaand(dat,adr) saawrite((dat) & saaread(adr), adr)
103#define saaor(dat,adr) saawrite((dat) | saaread(adr), adr)
104#define saaaor(dat,mask,adr) saawrite((dat) | ((mask) & saaread(adr)), adr)
105
106/* bitmask of attached hardware found */
107#define SAA7146_UNKNOWN 0x00000000
108#define SAA7146_SAA7111 0x00000001
109#define SAA7146_SAA7121 0x00000002
110#define SAA7146_IBMMPEG 0x00000004
111
112#endif
diff --git a/drivers/media/video/saa7146reg.h b/drivers/media/video/saa7146reg.h
deleted file mode 100644
index 80ec2c146b4c..000000000000
--- a/drivers/media/video/saa7146reg.h
+++ /dev/null
@@ -1,283 +0,0 @@
1/*
2 saa7146.h - definitions philips saa7146 based cards
3 Copyright (C) 1999 Nathan Laredo (laredo@gnu.org)
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18*/
19
20#ifndef __SAA7146_REG__
21#define __SAA7146_REG__
22#define SAA7146_BASE_ODD1 0x00
23#define SAA7146_BASE_EVEN1 0x04
24#define SAA7146_PROT_ADDR1 0x08
25#define SAA7146_PITCH1 0x0c
26#define SAA7146_PAGE1 0x10
27#define SAA7146_NUM_LINE_BYTE1 0x14
28#define SAA7146_BASE_ODD2 0x18
29#define SAA7146_BASE_EVEN2 0x1c
30#define SAA7146_PROT_ADDR2 0x20
31#define SAA7146_PITCH2 0x24
32#define SAA7146_PAGE2 0x28
33#define SAA7146_NUM_LINE_BYTE2 0x2c
34#define SAA7146_BASE_ODD3 0x30
35#define SAA7146_BASE_EVEN3 0x34
36#define SAA7146_PROT_ADDR3 0x38
37#define SAA7146_PITCH3 0x3c
38#define SAA7146_PAGE3 0x40
39#define SAA7146_NUM_LINE_BYTE3 0x44
40#define SAA7146_PCI_BT_V1 0x48
41#define SAA7146_PCI_BT_V2 0x49
42#define SAA7146_PCI_BT_V3 0x4a
43#define SAA7146_PCI_BT_DEBI 0x4b
44#define SAA7146_PCI_BT_A 0x4c
45#define SAA7146_DD1_INIT 0x50
46#define SAA7146_DD1_STREAM_B 0x54
47#define SAA7146_DD1_STREAM_A 0x56
48#define SAA7146_BRS_CTRL 0x58
49#define SAA7146_HPS_CTRL 0x5c
50#define SAA7146_HPS_V_SCALE 0x60
51#define SAA7146_HPS_V_GAIN 0x64
52#define SAA7146_HPS_H_PRESCALE 0x68
53#define SAA7146_HPS_H_SCALE 0x6c
54#define SAA7146_BCS_CTRL 0x70
55#define SAA7146_CHROMA_KEY_RANGE 0x74
56#define SAA7146_CLIP_FORMAT_CTRL 0x78
57#define SAA7146_DEBI_CONFIG 0x7c
58#define SAA7146_DEBI_COMMAND 0x80
59#define SAA7146_DEBI_PAGE 0x84
60#define SAA7146_DEBI_AD 0x88
61#define SAA7146_I2C_TRANSFER 0x8c
62#define SAA7146_I2C_STATUS 0x90
63#define SAA7146_BASE_A1_IN 0x94
64#define SAA7146_PROT_A1_IN 0x98
65#define SAA7146_PAGE_A1_IN 0x9C
66#define SAA7146_BASE_A1_OUT 0xa0
67#define SAA7146_PROT_A1_OUT 0xa4
68#define SAA7146_PAGE_A1_OUT 0xa8
69#define SAA7146_BASE_A2_IN 0xac
70#define SAA7146_PROT_A2_IN 0xb0
71#define SAA7146_PAGE_A2_IN 0xb4
72#define SAA7146_BASE_A2_OUT 0xb8
73#define SAA7146_PROT_A2_OUT 0xbc
74#define SAA7146_PAGE_A2_OUT 0xc0
75#define SAA7146_RPS_PAGE0 0xc4
76#define SAA7146_RPS_PAGE1 0xc8
77#define SAA7146_RPS_THRESH0 0xcc
78#define SAA7146_RPS_THRESH1 0xd0
79#define SAA7146_RPS_TOV0 0xd4
80#define SAA7146_RPS_TOV1 0xd8
81#define SAA7146_IER 0xdc
82#define SAA7146_GPIO_CTRL 0xe0
83#define SAA7146_EC1SSR 0xe4
84#define SAA7146_EC2SSR 0xe8
85#define SAA7146_ECT1R 0xec
86#define SAA7146_ECT2R 0xf0
87#define SAA7146_ACON1 0xf4
88#define SAA7146_ACON2 0xf8
89#define SAA7146_MC1 0xfc
90#define SAA7146_MC2 0x100
91#define SAA7146_RPS_ADDR0 0x104
92#define SAA7146_RPS_ADDR1 0x108
93#define SAA7146_ISR 0x10c
94#define SAA7146_PSR 0x110
95#define SAA7146_SSR 0x114
96#define SAA7146_EC1R 0x118
97#define SAA7146_EC2R 0x11c
98#define SAA7146_VDP1 0x120
99#define SAA7146_VDP2 0x124
100#define SAA7146_VDP3 0x128
101#define SAA7146_ADP1 0x12c
102#define SAA7146_ADP2 0x130
103#define SAA7146_ADP3 0x134
104#define SAA7146_ADP4 0x138
105#define SAA7146_DDP 0x13c
106#define SAA7146_LEVEL_REP 0x140
107#define SAA7146_FB_BUFFER1 0x144
108#define SAA7146_FB_BUFFER2 0x148
109#define SAA7146_A_TIME_SLOT1 0x180
110#define SAA7146_A_TIME_SLOT2 0x1C0
111
112/* bitfield defines */
113#define MASK_31 0x80000000
114#define MASK_30 0x40000000
115#define MASK_29 0x20000000
116#define MASK_28 0x10000000
117#define MASK_27 0x08000000
118#define MASK_26 0x04000000
119#define MASK_25 0x02000000
120#define MASK_24 0x01000000
121#define MASK_23 0x00800000
122#define MASK_22 0x00400000
123#define MASK_21 0x00200000
124#define MASK_20 0x00100000
125#define MASK_19 0x00080000
126#define MASK_18 0x00040000
127#define MASK_17 0x00020000
128#define MASK_16 0x00010000
129#define MASK_15 0x00008000
130#define MASK_14 0x00004000
131#define MASK_13 0x00002000
132#define MASK_12 0x00001000
133#define MASK_11 0x00000800
134#define MASK_10 0x00000400
135#define MASK_09 0x00000200
136#define MASK_08 0x00000100
137#define MASK_07 0x00000080
138#define MASK_06 0x00000040
139#define MASK_05 0x00000020
140#define MASK_04 0x00000010
141#define MASK_03 0x00000008
142#define MASK_02 0x00000004
143#define MASK_01 0x00000002
144#define MASK_00 0x00000001
145#define MASK_B0 0x000000ff
146#define MASK_B1 0x0000ff00
147#define MASK_B2 0x00ff0000
148#define MASK_B3 0xff000000
149#define MASK_W0 0x0000ffff
150#define MASK_W1 0xffff0000
151#define MASK_PA 0xfffffffc
152#define MASK_PR 0xfffffffe
153#define MASK_ER 0xffffffff
154#define MASK_NONE 0x00000000
155
156#define SAA7146_PAGE_MAP_EN MASK_11
157/* main control register 1 */
158#define SAA7146_MC1_MRST_N MASK_15
159#define SAA7146_MC1_ERPS1 MASK_13
160#define SAA7146_MC1_ERPS0 MASK_12
161#define SAA7146_MC1_EDP MASK_11
162#define SAA7146_MC1_EVP MASK_10
163#define SAA7146_MC1_EAP MASK_09
164#define SAA7146_MC1_EI2C MASK_08
165#define SAA7146_MC1_TR_E_DEBI MASK_07
166#define SAA7146_MC1_TR_E_1 MASK_06
167#define SAA7146_MC1_TR_E_2 MASK_05
168#define SAA7146_MC1_TR_E_3 MASK_04
169#define SAA7146_MC1_TR_E_A2_OUT MASK_03
170#define SAA7146_MC1_TR_E_A2_IN MASK_02
171#define SAA7146_MC1_TR_E_A1_OUT MASK_01
172#define SAA7146_MC1_TR_E_A1_IN MASK_00
173/* main control register 2 */
174#define SAA7146_MC2_RPS_SIG4 MASK_15
175#define SAA7146_MC2_RPS_SIG3 MASK_14
176#define SAA7146_MC2_RPS_SIG2 MASK_13
177#define SAA7146_MC2_RPS_SIG1 MASK_12
178#define SAA7146_MC2_RPS_SIG0 MASK_11
179#define SAA7146_MC2_UPLD_D1_B MASK_10
180#define SAA7146_MC2_UPLD_D1_A MASK_09
181#define SAA7146_MC2_UPLD_BRS MASK_08
182#define SAA7146_MC2_UPLD_HPS_H MASK_06
183#define SAA7146_MC2_UPLD_HPS_V MASK_05
184#define SAA7146_MC2_UPLD_DMA3 MASK_04
185#define SAA7146_MC2_UPLD_DMA2 MASK_03
186#define SAA7146_MC2_UPLD_DMA1 MASK_02
187#define SAA7146_MC2_UPLD_DEBI MASK_01
188#define SAA7146_MC2_UPLD_I2C MASK_00
189/* Primary Status Register and Interrupt Enable/Status Registers */
190#define SAA7146_PSR_PPEF MASK_31
191#define SAA7146_PSR_PABO MASK_30
192#define SAA7146_PSR_PPED MASK_29
193#define SAA7146_PSR_RPS_I1 MASK_28
194#define SAA7146_PSR_RPS_I0 MASK_27
195#define SAA7146_PSR_RPS_LATE1 MASK_26
196#define SAA7146_PSR_RPS_LATE0 MASK_25
197#define SAA7146_PSR_RPS_E1 MASK_24
198#define SAA7146_PSR_RPS_E0 MASK_23
199#define SAA7146_PSR_RPS_TO1 MASK_22
200#define SAA7146_PSR_RPS_TO0 MASK_21
201#define SAA7146_PSR_UPLD MASK_20
202#define SAA7146_PSR_DEBI_S MASK_19
203#define SAA7146_PSR_DEBI_E MASK_18
204#define SAA7146_PSR_I2C_S MASK_17
205#define SAA7146_PSR_I2C_E MASK_16
206#define SAA7146_PSR_A2_IN MASK_15
207#define SAA7146_PSR_A2_OUT MASK_14
208#define SAA7146_PSR_A1_IN MASK_13
209#define SAA7146_PSR_A1_OUT MASK_12
210#define SAA7146_PSR_AFOU MASK_11
211#define SAA7146_PSR_V_PE MASK_10
212#define SAA7146_PSR_VFOU MASK_09
213#define SAA7146_PSR_FIDA MASK_08
214#define SAA7146_PSR_FIDB MASK_07
215#define SAA7146_PSR_PIN3 MASK_06
216#define SAA7146_PSR_PIN2 MASK_05
217#define SAA7146_PSR_PIN1 MASK_04
218#define SAA7146_PSR_PIN0 MASK_03
219#define SAA7146_PSR_ECS MASK_02
220#define SAA7146_PSR_EC3S MASK_01
221#define SAA7146_PSR_EC0S MASK_00
222/* Secondary Status Register */
223#define SAA7146_SSR_PRQ MASK_31
224#define SAA7146_SSR_PMA MASK_30
225#define SAA7146_SSR_RPS_RE1 MASK_29
226#define SAA7146_SSR_RPS_PE1 MASK_28
227#define SAA7146_SSR_RPS_A1 MASK_27
228#define SAA7146_SSR_RPS_RE0 MASK_26
229#define SAA7146_SSR_RPS_PE0 MASK_25
230#define SAA7146_SSR_RPS_A0 MASK_24
231#define SAA7146_SSR_DEBI_TO MASK_23
232#define SAA7146_SSR_DEBI_EF MASK_22
233#define SAA7146_SSR_I2C_EA MASK_21
234#define SAA7146_SSR_I2C_EW MASK_20
235#define SAA7146_SSR_I2C_ER MASK_19
236#define SAA7146_SSR_I2C_EL MASK_18
237#define SAA7146_SSR_I2C_EF MASK_17
238#define SAA7146_SSR_V3P MASK_16
239#define SAA7146_SSR_V2P MASK_15
240#define SAA7146_SSR_V1P MASK_14
241#define SAA7146_SSR_VF3 MASK_13
242#define SAA7146_SSR_VF2 MASK_12
243#define SAA7146_SSR_VF1 MASK_11
244#define SAA7146_SSR_AF2_IN MASK_10
245#define SAA7146_SSR_AF2_OUT MASK_09
246#define SAA7146_SSR_AF1_IN MASK_08
247#define SAA7146_SSR_AF1_OUT MASK_07
248#define SAA7146_SSR_VGT MASK_05
249#define SAA7146_SSR_LNQG MASK_04
250#define SAA7146_SSR_EC5S MASK_03
251#define SAA7146_SSR_EC4S MASK_02
252#define SAA7146_SSR_EC2S MASK_01
253#define SAA7146_SSR_EC1S MASK_00
254/* I2C status register */
255#define SAA7146_I2C_ABORT MASK_07
256#define SAA7146_I2C_SPERR MASK_06
257#define SAA7146_I2C_APERR MASK_05
258#define SAA7146_I2C_DTERR MASK_04
259#define SAA7146_I2C_DRERR MASK_03
260#define SAA7146_I2C_AL MASK_02
261#define SAA7146_I2C_ERR MASK_01
262#define SAA7146_I2C_BUSY MASK_00
263/* output formats */
264#define SAA7146_YUV422 0
265#define SAA7146_RGB16 0
266#define SAA7146_YUV444 1
267#define SAA7146_RGB24 1
268#define SAA7146_ARGB32 2
269#define SAA7146_YUV411 3
270#define SAA7146_ARGB15 3
271#define SAA7146_YUV2 4
272#define SAA7146_RGAB15 4
273#define SAA7146_Y8 6
274#define SAA7146_YUV8 7
275#define SAA7146_RGB8 7
276#define SAA7146_YUV444p 8
277#define SAA7146_YUV422p 9
278#define SAA7146_YUV420p 10
279#define SAA7146_YUV1620 11
280#define SAA7146_Y1 13
281#define SAA7146_Y2 14
282#define SAA7146_YUV1 15
283#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-08 08:39:45 -0500