diff options
author | Imre Deak <imre.deak@intel.com> | 2014-02-11 14:39:06 -0500 |
---|---|---|
committer | Jani Nikula <jani.nikula@intel.com> | 2014-03-03 12:06:40 -0500 |
commit | 17b0c1f7865d8bf4f5e5aa94e2aeafb35d23e4e9 (patch) | |
tree | afbcfbc38f5b062a19826530d2984760e0355dc6 | |
parent | bcdb72ac7c00d2b56359fc82bcc8fe50454717d5 (diff) |
drm/i915: vlv: reserve GT power context early
We reserve the space for the power context in stolen memory at a fixed
address from a delayed work. This races with the subsequent driver
init/resume code which could allocate something at that address, so the
reservation for the power context fails. Reserve the space up-front, so
this can't happen. This also adds a missing struct_mutex lock around the
stolen allocation, which wasn't taken in the delayed work path.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d77cc81900f9..e1fc35a72656 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -3493,6 +3493,8 @@ static void valleyview_setup_pctx(struct drm_device *dev) | |||
3493 | u32 pcbr; | 3493 | u32 pcbr; |
3494 | int pctx_size = 24*1024; | 3494 | int pctx_size = 24*1024; |
3495 | 3495 | ||
3496 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | ||
3497 | |||
3496 | pcbr = I915_READ(VLV_PCBR); | 3498 | pcbr = I915_READ(VLV_PCBR); |
3497 | if (pcbr) { | 3499 | if (pcbr) { |
3498 | /* BIOS set it up already, grab the pre-alloc'd space */ | 3500 | /* BIOS set it up already, grab the pre-alloc'd space */ |
@@ -3542,8 +3544,6 @@ static void valleyview_enable_rps(struct drm_device *dev) | |||
3542 | I915_WRITE(GTFIFODBG, gtfifodbg); | 3544 | I915_WRITE(GTFIFODBG, gtfifodbg); |
3543 | } | 3545 | } |
3544 | 3546 | ||
3545 | valleyview_setup_pctx(dev); | ||
3546 | |||
3547 | /* If VLV, Forcewake all wells, else re-direct to regular path */ | 3547 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
3548 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | 3548 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3549 | 3549 | ||
@@ -4395,6 +4395,8 @@ void intel_enable_gt_powersave(struct drm_device *dev) | |||
4395 | ironlake_enable_rc6(dev); | 4395 | ironlake_enable_rc6(dev); |
4396 | intel_init_emon(dev); | 4396 | intel_init_emon(dev); |
4397 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { | 4397 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
4398 | if (IS_VALLEYVIEW(dev)) | ||
4399 | valleyview_setup_pctx(dev); | ||
4398 | /* | 4400 | /* |
4399 | * PCU communication is slow and this doesn't need to be | 4401 | * PCU communication is slow and this doesn't need to be |
4400 | * done at any specific time, so do this out of our fast path | 4402 | * done at any specific time, so do this out of our fast path |