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authorMagnus Damm <damm@opensource.se>2013-03-26 09:50:36 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-04-02 21:30:40 -0400
commit172fd616dd46a181be5c9c17bd0a84dd8ae0ce94 (patch)
tree078c9394671598deec1bf20fca2f71a2fba31e38
parent57ef73b469e7e6f7d15e5467649c787bc7070819 (diff)
sh-pfc: r8a73a4: Add SCIF pin groups and functions
Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and SCIFB0->SCIFB3. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c287
1 files changed, 287 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 86a5fd33a479..cd5c5fd74ba4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1576,6 +1576,286 @@ static const struct pinmux_range pinmux_ranges[] = {
1576 {.begin = 320, .end = 329,}, 1576 {.begin = 320, .end = 329,},
1577}; 1577};
1578 1578
1579/* - SCIFA0 ----------------------------------------------------------------- */
1580static const unsigned int scifa0_data_pins[] = {
1581 /* SCIFA0_RXD, SCIFA0_TXD */
1582 117, 116,
1583};
1584static const unsigned int scifa0_data_mux[] = {
1585 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1586};
1587static const unsigned int scifa0_clk_pins[] = {
1588 /* SCIFA0_SCK */
1589 34,
1590};
1591static const unsigned int scifa0_clk_mux[] = {
1592 SCIFA0_SCK_MARK,
1593};
1594static const unsigned int scifa0_ctrl_pins[] = {
1595 /* SCIFA0_RTS, SCIFA0_CTS */
1596 32, 33,
1597};
1598static const unsigned int scifa0_ctrl_mux[] = {
1599 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1600};
1601/* - SCIFA1 ----------------------------------------------------------------- */
1602static const unsigned int scifa1_data_pins[] = {
1603 /* SCIFA1_RXD, SCIFA1_TXD */
1604 119, 118,
1605};
1606static const unsigned int scifa1_data_mux[] = {
1607 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1608};
1609static const unsigned int scifa1_clk_pins[] = {
1610 /* SCIFA1_SCK */
1611 37,
1612};
1613static const unsigned int scifa1_clk_mux[] = {
1614 SCIFA1_SCK_MARK,
1615};
1616static const unsigned int scifa1_ctrl_pins[] = {
1617 /* SCIFA1_RTS, SCIFA1_CTS */
1618 35, 36,
1619};
1620static const unsigned int scifa1_ctrl_mux[] = {
1621 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1622};
1623/* - SCIFB0 ----------------------------------------------------------------- */
1624static const unsigned int scifb0_data_pins[] = {
1625 /* SCIFB0_RXD, SCIFB0_TXD */
1626 123, 122,
1627};
1628static const unsigned int scifb0_data_mux[] = {
1629 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1630};
1631static const unsigned int scifb0_clk_pins[] = {
1632 /* SCIFB0_SCK */
1633 40,
1634};
1635static const unsigned int scifb0_clk_mux[] = {
1636 SCIFB0_SCK_MARK,
1637};
1638static const unsigned int scifb0_ctrl_pins[] = {
1639 /* SCIFB0_RTS, SCIFB0_CTS */
1640 38, 39,
1641};
1642static const unsigned int scifb0_ctrl_mux[] = {
1643 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1644};
1645/* - SCIFB1 ----------------------------------------------------------------- */
1646static const unsigned int scifb1_data_pins[] = {
1647 /* SCIFB1_RXD, SCIFB1_TXD */
1648 27, 26,
1649};
1650static const unsigned int scifb1_data_mux[] = {
1651 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1652};
1653static const unsigned int scifb1_clk_pins[] = {
1654 /* SCIFB1_SCK */
1655 28,
1656};
1657static const unsigned int scifb1_clk_mux[] = {
1658 SCIFB1_SCK_28_MARK,
1659};
1660static const unsigned int scifb1_ctrl_pins[] = {
1661 /* SCIFB1_RTS, SCIFB1_CTS */
1662 24, 25,
1663};
1664static const unsigned int scifb1_ctrl_mux[] = {
1665 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1666};
1667static const unsigned int scifb1_data_b_pins[] = {
1668 /* SCIFB1_RXD, SCIFB1_TXD */
1669 72, 67,
1670};
1671static const unsigned int scifb1_data_b_mux[] = {
1672 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1673};
1674static const unsigned int scifb1_clk_b_pins[] = {
1675 /* SCIFB1_SCK */
1676 261,
1677};
1678static const unsigned int scifb1_clk_b_mux[] = {
1679 SCIFB1_SCK_261_MARK,
1680};
1681static const unsigned int scifb1_ctrl_b_pins[] = {
1682 /* SCIFB1_RTS, SCIFB1_CTS */
1683 70, 71,
1684};
1685static const unsigned int scifb1_ctrl_b_mux[] = {
1686 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1687};
1688/* - SCIFB2 ----------------------------------------------------------------- */
1689static const unsigned int scifb2_data_pins[] = {
1690 /* SCIFB2_RXD, SCIFB2_TXD */
1691 69, 68,
1692};
1693static const unsigned int scifb2_data_mux[] = {
1694 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1695};
1696static const unsigned int scifb2_clk_pins[] = {
1697 /* SCIFB2_SCK */
1698 262,
1699};
1700static const unsigned int scifb2_clk_mux[] = {
1701 SCIFB2_SCK_262_MARK,
1702};
1703static const unsigned int scifb2_ctrl_pins[] = {
1704 /* SCIFB2_RTS, SCIFB2_CTS */
1705 73, 66,
1706};
1707static const unsigned int scifb2_ctrl_mux[] = {
1708 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1709};
1710static const unsigned int scifb2_data_b_pins[] = {
1711 /* SCIFB2_RXD, SCIFB2_TXD */
1712 297, 295,
1713};
1714static const unsigned int scifb2_data_b_mux[] = {
1715 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1716};
1717static const unsigned int scifb2_clk_b_pins[] = {
1718 /* SCIFB2_SCK */
1719 299,
1720};
1721static const unsigned int scifb2_clk_b_mux[] = {
1722 SCIFB2_SCK_299_MARK,
1723};
1724static const unsigned int scifb2_ctrl_b_pins[] = {
1725 /* SCIFB2_RTS, SCIFB2_CTS */
1726 300, 298,
1727};
1728static const unsigned int scifb2_ctrl_b_mux[] = {
1729 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1730};
1731/* - SCIFB3 ----------------------------------------------------------------- */
1732static const unsigned int scifb3_data_pins[] = {
1733 /* SCIFB3_RXD, SCIFB3_TXD */
1734 22, 21,
1735};
1736static const unsigned int scifb3_data_mux[] = {
1737 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1738};
1739static const unsigned int scifb3_clk_pins[] = {
1740 /* SCIFB3_SCK */
1741 23,
1742};
1743static const unsigned int scifb3_clk_mux[] = {
1744 SCIFB3_SCK_23_MARK,
1745};
1746static const unsigned int scifb3_ctrl_pins[] = {
1747 /* SCIFB3_RTS, SCIFB3_CTS */
1748 19, 20,
1749};
1750static const unsigned int scifb3_ctrl_mux[] = {
1751 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1752};
1753static const unsigned int scifb3_data_b_pins[] = {
1754 /* SCIFB3_RXD, SCIFB3_TXD */
1755 120, 121,
1756};
1757static const unsigned int scifb3_data_b_mux[] = {
1758 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1759};
1760static const unsigned int scifb3_clk_b_pins[] = {
1761 /* SCIFB3_SCK */
1762 40,
1763};
1764static const unsigned int scifb3_clk_b_mux[] = {
1765 SCIFB3_SCK_40_MARK,
1766};
1767static const unsigned int scifb3_ctrl_b_pins[] = {
1768 /* SCIFB3_RTS, SCIFB3_CTS */
1769 38, 39,
1770};
1771static const unsigned int scifb3_ctrl_b_mux[] = {
1772 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1773};
1774
1775static const struct sh_pfc_pin_group pinmux_groups[] = {
1776 SH_PFC_PIN_GROUP(scifa0_data),
1777 SH_PFC_PIN_GROUP(scifa0_clk),
1778 SH_PFC_PIN_GROUP(scifa0_ctrl),
1779 SH_PFC_PIN_GROUP(scifa1_data),
1780 SH_PFC_PIN_GROUP(scifa1_clk),
1781 SH_PFC_PIN_GROUP(scifa1_ctrl),
1782 SH_PFC_PIN_GROUP(scifb0_data),
1783 SH_PFC_PIN_GROUP(scifb0_clk),
1784 SH_PFC_PIN_GROUP(scifb0_ctrl),
1785 SH_PFC_PIN_GROUP(scifb1_data),
1786 SH_PFC_PIN_GROUP(scifb1_clk),
1787 SH_PFC_PIN_GROUP(scifb1_ctrl),
1788 SH_PFC_PIN_GROUP(scifb1_data_b),
1789 SH_PFC_PIN_GROUP(scifb1_clk_b),
1790 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1791 SH_PFC_PIN_GROUP(scifb2_data),
1792 SH_PFC_PIN_GROUP(scifb2_clk),
1793 SH_PFC_PIN_GROUP(scifb2_ctrl),
1794 SH_PFC_PIN_GROUP(scifb2_data_b),
1795 SH_PFC_PIN_GROUP(scifb2_clk_b),
1796 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1797 SH_PFC_PIN_GROUP(scifb3_data),
1798 SH_PFC_PIN_GROUP(scifb3_clk),
1799 SH_PFC_PIN_GROUP(scifb3_ctrl),
1800 SH_PFC_PIN_GROUP(scifb3_data_b),
1801 SH_PFC_PIN_GROUP(scifb3_clk_b),
1802 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1803};
1804
1805static const char * const scifa0_groups[] = {
1806 "scifa0_data",
1807 "scifa0_clk",
1808 "scifa0_ctrl",
1809};
1810
1811static const char * const scifa1_groups[] = {
1812 "scifa1_data",
1813 "scifa1_clk",
1814 "scifa1_ctrl",
1815};
1816
1817static const char * const scifb0_groups[] = {
1818 "scifb0_data",
1819 "scifb0_clk",
1820 "scifb0_ctrl",
1821};
1822
1823static const char * const scifb1_groups[] = {
1824 "scifb1_data",
1825 "scifb1_clk",
1826 "scifb1_ctrl",
1827 "scifb1_data_b",
1828 "scifb1_clk_b",
1829 "scifb1_ctrl_b",
1830};
1831
1832static const char * const scifb2_groups[] = {
1833 "scifb2_data",
1834 "scifb2_clk",
1835 "scifb2_ctrl",
1836 "scifb2_data_b",
1837 "scifb2_clk_b",
1838 "scifb2_ctrl_b",
1839};
1840
1841static const char * const scifb3_groups[] = {
1842 "scifb3_data",
1843 "scifb3_clk",
1844 "scifb3_ctrl",
1845 "scifb3_data_b",
1846 "scifb3_clk_b",
1847 "scifb3_ctrl_b",
1848};
1849
1850static const struct sh_pfc_function pinmux_functions[] = {
1851 SH_PFC_FUNCTION(scifa0),
1852 SH_PFC_FUNCTION(scifa1),
1853 SH_PFC_FUNCTION(scifb0),
1854 SH_PFC_FUNCTION(scifb1),
1855 SH_PFC_FUNCTION(scifb2),
1856 SH_PFC_FUNCTION(scifb3),
1857};
1858
1579#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 1859#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1580 1860
1581static const struct pinmux_func pinmux_func_gpios[] = { 1861static const struct pinmux_func pinmux_func_gpios[] = {
@@ -3084,8 +3364,15 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
3084 3364
3085 .pins = pinmux_pins, 3365 .pins = pinmux_pins,
3086 .nr_pins = ARRAY_SIZE(pinmux_pins), 3366 .nr_pins = ARRAY_SIZE(pinmux_pins),
3367
3087 .ranges = pinmux_ranges, 3368 .ranges = pinmux_ranges,
3088 .nr_ranges = ARRAY_SIZE(pinmux_ranges), 3369 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
3370
3371 .groups = pinmux_groups,
3372 .nr_groups = ARRAY_SIZE(pinmux_groups),
3373 .functions = pinmux_functions,
3374 .nr_functions = ARRAY_SIZE(pinmux_functions),
3375
3089 .func_gpios = pinmux_func_gpios, 3376 .func_gpios = pinmux_func_gpios,
3090 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), 3377 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3091 3378