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authorSujith <Sujith.Manoharan@atheros.com>2010-06-01 05:44:04 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-06-03 14:10:46 -0400
commit16c94ac6cf9727b686e16b8d5dedfd282ab3a9ee (patch)
tree8adaeddf9b2abee13cee82b0e5cc54fa3e634a31
parentad0e2b5a00dbec303e4682b403bb6703d11dcdb2 (diff)
ath9k_hw: Cleanup eeprom_9287.c
* Fix whitespace damage. * Remove unused debug messages. * Introduce a macro NUM_EEP_WORDS. * Convert AR9287 to lowercase in function names. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c273
1 files changed, 136 insertions, 137 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index b471db5fb82d..5010cd13023c 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -17,17 +17,19 @@
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h" 18#include "ar9002_phy.h"
19 19
20static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 20#define NUM_EEP_WORDS (sizeof(struct ar9287_eeprom) / sizeof(u16))
21
22static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
21{ 23{
22 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF; 24 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
23} 25}
24 26
25static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah) 27static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
26{ 28{
27 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF; 29 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
28} 30}
29 31
30static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah) 32static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
31{ 33{
32 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 34 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
33 struct ath_common *common = ath9k_hw_common(ah); 35 struct ath_common *common = ath9k_hw_common(ah);
@@ -40,20 +42,20 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
40 "Reading from EEPROM, not flash\n"); 42 "Reading from EEPROM, not flash\n");
41 } 43 }
42 44
43 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); 45 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
44 addr++) { 46 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
45 if (!ath9k_hw_nvram_read(common, 47 eep_data)) {
46 addr + eep_start_loc, eep_data)) {
47 ath_print(common, ATH_DBG_EEPROM, 48 ath_print(common, ATH_DBG_EEPROM,
48 "Unable to read eeprom region\n"); 49 "Unable to read eeprom region\n");
49 return false; 50 return false;
50 } 51 }
51 eep_data++; 52 eep_data++;
52 } 53 }
54
53 return true; 55 return true;
54} 56}
55 57
56static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) 58static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
57{ 59{
58 u32 sum = 0, el, integer; 60 u32 sum = 0, el, integer;
59 u16 temp, word, magic, magic2, *eepdata; 61 u16 temp, word, magic, magic2, *eepdata;
@@ -63,8 +65,8 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
63 struct ath_common *common = ath9k_hw_common(ah); 65 struct ath_common *common = ath9k_hw_common(ah);
64 66
65 if (!ath9k_hw_use_flash(ah)) { 67 if (!ath9k_hw_use_flash(ah)) {
66 if (!ath9k_hw_nvram_read(common, 68 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
67 AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 69 &magic)) {
68 ath_print(common, ATH_DBG_FATAL, 70 ath_print(common, ATH_DBG_FATAL,
69 "Reading Magic # failed\n"); 71 "Reading Magic # failed\n");
70 return false; 72 return false;
@@ -72,6 +74,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
72 74
73 ath_print(common, ATH_DBG_EEPROM, 75 ath_print(common, ATH_DBG_EEPROM,
74 "Read Magic = 0x%04X\n", magic); 76 "Read Magic = 0x%04X\n", magic);
77
75 if (magic != AR5416_EEPROM_MAGIC) { 78 if (magic != AR5416_EEPROM_MAGIC) {
76 magic2 = swab16(magic); 79 magic2 = swab16(magic);
77 80
@@ -79,9 +82,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
79 need_swap = true; 82 need_swap = true;
80 eepdata = (u16 *)(&ah->eeprom); 83 eepdata = (u16 *)(&ah->eeprom);
81 84
82 for (addr = 0; 85 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
83 addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
84 addr++) {
85 temp = swab16(*eepdata); 86 temp = swab16(*eepdata);
86 *eepdata = temp; 87 *eepdata = temp;
87 eepdata++; 88 eepdata++;
@@ -89,13 +90,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
89 } else { 90 } else {
90 ath_print(common, ATH_DBG_FATAL, 91 ath_print(common, ATH_DBG_FATAL,
91 "Invalid EEPROM Magic. " 92 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n"); 93 "Endianness mismatch.\n");
93 return -EINVAL; 94 return -EINVAL;
94 } 95 }
95 } 96 }
96 } 97 }
97 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? 98
98 "True" : "False"); 99 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
100 need_swap ? "True" : "False");
99 101
100 if (need_swap) 102 if (need_swap)
101 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 103 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -108,6 +110,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
108 el = el / sizeof(u16); 110 el = el / sizeof(u16);
109 111
110 eepdata = (u16 *)(&ah->eeprom); 112 eepdata = (u16 *)(&ah->eeprom);
113
111 for (i = 0; i < el; i++) 114 for (i = 0; i < el; i++)
112 sum ^= *eepdata++; 115 sum ^= *eepdata++;
113 116
@@ -161,7 +164,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
161 return 0; 164 return 0;
162} 165}
163 166
164static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah, 167static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
165 enum eeprom_param param) 168 enum eeprom_param param)
166{ 169{
167 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 170 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
@@ -170,6 +173,7 @@ static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
170 u16 ver_minor; 173 u16 ver_minor;
171 174
172 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK; 175 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
176
173 switch (param) { 177 switch (param) {
174 case EEP_NFTHRESH_2: 178 case EEP_NFTHRESH_2:
175 return pModal->noiseFloorThreshCh[0]; 179 return pModal->noiseFloorThreshCh[0];
@@ -214,29 +218,30 @@ static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
214 } 218 }
215} 219}
216 220
217 221static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
218static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah, 222 struct ath9k_channel *chan,
219 struct ath9k_channel *chan, 223 struct cal_data_per_freq_ar9287 *pRawDataSet,
220 struct cal_data_per_freq_ar9287 *pRawDataSet, 224 u8 *bChans, u16 availPiers,
221 u8 *bChans, u16 availPiers, 225 u16 tPdGainOverlap,
222 u16 tPdGainOverlap, int16_t *pMinCalPower, 226 int16_t *pMinCalPower,
223 u16 *pPdGainBoundaries, u8 *pPDADCValues, 227 u16 *pPdGainBoundaries,
224 u16 numXpdGains) 228 u8 *pPDADCValues,
229 u16 numXpdGains)
225{ 230{
226#define TMP_VAL_VPD_TABLE \ 231#define TMP_VAL_VPD_TABLE \
227 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep)); 232 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
228 233
229 int i, j, k; 234 int i, j, k;
230 int16_t ss; 235 int16_t ss;
231 u16 idxL = 0, idxR = 0, numPiers; 236 u16 idxL = 0, idxR = 0, numPiers;
232 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; 237 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
233 u8 minPwrT4[AR9287_NUM_PD_GAINS]; 238 u8 minPwrT4[AR9287_NUM_PD_GAINS];
234 u8 maxPwrT4[AR9287_NUM_PD_GAINS]; 239 u8 maxPwrT4[AR9287_NUM_PD_GAINS];
235 int16_t vpdStep; 240 int16_t vpdStep;
236 int16_t tmpVal; 241 int16_t tmpVal;
237 u16 sizeCurrVpdTable, maxIndex, tgtIndex; 242 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
238 bool match; 243 bool match;
239 int16_t minDelta = 0; 244 int16_t minDelta = 0;
240 struct chan_centers centers; 245 struct chan_centers centers;
241 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS] 246 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
242 [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 247 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
@@ -253,18 +258,18 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
253 } 258 }
254 259
255 match = ath9k_hw_get_lower_upper_index( 260 match = ath9k_hw_get_lower_upper_index(
256 (u8)FREQ2FBIN(centers.synth_center, 261 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
257 IS_CHAN_2GHZ(chan)), bChans, numPiers, 262 bChans, numPiers, &idxL, &idxR);
258 &idxL, &idxR);
259 263
260 if (match) { 264 if (match) {
261 for (i = 0; i < numXpdGains; i++) { 265 for (i = 0; i < numXpdGains; i++) {
262 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 266 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
263 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 267 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
264 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 268 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
265 pRawDataSet[idxL].pwrPdg[i], 269 pRawDataSet[idxL].pwrPdg[i],
266 pRawDataSet[idxL].vpdPdg[i], 270 pRawDataSet[idxL].vpdPdg[i],
267 AR9287_PD_GAIN_ICEPTS, vpdTableI[i]); 271 AR9287_PD_GAIN_ICEPTS,
272 vpdTableI[i]);
268 } 273 }
269 } else { 274 } else {
270 for (i = 0; i < numXpdGains; i++) { 275 for (i = 0; i < numXpdGains; i++) {
@@ -275,41 +280,41 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
275 280
276 minPwrT4[i] = max(pPwrL[0], pPwrR[0]); 281 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
277 282
278 maxPwrT4[i] = 283 maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
279 min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1], 284 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
280 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
281 285
282 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 286 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
283 pPwrL, pVpdL, 287 pPwrL, pVpdL,
284 AR9287_PD_GAIN_ICEPTS, 288 AR9287_PD_GAIN_ICEPTS,
285 vpdTableL[i]); 289 vpdTableL[i]);
286 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], 290 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
287 pPwrR, pVpdR, 291 pPwrR, pVpdR,
288 AR9287_PD_GAIN_ICEPTS, 292 AR9287_PD_GAIN_ICEPTS,
289 vpdTableR[i]); 293 vpdTableR[i]);
290 294
291 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 295 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
292 vpdTableI[i][j] = 296 vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
293 (u8)(ath9k_hw_interpolate((u16) 297 (u16)FREQ2FBIN(centers. synth_center,
294 FREQ2FBIN(centers. synth_center, 298 IS_CHAN_2GHZ(chan)),
295 IS_CHAN_2GHZ(chan)), 299 bChans[idxL], bChans[idxR],
296 bChans[idxL], bChans[idxR], 300 vpdTableL[i][j], vpdTableR[i][j]));
297 vpdTableL[i][j], vpdTableR[i][j]));
298 } 301 }
299 } 302 }
300 } 303 }
301 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
302 304
305 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
303 k = 0; 306 k = 0;
307
304 for (i = 0; i < numXpdGains; i++) { 308 for (i = 0; i < numXpdGains; i++) {
305 if (i == (numXpdGains - 1)) 309 if (i == (numXpdGains - 1))
306 pPdGainBoundaries[i] = (u16)(maxPwrT4[i] / 2); 310 pPdGainBoundaries[i] =
311 (u16)(maxPwrT4[i] / 2);
307 else 312 else
308 pPdGainBoundaries[i] = (u16)((maxPwrT4[i] + 313 pPdGainBoundaries[i] =
309 minPwrT4[i+1]) / 4); 314 (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
310 315
311 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER, 316 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
312 pPdGainBoundaries[i]); 317 pPdGainBoundaries[i]);
313 318
314 319
315 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { 320 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
@@ -325,11 +330,12 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
325 ss = 0; 330 ss = 0;
326 } else 331 } else
327 ss = (int16_t)((pPdGainBoundaries[i-1] - 332 ss = (int16_t)((pPdGainBoundaries[i-1] -
328 (minPwrT4[i] / 2)) - 333 (minPwrT4[i] / 2)) -
329 tPdGainOverlap + 1 + minDelta); 334 tPdGainOverlap + 1 + minDelta);
330 335
331 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 336 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
332 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 337 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
338
333 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) { 339 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
334 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 340 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
335 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); 341 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
@@ -348,12 +354,13 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
348 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - 354 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
349 vpdTableI[i][sizeCurrVpdTable - 2]); 355 vpdTableI[i][sizeCurrVpdTable - 2]);
350 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 356 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
357
351 if (tgtIndex > maxIndex) { 358 if (tgtIndex > maxIndex) {
352 while ((ss <= tgtIndex) && 359 while ((ss <= tgtIndex) &&
353 (k < (AR9287_NUM_PDADC_VALUES - 1))) { 360 (k < (AR9287_NUM_PDADC_VALUES - 1))) {
354 tmpVal = (int16_t) TMP_VAL_VPD_TABLE; 361 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
355 pPDADCValues[k++] = (u8)((tmpVal > 255) ? 362 pPDADCValues[k++] =
356 255 : tmpVal); 363 (u8)((tmpVal > 255) ? 255 : tmpVal);
357 ss++; 364 ss++;
358 } 365 }
359 } 366 }
@@ -375,10 +382,9 @@ static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
375static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, 382static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
376 struct ath9k_channel *chan, 383 struct ath9k_channel *chan,
377 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, 384 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
378 u8 *pCalChans, u16 availPiers, 385 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
379 int8_t *pPwr)
380{ 386{
381 u16 idxL = 0, idxR = 0, numPiers; 387 u16 idxL = 0, idxR = 0, numPiers;
382 bool match; 388 bool match;
383 struct chan_centers centers; 389 struct chan_centers centers;
384 390
@@ -391,14 +397,13 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
391 397
392 match = ath9k_hw_get_lower_upper_index( 398 match = ath9k_hw_get_lower_upper_index(
393 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), 399 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
394 pCalChans, numPiers, 400 pCalChans, numPiers, &idxL, &idxR);
395 &idxL, &idxR);
396 401
397 if (match) { 402 if (match) {
398 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0]; 403 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
399 } else { 404 } else {
400 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] + 405 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
401 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2; 406 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
402 } 407 }
403 408
404} 409}
@@ -409,16 +414,22 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
409 u32 tmpVal; 414 u32 tmpVal;
410 u32 a; 415 u32 a;
411 416
417 /* Enable OLPC for chain 0 */
418
412 tmpVal = REG_READ(ah, 0xa270); 419 tmpVal = REG_READ(ah, 0xa270);
413 tmpVal = tmpVal & 0xFCFFFFFF; 420 tmpVal = tmpVal & 0xFCFFFFFF;
414 tmpVal = tmpVal | (0x3 << 24); 421 tmpVal = tmpVal | (0x3 << 24);
415 REG_WRITE(ah, 0xa270, tmpVal); 422 REG_WRITE(ah, 0xa270, tmpVal);
416 423
424 /* Enable OLPC for chain 1 */
425
417 tmpVal = REG_READ(ah, 0xb270); 426 tmpVal = REG_READ(ah, 0xb270);
418 tmpVal = tmpVal & 0xFCFFFFFF; 427 tmpVal = tmpVal & 0xFCFFFFFF;
419 tmpVal = tmpVal | (0x3 << 24); 428 tmpVal = tmpVal | (0x3 << 24);
420 REG_WRITE(ah, 0xb270, tmpVal); 429 REG_WRITE(ah, 0xb270, tmpVal);
421 430
431 /* Write the OLPC ref power for chain 0 */
432
422 if (chain == 0) { 433 if (chain == 0) {
423 tmpVal = REG_READ(ah, 0xa398); 434 tmpVal = REG_READ(ah, 0xa398);
424 tmpVal = tmpVal & 0xff00ffff; 435 tmpVal = tmpVal & 0xff00ffff;
@@ -427,6 +438,8 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
427 REG_WRITE(ah, 0xa398, tmpVal); 438 REG_WRITE(ah, 0xa398, tmpVal);
428 } 439 }
429 440
441 /* Write the OLPC ref power for chain 1 */
442
430 if (chain == 1) { 443 if (chain == 1) {
431 tmpVal = REG_READ(ah, 0xb398); 444 tmpVal = REG_READ(ah, 0xb398);
432 tmpVal = tmpVal & 0xff00ffff; 445 tmpVal = tmpVal & 0xff00ffff;
@@ -436,26 +449,27 @@ static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
436 } 449 }
437} 450}
438 451
439static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, 452static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
440 struct ath9k_channel *chan, 453 struct ath9k_channel *chan,
441 int16_t *pTxPowerIndexOffset) 454 int16_t *pTxPowerIndexOffset)
442{ 455{
443 struct ath_common *common = ath9k_hw_common(ah);
444 struct cal_data_per_freq_ar9287 *pRawDataset; 456 struct cal_data_per_freq_ar9287 *pRawDataset;
445 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 457 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
446 u8 *pCalBChans = NULL; 458 u8 *pCalBChans = NULL;
447 u16 pdGainOverlap_t2; 459 u16 pdGainOverlap_t2;
448 u8 pdadcValues[AR9287_NUM_PDADC_VALUES]; 460 u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
449 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK]; 461 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
450 u16 numPiers = 0, i, j; 462 u16 numPiers = 0, i, j;
451 int16_t tMinCalPower; 463 int16_t tMinCalPower;
452 u16 numXpdGain, xpdMask; 464 u16 numXpdGain, xpdMask;
453 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0}; 465 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
454 u32 reg32, regOffset, regChainOffset; 466 u32 reg32, regOffset, regChainOffset;
455 int16_t modalIdx, diff = 0; 467 int16_t modalIdx, diff = 0;
456 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 468 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
469
457 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 470 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
458 xpdMask = pEepData->modalHeader.xpdGain; 471 xpdMask = pEepData->modalHeader.xpdGain;
472
459 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= 473 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
460 AR9287_EEP_MINOR_VER_2) 474 AR9287_EEP_MINOR_VER_2)
461 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; 475 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
@@ -466,7 +480,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
466 if (IS_CHAN_2GHZ(chan)) { 480 if (IS_CHAN_2GHZ(chan)) {
467 pCalBChans = pEepData->calFreqPier2G; 481 pCalBChans = pEepData->calFreqPier2G;
468 numPiers = AR9287_NUM_2G_CAL_PIERS; 482 numPiers = AR9287_NUM_2G_CAL_PIERS;
469 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 483 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
470 pRawDatasetOpenLoop = 484 pRawDatasetOpenLoop =
471 (struct cal_data_op_loop_ar9287 *) 485 (struct cal_data_op_loop_ar9287 *)
472 pEepData->calPierData2G[0]; 486 pEepData->calPierData2G[0];
@@ -475,6 +489,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
475 } 489 }
476 490
477 numXpdGain = 0; 491 numXpdGain = 0;
492
478 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) { 493 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
479 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) { 494 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
480 if (numXpdGain >= AR9287_NUM_PD_GAINS) 495 if (numXpdGain >= AR9287_NUM_PD_GAINS)
@@ -499,7 +514,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
499 if (pEepData->baseEepHeader.txMask & (1 << i)) { 514 if (pEepData->baseEepHeader.txMask & (1 << i)) {
500 pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *) 515 pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)
501 pEepData->calPierData2G[i]; 516 pEepData->calPierData2G[i];
502 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 517 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
503 int8_t txPower; 518 int8_t txPower;
504 ar9287_eeprom_get_tx_gain_index(ah, chan, 519 ar9287_eeprom_get_tx_gain_index(ah, chan,
505 pRawDatasetOpenLoop, 520 pRawDatasetOpenLoop,
@@ -510,7 +525,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
510 pRawDataset = 525 pRawDataset =
511 (struct cal_data_per_freq_ar9287 *) 526 (struct cal_data_per_freq_ar9287 *)
512 pEepData->calPierData2G[i]; 527 pEepData->calPierData2G[i];
513 ath9k_hw_get_AR9287_gain_boundaries_pdadcs( 528 ath9k_hw_get_ar9287_gain_boundaries_pdadcs(
514 ah, chan, pRawDataset, 529 ah, chan, pRawDataset,
515 pCalBChans, numPiers, 530 pCalBChans, numPiers,
516 pdGainOverlap_t2, 531 pdGainOverlap_t2,
@@ -519,7 +534,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
519 } 534 }
520 535
521 if (i == 0) { 536 if (i == 0) {
522 if (!ath9k_hw_AR9287_get_eeprom( 537 if (!ath9k_hw_ar9287_get_eeprom(
523 ah, EEP_OL_PWRCTRL)) { 538 ah, EEP_OL_PWRCTRL)) {
524 REG_WRITE(ah, AR_PHY_TPCRG5 + 539 REG_WRITE(ah, AR_PHY_TPCRG5 +
525 regChainOffset, 540 regChainOffset,
@@ -555,7 +570,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
555 AR9287_NUM_PDADC_VALUES-diff]; 570 AR9287_NUM_PDADC_VALUES-diff];
556 } 571 }
557 572
558 if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 573 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
559 regOffset = AR_PHY_BASE + (672 << 2) + 574 regOffset = AR_PHY_BASE + (672 << 2) +
560 regChainOffset; 575 regChainOffset;
561 for (j = 0; j < 32; j++) { 576 for (j = 0; j < 32; j++) {
@@ -568,27 +583,6 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
568 ((pdadcValues[4*j + 3] 583 ((pdadcValues[4*j + 3]
569 & 0xFF) << 24) ; 584 & 0xFF) << 24) ;
570 REG_WRITE(ah, regOffset, reg32); 585 REG_WRITE(ah, regOffset, reg32);
571
572 ath_print(common, ATH_DBG_EEPROM,
573 "PDADC (%d,%4x): %4.4x "
574 "%8.8x\n",
575 i, regChainOffset, regOffset,
576 reg32);
577
578 ath_print(common, ATH_DBG_EEPROM,
579 "PDADC: Chain %d | "
580 "PDADC %3d Value %3d | "
581 "PDADC %3d Value %3d | "
582 "PDADC %3d Value %3d | "
583 "PDADC %3d Value %3d |\n",
584 i, 4 * j, pdadcValues[4 * j],
585 4 * j + 1,
586 pdadcValues[4 * j + 1],
587 4 * j + 2,
588 pdadcValues[4 * j + 2],
589 4 * j + 3,
590 pdadcValues[4 * j + 3]);
591
592 regOffset += 4; 586 regOffset += 4;
593 } 587 }
594 } 588 }
@@ -598,25 +592,29 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
598 *pTxPowerIndexOffset = 0; 592 *pTxPowerIndexOffset = 0;
599} 593}
600 594
601static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, 595static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
602 struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, 596 struct ath9k_channel *chan,
603 u16 AntennaReduction, u16 twiceMaxRegulatoryPower, 597 int16_t *ratesArray,
604 u16 powerLimit) 598 u16 cfgCtl,
599 u16 AntennaReduction,
600 u16 twiceMaxRegulatoryPower,
601 u16 powerLimit)
605{ 602{
606#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 603#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
607#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 604#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
605
608 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 606 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
609 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 607 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
610 static const u16 tpScaleReductionTable[5] = 608 static const u16 tpScaleReductionTable[5] =
611 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 609 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
612 int i; 610 int i;
613 int16_t twiceLargestAntenna; 611 int16_t twiceLargestAntenna;
614 struct cal_ctl_data_ar9287 *rep; 612 struct cal_ctl_data_ar9287 *rep;
615 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, 613 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
616 targetPowerCck = {0, {0, 0, 0, 0} }; 614 targetPowerCck = {0, {0, 0, 0, 0} };
617 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} }, 615 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
618 targetPowerCckExt = {0, {0, 0, 0, 0} }; 616 targetPowerCckExt = {0, {0, 0, 0, 0} };
619 struct cal_target_power_ht targetPowerHt20, 617 struct cal_target_power_ht targetPowerHt20,
620 targetPowerHt40 = {0, {0, 0, 0, 0} }; 618 targetPowerHt40 = {0, {0, 0, 0, 0} };
621 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; 619 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
622 u16 ctlModesFor11g[] = 620 u16 ctlModesFor11g[] =
@@ -634,8 +632,8 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
634 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0], 632 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
635 pEepData->modalHeader.antennaGainCh[1]); 633 pEepData->modalHeader.antennaGainCh[1]);
636 634
637 twiceLargestAntenna = (int16_t)min((AntennaReduction) - 635 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
638 twiceLargestAntenna, 0); 636 twiceLargestAntenna, 0);
639 637
640 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 638 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
641 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) 639 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
@@ -659,6 +657,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
659 if (IS_CHAN_2GHZ(chan)) { 657 if (IS_CHAN_2GHZ(chan)) {
660 numCtlModes = 658 numCtlModes =
661 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 659 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
660
662 pCtlMode = ctlModesFor11g; 661 pCtlMode = ctlModesFor11g;
663 662
664 ath9k_hw_get_legacy_target_powers(ah, chan, 663 ath9k_hw_get_legacy_target_powers(ah, chan,
@@ -829,7 +828,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
829#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN 828#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
830} 829}
831 830
832static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah, 831static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
833 struct ath9k_channel *chan, u16 cfgCtl, 832 struct ath9k_channel *chan, u16 cfgCtl,
834 u8 twiceAntennaReduction, 833 u8 twiceAntennaReduction,
835 u8 twiceMaxRegulatoryPower, 834 u8 twiceMaxRegulatoryPower,
@@ -837,12 +836,13 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
837{ 836{
838#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 837#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
839#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 838#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
839
840 struct ath_common *common = ath9k_hw_common(ah); 840 struct ath_common *common = ath9k_hw_common(ah);
841 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 841 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
842 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 842 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
843 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 843 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
844 int16_t ratesArray[Ar5416RateSize]; 844 int16_t ratesArray[Ar5416RateSize];
845 int16_t txPowerIndexOffset = 0; 845 int16_t txPowerIndexOffset = 0;
846 u8 ht40PowerIncForPdadc = 2; 846 u8 ht40PowerIncForPdadc = 2;
847 int i; 847 int i;
848 848
@@ -852,13 +852,13 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
852 AR9287_EEP_MINOR_VER_2) 852 AR9287_EEP_MINOR_VER_2)
853 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 853 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
854 854
855 ath9k_hw_set_AR9287_power_per_rate_table(ah, chan, 855 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
856 &ratesArray[0], cfgCtl, 856 &ratesArray[0], cfgCtl,
857 twiceAntennaReduction, 857 twiceAntennaReduction,
858 twiceMaxRegulatoryPower, 858 twiceMaxRegulatoryPower,
859 powerLimit); 859 powerLimit);
860 860
861 ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset); 861 ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
862 862
863 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 863 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
864 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 864 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
@@ -909,7 +909,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
909 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 909 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
910 910
911 if (IS_CHAN_HT40(chan)) { 911 if (IS_CHAN_HT40(chan)) {
912 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 912 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
913 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 913 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
914 ATH9K_POW_SM(ratesArray[rateHt40_3], 24) 914 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
915 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16) 915 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
@@ -965,12 +965,10 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
965 case 1: 965 case 1:
966 break; 966 break;
967 case 2: 967 case 2:
968 regulatory->max_power_level += 968 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
969 INCREASE_MAXPOW_BY_TWO_CHAIN;
970 break; 969 break;
971 case 3: 970 case 3:
972 regulatory->max_power_level += 971 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
973 INCREASE_MAXPOW_BY_THREE_CHAIN;
974 break; 972 break;
975 default: 973 default:
976 ath_print(common, ATH_DBG_EEPROM, 974 ath_print(common, ATH_DBG_EEPROM,
@@ -979,12 +977,12 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
979 } 977 }
980} 978}
981 979
982static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah, 980static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
983 struct ath9k_channel *chan) 981 struct ath9k_channel *chan)
984{ 982{
985} 983}
986 984
987static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah, 985static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
988 struct ath9k_channel *chan) 986 struct ath9k_channel *chan)
989{ 987{
990 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 988 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
@@ -1125,13 +1123,13 @@ static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
1125 pModal->xpaBiasLvl); 1123 pModal->xpaBiasLvl);
1126} 1124}
1127 1125
1128static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah, 1126static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
1129 enum ieee80211_band freq_band) 1127 enum ieee80211_band freq_band)
1130{ 1128{
1131 return 1; 1129 return 1;
1132} 1130}
1133 1131
1134static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah, 1132static u16 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1135 struct ath9k_channel *chan) 1133 struct ath9k_channel *chan)
1136{ 1134{
1137 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 1135 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
@@ -1140,11 +1138,12 @@ static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1140 return pModal->antCtrlCommon & 0xFFFF; 1138 return pModal->antCtrlCommon & 0xFFFF;
1141} 1139}
1142 1140
1143static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah, 1141static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
1144 u16 i, bool is2GHz) 1142 u16 i, bool is2GHz)
1145{ 1143{
1146#define EEP_MAP9287_SPURCHAN \ 1144#define EEP_MAP9287_SPURCHAN \
1147 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 1145 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1146
1148 struct ath_common *common = ath9k_hw_common(ah); 1147 struct ath_common *common = ath9k_hw_common(ah);
1149 u16 spur_val = AR_NO_SPUR; 1148 u16 spur_val = AR_NO_SPUR;
1150 1149
@@ -1171,15 +1170,15 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1171} 1170}
1172 1171
1173const struct eeprom_ops eep_ar9287_ops = { 1172const struct eeprom_ops eep_ar9287_ops = {
1174 .check_eeprom = ath9k_hw_AR9287_check_eeprom, 1173 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
1175 .get_eeprom = ath9k_hw_AR9287_get_eeprom, 1174 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1176 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom, 1175 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1177 .get_eeprom_ver = ath9k_hw_AR9287_get_eeprom_ver, 1176 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1178 .get_eeprom_rev = ath9k_hw_AR9287_get_eeprom_rev, 1177 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1179 .get_num_ant_config = ath9k_hw_AR9287_get_num_ant_config, 1178 .get_num_ant_config = ath9k_hw_ar9287_get_num_ant_config,
1180 .get_eeprom_antenna_cfg = ath9k_hw_AR9287_get_eeprom_antenna_cfg, 1179 .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
1181 .set_board_values = ath9k_hw_AR9287_set_board_values, 1180 .set_board_values = ath9k_hw_ar9287_set_board_values,
1182 .set_addac = ath9k_hw_AR9287_set_addac, 1181 .set_addac = ath9k_hw_ar9287_set_addac,
1183 .set_txpower = ath9k_hw_AR9287_set_txpower, 1182 .set_txpower = ath9k_hw_ar9287_set_txpower,
1184 .get_spur_channel = ath9k_hw_AR9287_get_spur_channel 1183 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
1185}; 1184};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-21 03:46:26 -0400