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authorLaxman Dewangan <ldewangan@nvidia.com>2012-08-09 07:00:37 -0400
committerStephen Warren <swarren@nvidia.com>2012-09-06 13:48:38 -0400
commit167e62798ccd4172d02c8f10ca7010a301498aa3 (patch)
tree1db5322b341f1b2de0d18a661ca487af350634e1
parent4cbe5a555fa58a79b6ecbb6c531b8bab0650778d (diff)
ARM: dt: tegra: cardhu: add entry for PMIC TPS65911.
Tegra30 based platform "cardhu" have the power management IC TPS65911 for the regulator. Adding DT entry for this device. Data are chosen from downstream kernel and making the voltage output as require by default for device to operate. The default interrupt line is HIGH from PMIC device and so inverting the interrupt detection line of PMU interrupt through configuring PMC. In this patch, do not registering LDO5 because the input supply for this rail is different for different version of cardhu i..e A02 and A04. The registration will be done once the dts file for cardhu A02 and A04 are added in follow on patches. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dts134
1 files changed, 134 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
index c169bced131e..6f9daaead5f9 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu.dts
@@ -126,6 +126,120 @@
126 ti,vsel0-state-high; 126 ti,vsel0-state-high;
127 ti,vsel1-state-high; 127 ti,vsel1-state-high;
128 }; 128 };
129
130 pmic: tps65911@2d {
131 compatible = "ti,tps65911";
132 reg = <0x2d>;
133
134 interrupts = <0 86 0x4>;
135 #interrupt-cells = <2>;
136 interrupt-controller;
137
138 #gpio-cells = <2>;
139 gpio-controller;
140
141 vcc1-supply = <&vdd_ac_bat_reg>;
142 vcc2-supply = <&vdd_ac_bat_reg>;
143 vcc3-supply = <&vio_reg>;
144 vcc5-supply = <&vdd_ac_bat_reg>;
145 vcc6-supply = <&vdd2_reg>;
146 vcc7-supply = <&vdd_ac_bat_reg>;
147 vccio-supply = <&vdd_ac_bat_reg>;
148
149 regulators {
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 vdd1_reg: regulator@0 {
154 reg = <0>;
155 regulator-compatible = "vdd1";
156 regulator-name = "vddio_ddr_1v2";
157 regulator-min-microvolt = <1200000>;
158 regulator-max-microvolt = <1200000>;
159 regulator-always-on;
160 };
161
162 vdd2_reg: regulator@1 {
163 reg = <1>;
164 regulator-compatible = "vdd2";
165 regulator-name = "vdd_1v5_gen";
166 regulator-min-microvolt = <1500000>;
167 regulator-max-microvolt = <1500000>;
168 regulator-always-on;
169 };
170
171 vddctrl_reg: regulator@2 {
172 reg = <2>;
173 regulator-compatible = "vddctrl";
174 regulator-name = "vdd_cpu,vdd_sys";
175 regulator-min-microvolt = <1000000>;
176 regulator-max-microvolt = <1000000>;
177 regulator-always-on;
178 };
179
180 vio_reg: regulator@3 {
181 reg = <3>;
182 regulator-compatible = "vio";
183 regulator-name = "vdd_1v8_gen";
184 regulator-min-microvolt = <1800000>;
185 regulator-max-microvolt = <1800000>;
186 regulator-always-on;
187 };
188
189 ldo1_reg: regulator@4 {
190 reg = <4>;
191 regulator-compatible = "ldo1";
192 regulator-name = "vdd_pexa,vdd_pexb";
193 regulator-min-microvolt = <1050000>;
194 regulator-max-microvolt = <1050000>;
195 };
196
197 ldo2_reg: regulator@5 {
198 reg = <5>;
199 regulator-compatible = "ldo2";
200 regulator-name = "vdd_sata,avdd_plle";
201 regulator-min-microvolt = <1050000>;
202 regulator-max-microvolt = <1050000>;
203 };
204
205 /* LDO3 is not connected to anything */
206
207 ldo4_reg: regulator@7 {
208 reg = <7>;
209 regulator-compatible = "ldo4";
210 regulator-name = "vdd_rtc";
211 regulator-min-microvolt = <1200000>;
212 regulator-max-microvolt = <1200000>;
213 regulator-always-on;
214 };
215
216 ldo6_reg: regulator@9 {
217 reg = <9>;
218 regulator-compatible = "ldo6";
219 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
220 regulator-min-microvolt = <1200000>;
221 regulator-max-microvolt = <1200000>;
222 };
223
224 ldo7_reg: regulator@10 {
225 reg = <10>;
226 regulator-compatible = "ldo7";
227 regulator-name = "vdd_pllm,x,u,a_p_c_s";
228 regulator-min-microvolt = <1200000>;
229 regulator-max-microvolt = <1200000>;
230 regulator-always-on;
231 };
232
233 ldo8_reg: regulator@11 {
234 reg = <11>;
235 regulator-compatible = "ldo8";
236 regulator-name = "vdd_ddr_hs";
237 regulator-min-microvolt = <1000000>;
238 regulator-max-microvolt = <1000000>;
239 regulator-always-on;
240 };
241 };
242 };
129 }; 243 };
130 244
131 ahub { 245 ahub {
@@ -134,6 +248,11 @@
134 }; 248 };
135 }; 249 };
136 250
251 pmc {
252 status = "okay";
253 nvidia,invert-interrupt;
254 };
255
137 sdhci@78000000 { 256 sdhci@78000000 {
138 status = "okay"; 257 status = "okay";
139 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 258 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
@@ -147,6 +266,21 @@
147 bus-width = <8>; 266 bus-width = <8>;
148 }; 267 };
149 268
269 regulators {
270 compatible = "simple-bus";
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 vdd_ac_bat_reg: regulator@0 {
275 compatible = "regulator-fixed";
276 reg = <0>;
277 regulator-name = "vdd_ac_bat";
278 regulator-min-microvolt = <5000000>;
279 regulator-max-microvolt = <5000000>;
280 regulator-always-on;
281 };
282 };
283
150 sound { 284 sound {
151 compatible = "nvidia,tegra-audio-wm8903-cardhu", 285 compatible = "nvidia,tegra-audio-wm8903-cardhu",
152 "nvidia,tegra-audio-wm8903"; 286 "nvidia,tegra-audio-wm8903";