litmus-rt.git - The LITMUS^RT kernel.

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author	Linus Torvalds <torvalds@linux-foundation.org>	2015-05-16 19:28:01 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2015-05-16 19:28:01 -0400
commit	1630ee5e01c68ebee5e91da42a56f1865ffbfa1b (patch)
tree	c9f7cab3b64e321751ab5af93ec1a949bb79a0c8
parent	6a8098a447206f8d2ce3954271657b6d79911d51 (diff)
parent	98fb1ffd8154890d7051750e61ff5548c3ee2ab2 (diff)

Merge tag 'upstream-4.1-rc4' of git://git.infradead.org/linux-ubifs

Pull UBI bufix from Richard Weinberger: "This contains a single bug fix for the UBI block driver" * tag 'upstream-4.1-rc4' of git://git.infradead.org/linux-ubifs: UBI: block: Add missing cache flushes

Diffstat

-rw-r--r--

drivers/mtd/ubi/block.c

1 files changed, 2 insertions, 0 deletions


diff --git a/drivers/mtd/ubi/block.c b/drivers/mtd/ubi/block.c index db2c05b6fe7f..c9eb78f10a0d 100644 --- a/drivers/mtd/ubi/block.c +++ b/drivers/mtd/ubi/block.c
@@ -310,6 +310,8 @@ static void ubiblock_do_work(struct work_struct *work)
310	blk_rq_map_sg(req->q, req, pdu->usgl.sg);	310	blk_rq_map_sg(req->q, req, pdu->usgl.sg);
311		311
312	ret = ubiblock_read(pdu);	312	ret = ubiblock_read(pdu);
		313	rq_flush_dcache_pages(req);
		314
313	blk_mq_end_request(req, ret);	315	blk_mq_end_request(req, ret);
314	}	316	}
315		317

/* * Driver for NEC VR4100 series General-purpose I/O Unit. * * Copyright (C) 2002 MontaVista Software Inc. * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> * Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/errno.h> #include <linux/fs.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/spinlock.h> #include <linux/types.h> #include <asm/io.h> #include <asm/vr41xx/giu.h> #include <asm/vr41xx/irq.h> #include <asm/vr41xx/vr41xx.h> MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>"); MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver"); MODULE_LICENSE("GPL"); static int major; /* default is dynamic major device number */ module_param(major, int, 0); MODULE_PARM_DESC(major, "Major device number"); #define GIUIOSELL 0x00 #define GIUIOSELH 0x02 #define GIUPIODL 0x04 #define GIUPIODH 0x06 #define GIUINTSTATL 0x08 #define GIUINTSTATH 0x0a #define GIUINTENL 0x0c #define GIUINTENH 0x0e #define GIUINTTYPL 0x10 #define GIUINTTYPH 0x12 #define GIUINTALSELL 0x14 #define GIUINTALSELH 0x16 #define GIUINTHTSELL 0x18 #define GIUINTHTSELH 0x1a #define GIUPODATL 0x1c #define GIUPODATEN 0x1c #define GIUPODATH 0x1e #define PIOEN0 0x0100 #define PIOEN1 0x0200 #define GIUPODAT 0x1e #define GIUFEDGEINHL 0x20 #define GIUFEDGEINHH 0x22 #define GIUREDGEINHL 0x24 #define GIUREDGEINHH 0x26 #define GIUUSEUPDN 0x1e0 #define GIUTERMUPDN 0x1e2 #define GPIO_HAS_PULLUPDOWN_IO 0x0001 #define GPIO_HAS_OUTPUT_ENABLE 0x0002 #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100 static spinlock_t giu_lock; static unsigned long giu_flags; static unsigned int giu_nr_pins; static void __iomem *giu_base; #define giu_read(offset) readw(giu_base + (offset)) #define giu_write(offset, value) writew((value), giu_base + (offset)) #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE) #define GIUINT_HIGH_OFFSET 16 #define GIUINT_HIGH_MAX 32 static inline uint16_t giu_set(uint16_t offset, uint16_t set) { uint16_t data; data = giu_read(offset); data |= set; giu_write(offset, data); return data; } static inline uint16_t giu_clear(uint16_t offset, uint16_t clear) { uint16_t data; data = giu_read(offset); data &= ~clear; giu_write(offset, data); return data; } static void ack_giuint_low(unsigned int irq) { giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq)); } static void mask_giuint_low(unsigned int irq) { giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); } static void mask_ack_giuint_low(unsigned int irq) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(irq); giu_clear(GIUINTENL, 1 << pin); giu_write(GIUINTSTATL, 1 << pin); } static void unmask_giuint_low(unsigned int irq) { giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq)); } static struct irq_chip giuint_low_irq_chip = { .name = "GIUINTL", .ack = ack_giuint_low, .mask = mask_giuint_low, .mask_ack = mask_ack_giuint_low, .unmask = unmask_giuint_low, }; static void ack_giuint_high(unsigned int irq) { giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); } static void mask_giuint_high(unsigned int irq) { giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); } static void mask_ack_giuint_high(unsigned int irq) { unsigned int pin; pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET; giu_clear(GIUINTENH, 1 << pin); giu_write(GIUINTSTATH, 1 << pin); } static void unmask_giuint_high(unsigned int irq) { giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET)); } static struct irq_chip giuint_high_irq_chip = { .name = "GIUINTH", .ack = ack_giuint_high, .mask = mask_giuint_high, .mask_ack = mask_ack_giuint_high, .unmask = unmask_giuint_high, }; static int giu_get_irq(unsigned int irq) { uint16_t pendl, pendh, maskl, maskh; int i; pendl = giu_read(GIUINTSTATL); pendh = giu_read(GIUINTSTATH); maskl = giu_read(GIUINTENL); maskh = giu_read(GIUINTENH); maskl &= pendl; maskh &= pendh; if (maskl) { for (i = 0; i < 16; i++) { if (maskl & (1 << i)) return GIU_IRQ(i); } } else if (maskh) { for (i = 0; i < 16; i++) { if (maskh & (1 << i)) return GIU_IRQ(i + GIUINT_HIGH_OFFSET); } } printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n", maskl, pendl, maskh, pendh); atomic_inc(&irq_err_count); return -EINVAL; } void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal) { uint16_t mask; if (pin < GIUINT_HIGH_OFFSET) { mask = 1 << pin; if (trigger != IRQ_TRIGGER_LEVEL) { giu_set(GIUINTTYPL, mask); if (signal == IRQ_SIGNAL_HOLD) giu_set(GIUINTHTSELL, mask); else giu_clear(GIUINTHTSELL, mask); if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) { switch (trigger) { case IRQ_TRIGGER_EDGE_FALLING: giu_set(GIUFEDGEINHL, mask); giu_clear(GIUREDGEINHL, mask); break; case IRQ_TRIGGER_EDGE_RISING: giu_clear(GIUFEDGEINHL, mask); giu_set(GIUREDGEINHL, mask); break; default: giu_set(GIUFEDGEINHL, mask); giu_set(GIUREDGEINHL, mask); break; } } set_irq_chip_and_handler(GIU_IRQ(pin), &giuint_low_irq_chip, handle_edge_irq); } else { giu_clear(GIUINTTYPL, mask); giu_clear(GIUINTHTSELL, mask); set_irq_chip_and_handler(GIU_IRQ(pin), &giuint_low_irq_chip, handle_level_irq); } giu_write(GIUINTSTATL, mask); } else if (pin < GIUINT_HIGH_MAX) { mask = 1 << (pin - GIUINT_HIGH_OFFSET); if (trigger != IRQ_TRIGGER_LEVEL) { giu_set(GIUINTTYPH, mask); if (signal == IRQ_SIGNAL_HOLD) giu_set(GIUINTHTSELH, mask); else giu_clear(GIUINTHTSELH, mask); if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) { switch (trigger) { case IRQ_TRIGGER_EDGE_FALLING: giu_set(GIUFEDGEINHH, mask); giu_clear(GIUREDGEINHH, mask); break; case IRQ_TRIGGER_EDGE_RISING: giu_clear(GIUFEDGEINHH, mask); giu_set(GIUREDGEINHH, mask); break; default: giu_set(GIUFEDGEINHH, mask); giu_set(GIUREDGEINHH, mask); break; } }


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