diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2013-11-29 20:40:55 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-01-22 22:38:54 -0500 |
commit | 1522ecae6522a77545118774af7ecaa6252158eb (patch) | |
tree | 4442d9756ae84219632bc0d0059db15c095afb04 | |
parent | 09692e5b4efb1ed1d91b4e9e4c7a31b7dbe06f03 (diff) |
drm/nouveau/bios: timing 2.0 entries can have subentries
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
6 files changed, 34 insertions, 23 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h index 963694b54224..2e814827d64d 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h | |||
@@ -1,8 +1,9 @@ | |||
1 | #ifndef __NVBIOS_TIMING_H__ | 1 | #ifndef __NVBIOS_TIMING_H__ |
2 | #define __NVBIOS_TIMING_H__ | 2 | #define __NVBIOS_TIMING_H__ |
3 | 3 | ||
4 | u16 nvbios_timing_table(struct nouveau_bios *, | 4 | u16 nvbios_timingTe(struct nouveau_bios *, |
5 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | 5 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); |
6 | u16 nvbios_timing_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); | 6 | u16 nvbios_timingEe(struct nouveau_bios *, int idx, |
7 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | ||
7 | 8 | ||
8 | #endif | 9 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c index 151c2d6aaee8..ddcc595d9a01 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c | |||
@@ -27,8 +27,8 @@ | |||
27 | #include <subdev/bios/timing.h> | 27 | #include <subdev/bios/timing.h> |
28 | 28 | ||
29 | u16 | 29 | u16 |
30 | nvbios_timing_table(struct nouveau_bios *bios, | 30 | nvbios_timingTe(struct nouveau_bios *bios, |
31 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | 31 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) |
32 | { | 32 | { |
33 | struct bit_entry bit_P; | 33 | struct bit_entry bit_P; |
34 | u16 timing = 0x0000; | 34 | u16 timing = 0x0000; |
@@ -47,11 +47,15 @@ nvbios_timing_table(struct nouveau_bios *bios, | |||
47 | *hdr = nv_ro08(bios, timing + 1); | 47 | *hdr = nv_ro08(bios, timing + 1); |
48 | *cnt = nv_ro08(bios, timing + 2); | 48 | *cnt = nv_ro08(bios, timing + 2); |
49 | *len = nv_ro08(bios, timing + 3); | 49 | *len = nv_ro08(bios, timing + 3); |
50 | *snr = 0; | ||
51 | *ssz = 0; | ||
50 | return timing; | 52 | return timing; |
51 | case 0x20: | 53 | case 0x20: |
52 | *hdr = nv_ro08(bios, timing + 1); | 54 | *hdr = nv_ro08(bios, timing + 1); |
53 | *cnt = nv_ro08(bios, timing + 3); | 55 | *cnt = nv_ro08(bios, timing + 5); |
54 | *len = nv_ro08(bios, timing + 2); | 56 | *len = nv_ro08(bios, timing + 2); |
57 | *snr = nv_ro08(bios, timing + 4); | ||
58 | *ssz = nv_ro08(bios, timing + 3); | ||
55 | return timing; | 59 | return timing; |
56 | default: | 60 | default: |
57 | break; | 61 | break; |
@@ -63,11 +67,17 @@ nvbios_timing_table(struct nouveau_bios *bios, | |||
63 | } | 67 | } |
64 | 68 | ||
65 | u16 | 69 | u16 |
66 | nvbios_timing_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) | 70 | nvbios_timingEe(struct nouveau_bios *bios, int idx, |
71 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | ||
67 | { | 72 | { |
68 | u8 hdr, cnt; | 73 | u8 snr, ssz; |
69 | u16 timing = nvbios_timing_table(bios, ver, &hdr, &cnt, len); | 74 | u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); |
70 | if (timing && idx < cnt) | 75 | if (timing && idx < *cnt) { |
71 | return timing + hdr + (idx * *len); | 76 | timing += *hdr + idx * (*len + (snr * ssz)); |
77 | *hdr = *len; | ||
78 | *cnt = snr; | ||
79 | *len = ssz; | ||
80 | return timing; | ||
81 | } | ||
72 | return 0x0000; | 82 | return 0x0000; |
73 | } | 83 | } |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c index 38541db800d2..c7fdb3a9e88b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c | |||
@@ -74,7 +74,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
74 | u32 data; | 74 | u32 data; |
75 | u8 size; | 75 | u8 size; |
76 | } ramcfg, timing; | 76 | } ramcfg, timing; |
77 | u8 ver, hdr, cnt, strap; | 77 | u8 ver, hdr, cnt, len, strap; |
78 | int N1, M1, N2, M2, P; | 78 | int N1, M1, N2, M2, P; |
79 | int ret, i; | 79 | int ret, i; |
80 | 80 | ||
@@ -102,7 +102,8 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
102 | /* lookup memory timings, if bios says they're present */ | 102 | /* lookup memory timings, if bios says they're present */ |
103 | strap = nv_ro08(bios, ramcfg.data + 0x01); | 103 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
104 | if (strap != 0xff) { | 104 | if (strap != 0xff) { |
105 | timing.data = nvbios_timing_entry(bios, strap, &ver, &hdr); | 105 | timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, |
106 | &cnt, &len); | ||
106 | if (!timing.data || ver != 0x10 || hdr < 0x12) { | 107 | if (!timing.data || ver != 0x10 || hdr < 0x12) { |
107 | nv_error(pfb, "invalid/missing timing entry " | 108 | nv_error(pfb, "invalid/missing timing entry " |
108 | "%02x %04x %02x %02x\n", | 109 | "%02x %04x %02x %02x\n", |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c index f23c78f4b1c7..08d3ef6c2e69 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | |||
@@ -79,7 +79,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
79 | struct nva3_ram *ram = (void *)pfb->ram; | 79 | struct nva3_ram *ram = (void *)pfb->ram; |
80 | struct nva3_ramfuc *fuc = &ram->fuc; | 80 | struct nva3_ramfuc *fuc = &ram->fuc; |
81 | struct nva3_clock_info mclk; | 81 | struct nva3_clock_info mclk; |
82 | u8 ver, cnt, strap; | 82 | u8 ver, cnt, len, strap; |
83 | u32 data; | 83 | u32 data; |
84 | struct { | 84 | struct { |
85 | u32 data; | 85 | u32 data; |
@@ -113,8 +113,8 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
113 | /* lookup memory timings, if bios says they're present */ | 113 | /* lookup memory timings, if bios says they're present */ |
114 | strap = nv_ro08(bios, ramcfg.data + 0x01); | 114 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
115 | if (strap != 0xff) { | 115 | if (strap != 0xff) { |
116 | timing.data = nvbios_timing_entry(bios, strap, &ver, | 116 | timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, |
117 | &timing.size); | 117 | &cnt, &len); |
118 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { | 118 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { |
119 | nv_error(pfb, "invalid/missing timing entry\n"); | 119 | nv_error(pfb, "invalid/missing timing entry\n"); |
120 | return -EINVAL; | 120 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c index 3727cba0a692..9abc625d9b52 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c | |||
@@ -133,7 +133,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
133 | struct nouveau_bios *bios = nouveau_bios(pfb); | 133 | struct nouveau_bios *bios = nouveau_bios(pfb); |
134 | struct nvc0_ram *ram = (void *)pfb->ram; | 134 | struct nvc0_ram *ram = (void *)pfb->ram; |
135 | struct nvc0_ramfuc *fuc = &ram->fuc; | 135 | struct nvc0_ramfuc *fuc = &ram->fuc; |
136 | u8 ver, cnt, strap; | 136 | u8 ver, cnt, len, strap; |
137 | struct { | 137 | struct { |
138 | u32 data; | 138 | u32 data; |
139 | u8 size; | 139 | u8 size; |
@@ -167,8 +167,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
167 | /* lookup memory timings, if bios says they're present */ | 167 | /* lookup memory timings, if bios says they're present */ |
168 | strap = nv_ro08(bios, ramcfg.data + 0x01); | 168 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
169 | if (strap != 0xff) { | 169 | if (strap != 0xff) { |
170 | timing.data = nvbios_timing_entry(bios, strap, &ver, | 170 | timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, |
171 | &timing.size); | 171 | &cnt, &len); |
172 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { | 172 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { |
173 | nv_error(pfb, "invalid/missing timing entry\n"); | 173 | nv_error(pfb, "invalid/missing timing entry\n"); |
174 | return -EINVAL; | 174 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index abaace7bcc74..b085691c50dc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | |||
@@ -907,7 +907,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
907 | struct nve0_ramfuc *fuc = &ram->fuc; | 907 | struct nve0_ramfuc *fuc = &ram->fuc; |
908 | int ret, refclk, strap, i; | 908 | int ret, refclk, strap, i; |
909 | u32 data; | 909 | u32 data; |
910 | u8 cnt; | 910 | u8 cnt, len; |
911 | 911 | ||
912 | /* lookup memory config data relevant to the target frequency */ | 912 | /* lookup memory config data relevant to the target frequency */ |
913 | ram->base.rammap.data = nvbios_rammap_match(bios, freq / 1000, | 913 | ram->base.rammap.data = nvbios_rammap_match(bios, freq / 1000, |
@@ -940,9 +940,8 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
940 | strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); | 940 | strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); |
941 | if (strap != 0xff) { | 941 | if (strap != 0xff) { |
942 | ram->base.timing.data = | 942 | ram->base.timing.data = |
943 | nvbios_timing_entry(bios, strap, | 943 | nvbios_timingEe(bios, strap, &ram->base.timing.version, |
944 | &ram->base.timing.version, | 944 | &ram->base.timing.size, &cnt, &len); |
945 | &ram->base.timing.size); | ||
946 | if (!ram->base.timing.data || | 945 | if (!ram->base.timing.data || |
947 | ram->base.timing.version != 0x20 || | 946 | ram->base.timing.version != 0x20 || |
948 | ram->base.timing.size < 0x33) { | 947 | ram->base.timing.size < 0x33) { |