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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2013-07-26 09:18:00 -0400
committerJason Cooper <jason@lakedaemon.net>2013-08-06 10:11:27 -0400
commit14fd8ed0a7fd199131425fe9e802173c4ba6a4e9 (patch)
treedb73d939f2487613d91c778ec197d4f27f589a22
parentde1af8d486ae05922efbb69b93b902b197dfaca9 (diff)
ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts32
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi101
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts67
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts42
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi222
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi261
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi409
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts18
9 files changed, 612 insertions, 542 deletions
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 19341d26f7a3..2471d9da767b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -28,6 +28,22 @@
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
29 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; 29 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
30 30
31 pcie-controller {
32 status = "okay";
33
34 /* Internal mini-PCIe connector */
35 pcie@1,0 {
36 /* Port 0, Lane 0 */
37 status = "okay";
38 };
39
40 /* Connected on the PCB to a USB 3.0 XHCI controller */
41 pcie@2,0 {
42 /* Port 1, Lane 0 */
43 status = "okay";
44 };
45 };
46
31 internal-regs { 47 internal-regs {
32 serial@12000 { 48 serial@12000 {
33 clock-frequency = <200000000>; 49 clock-frequency = <200000000>;
@@ -123,22 +139,6 @@
123 reg = <0x25>; 139 reg = <0x25>;
124 }; 140 };
125 }; 141 };
126
127 pcie-controller {
128 status = "okay";
129
130 /* Internal mini-PCIe connector */
131 pcie@1,0 {
132 /* Port 0, Lane 0 */
133 status = "okay";
134 };
135
136 /* Connected on the PCB to a USB 3.0 XHCI controller */
137 pcie@2,0 {
138 /* Port 1, Lane 0 */
139 status = "okay";
140 };
141 };
142 }; 142 };
143 }; 143 };
144}; 144};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 073dd203a819..e984ce6bb33f 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -44,6 +44,8 @@
44 #size-cells = <1>; 44 #size-cells = <1>;
45 controller = <&mbusc>; 45 controller = <&mbusc>;
46 interrupt-parent = <&mpic>; 46 interrupt-parent = <&mpic>;
47 pcie-mem-aperture = <0xe0000000 0x8000000>;
48 pcie-io-aperture = <0xe8000000 0x100000>;
47 49
48 devbus-bootcs { 50 devbus-bootcs {
49 compatible = "marvell,mvebu-devbus"; 51 compatible = "marvell,mvebu-devbus";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index bd21d497c13f..648e5303446e 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -36,6 +36,59 @@
36 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; 36 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
37 }; 37 };
38 38
39 pcie-controller {
40 compatible = "marvell,armada-370-pcie";
41 status = "disabled";
42 device_type = "pci";
43
44 #address-cells = <3>;
45 #size-cells = <2>;
46
47 bus-range = <0x00 0xff>;
48
49 ranges =
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
56
57 pcie@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 reg = <0x0800 0 0 0 0>;
61 #address-cells = <3>;
62 #size-cells = <2>;
63 #interrupt-cells = <1>;
64 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
65 0x81000000 0 0 0x81000000 0x1 0 1 0>;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &mpic 58>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gateclk 5>;
71 status = "disabled";
72 };
73
74 pcie@2,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
77 reg = <0x1000 0 0 0 0>;
78 #address-cells = <3>;
79 #size-cells = <2>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
82 0x81000000 0 0 0x81000000 0x2 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &mpic 62>;
85 marvell,pcie-port = <1>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 9>;
88 status = "disabled";
89 };
90 };
91
39 internal-regs { 92 internal-regs {
40 system-controller@18200 { 93 system-controller@18200 {
41 compatible = "marvell,armada-370-xp-system-controller"; 94 compatible = "marvell,armada-370-xp-system-controller";
@@ -174,54 +227,6 @@
174 0x18304 0x4>; 227 0x18304 0x4>;
175 status = "okay"; 228 status = "okay";
176 }; 229 };
177
178 pcie-controller {
179 compatible = "marvell,armada-370-pcie";
180 status = "disabled";
181 device_type = "pci";
182
183 #address-cells = <3>;
184 #size-cells = <2>;
185
186 bus-range = <0x00 0xff>;
187
188 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
189 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
190 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
191 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
192
193 pcie@1,0 {
194 device_type = "pci";
195 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
196 reg = <0x0800 0 0 0 0>;
197 #address-cells = <3>;
198 #size-cells = <2>;
199 #interrupt-cells = <1>;
200 ranges;
201 interrupt-map-mask = <0 0 0 0>;
202 interrupt-map = <0 0 0 0 &mpic 58>;
203 marvell,pcie-port = <0>;
204 marvell,pcie-lane = <0>;
205 clocks = <&gateclk 5>;
206 status = "disabled";
207 };
208
209 pcie@2,0 {
210 device_type = "pci";
211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
212 reg = <0x1000 0 0 0 0>;
213 #address-cells = <3>;
214 #size-cells = <2>;
215 #interrupt-cells = <1>;
216 ranges;
217 interrupt-map-mask = <0 0 0 0>;
218 interrupt-map = <0 0 0 0 &mpic 62>;
219 marvell,pcie-port = <1>;
220 marvell,pcie-lane = <0>;
221 clocks = <&gateclk 9>;
222 status = "disabled";
223 };
224 };
225 }; 230 };
226 }; 231 };
227}; 232};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 76ae1a95111b..bcf6d79a57ec 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -62,6 +62,39 @@
62 }; 62 };
63 }; 63 };
64 64
65 pcie-controller {
66 status = "okay";
67
68 /*
69 * All 6 slots are physically present as
70 * standard PCIe slots on the board.
71 */
72 pcie@1,0 {
73 /* Port 0, Lane 0 */
74 status = "okay";
75 };
76 pcie@2,0 {
77 /* Port 0, Lane 1 */
78 status = "okay";
79 };
80 pcie@3,0 {
81 /* Port 0, Lane 2 */
82 status = "okay";
83 };
84 pcie@4,0 {
85 /* Port 0, Lane 3 */
86 status = "okay";
87 };
88 pcie@9,0 {
89 /* Port 2, Lane 0 */
90 status = "okay";
91 };
92 pcie@10,0 {
93 /* Port 3, Lane 0 */
94 status = "okay";
95 };
96 };
97
65 internal-regs { 98 internal-regs {
66 serial@12000 { 99 serial@12000 {
67 clock-frequency = <250000000>; 100 clock-frequency = <250000000>;
@@ -155,40 +188,6 @@
155 spi-max-frequency = <20000000>; 188 spi-max-frequency = <20000000>;
156 }; 189 };
157 }; 190 };
158
159 pcie-controller {
160 status = "okay";
161
162 /*
163 * All 6 slots are physically present as
164 * standard PCIe slots on the board.
165 */
166 pcie@1,0 {
167 /* Port 0, Lane 0 */
168 status = "okay";
169 };
170 pcie@2,0 {
171 /* Port 0, Lane 1 */
172 status = "okay";
173 };
174 pcie@3,0 {
175 /* Port 0, Lane 2 */
176 status = "okay";
177 };
178 pcie@4,0 {
179 /* Port 0, Lane 3 */
180 status = "okay";
181 };
182 pcie@9,0 {
183 /* Port 2, Lane 0 */
184 status = "okay";
185 };
186 pcie@10,0 {
187 /* Port 3, Lane 0 */
188 status = "okay";
189 };
190 };
191
192 }; 191 };
193 }; 192 };
194}; 193};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 8c0de201c65b..2298e4a910e2 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -71,6 +71,27 @@
71 }; 71 };
72 }; 72 };
73 73
74 pcie-controller {
75 status = "okay";
76
77 /*
78 * The 3 slots are physically present as
79 * standard PCIe slots on the board.
80 */
81 pcie@1,0 {
82 /* Port 0, Lane 0 */
83 status = "okay";
84 };
85 pcie@9,0 {
86 /* Port 2, Lane 0 */
87 status = "okay";
88 };
89 pcie@10,0 {
90 /* Port 3, Lane 0 */
91 status = "okay";
92 };
93 };
94
74 internal-regs { 95 internal-regs {
75 serial@12000 { 96 serial@12000 {
76 clock-frequency = <250000000>; 97 clock-frequency = <250000000>;
@@ -154,27 +175,6 @@
154 spi-max-frequency = <108000000>; 175 spi-max-frequency = <108000000>;
155 }; 176 };
156 }; 177 };
157
158 pcie-controller {
159 status = "okay";
160
161 /*
162 * The 3 slots are physically present as
163 * standard PCIe slots on the board.
164 */
165 pcie@1,0 {
166 /* Port 0, Lane 0 */
167 status = "okay";
168 };
169 pcie@9,0 {
170 /* Port 2, Lane 0 */
171 status = "okay";
172 };
173 pcie@10,0 {
174 /* Port 3, Lane 0 */
175 status = "okay";
176 };
177 };
178 }; 178 };
179 }; 179 };
180}; 180};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa383e07f..f093e3974d6a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -44,6 +44,124 @@
44 }; 44 };
45 45
46 soc { 46 soc {
47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x4/x1.
51 */
52 pcie-controller {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 bus-range = <0x00 0xff>;
61
62 ranges =
63 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
64 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
69 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
70 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
71 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
72 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
73 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
74 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
75 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
76 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
77 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
78
79 pcie@1,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
82 reg = <0x0800 0 0 0 0>;
83 #address-cells = <3>;
84 #size-cells = <2>;
85 #interrupt-cells = <1>;
86 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
87 0x81000000 0 0 0x81000000 0x1 0 1 0>;
88 interrupt-map-mask = <0 0 0 0>;
89 interrupt-map = <0 0 0 0 &mpic 58>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
93 status = "disabled";
94 };
95
96 pcie@2,0 {
97 device_type = "pci";
98 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
99 reg = <0x1000 0 0 0 0>;
100 #address-cells = <3>;
101 #size-cells = <2>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
104 0x81000000 0 0 0x81000000 0x2 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 59>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <1>;
109 clocks = <&gateclk 6>;
110 status = "disabled";
111 };
112
113 pcie@3,0 {
114 device_type = "pci";
115 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
116 reg = <0x1800 0 0 0 0>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
121 0x81000000 0 0 0x81000000 0x3 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 60>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <2>;
126 clocks = <&gateclk 7>;
127 status = "disabled";
128 };
129
130 pcie@4,0 {
131 device_type = "pci";
132 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
133 reg = <0x2000 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
138 0x81000000 0 0 0x81000000 0x4 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 61>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <3>;
143 clocks = <&gateclk 8>;
144 status = "disabled";
145 };
146
147 pcie@9,0 {
148 device_type = "pci";
149 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
150 reg = <0x4800 0 0 0 0>;
151 #address-cells = <3>;
152 #size-cells = <2>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
155 0x81000000 0 0 0x81000000 0x9 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 99>;
158 marvell,pcie-port = <2>;
159 marvell,pcie-lane = <0>;
160 clocks = <&gateclk 26>;
161 status = "disabled";
162 };
163 };
164
47 internal-regs { 165 internal-regs {
48 pinctrl { 166 pinctrl {
49 compatible = "marvell,mv78230-pinctrl"; 167 compatible = "marvell,mv78230-pinctrl";
@@ -77,110 +195,6 @@
77 #interrupts-cells = <2>; 195 #interrupts-cells = <2>;
78 interrupts = <87>, <88>, <89>; 196 interrupts = <87>, <88>, <89>;
79 }; 197 };
80
81 /*
82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
83 * configured as x4 or quad x1 lanes. One unit is
84 * x4/x1.
85 */
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
88 status = "disabled";
89 device_type = "pci";
90
91#address-cells = <3>;
92#size-cells = <2>;
93
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
183 };
184 }; 198 };
185 }; 199 };
186}; 200};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 985373a04561..6dc3921df9b3 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -45,6 +45,145 @@
45 }; 45 };
46 46
47 soc { 47 soc {
48 /*
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
51 * x4/x1.
52 */
53 pcie-controller {
54 compatible = "marvell,armada-xp-pcie";
55 status = "disabled";
56 device_type = "pci";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60
61 bus-range = <0x00 0xff>;
62
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
69 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
70 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
71 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
72 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
73 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
74 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
75 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
76 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
77 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
78 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
79 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
80 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
81 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
82 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
83
84 pcie@1,0 {
85 device_type = "pci";
86 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
87 reg = <0x0800 0 0 0 0>;
88 #address-cells = <3>;
89 #size-cells = <2>;
90 #interrupt-cells = <1>;
91 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
92 0x81000000 0 0 0x81000000 0x1 0 1 0>;
93 interrupt-map-mask = <0 0 0 0>;
94 interrupt-map = <0 0 0 0 &mpic 58>;
95 marvell,pcie-port = <0>;
96 marvell,pcie-lane = <0>;
97 clocks = <&gateclk 5>;
98 status = "disabled";
99 };
100
101 pcie@2,0 {
102 device_type = "pci";
103 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
104 reg = <0x1000 0 0 0 0>;
105 #address-cells = <3>;
106 #size-cells = <2>;
107 #interrupt-cells = <1>;
108 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
109 0x81000000 0 0 0x81000000 0x2 0 1 0>;
110 interrupt-map-mask = <0 0 0 0>;
111 interrupt-map = <0 0 0 0 &mpic 59>;
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <1>;
114 clocks = <&gateclk 6>;
115 status = "disabled";
116 };
117
118 pcie@3,0 {
119 device_type = "pci";
120 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
121 reg = <0x1800 0 0 0 0>;
122 #address-cells = <3>;
123 #size-cells = <2>;
124 #interrupt-cells = <1>;
125 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
126 0x81000000 0 0 0x81000000 0x3 0 1 0>;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 60>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <2>;
131 clocks = <&gateclk 7>;
132 status = "disabled";
133 };
134
135 pcie@4,0 {
136 device_type = "pci";
137 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
138 reg = <0x2000 0 0 0 0>;
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
143 0x81000000 0 0 0x81000000 0x4 0 1 0>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 61>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <3>;
148 clocks = <&gateclk 8>;
149 status = "disabled";
150 };
151
152 pcie@9,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
155 reg = <0x4800 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
160 0x81000000 0 0 0x81000000 0x9 0 1 0>;
161 interrupt-map-mask = <0 0 0 0>;
162 interrupt-map = <0 0 0 0 &mpic 99>;
163 marvell,pcie-port = <2>;
164 marvell,pcie-lane = <0>;
165 clocks = <&gateclk 26>;
166 status = "disabled";
167 };
168
169 pcie@10,0 {
170 device_type = "pci";
171 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
172 reg = <0x5000 0 0 0 0>;
173 #address-cells = <3>;
174 #size-cells = <2>;
175 #interrupt-cells = <1>;
176 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
177 0x81000000 0 0 0x81000000 0xa 0 1 0>;
178 interrupt-map-mask = <0 0 0 0>;
179 interrupt-map = <0 0 0 0 &mpic 103>;
180 marvell,pcie-port = <3>;
181 marvell,pcie-lane = <0>;
182 clocks = <&gateclk 27>;
183 status = "disabled";
184 };
185 };
186
48 internal-regs { 187 internal-regs {
49 pinctrl { 188 pinctrl {
50 compatible = "marvell,mv78260-pinctrl"; 189 compatible = "marvell,mv78260-pinctrl";
@@ -97,128 +236,6 @@
97 clocks = <&gateclk 1>; 236 clocks = <&gateclk 1>;
98 status = "disabled"; 237 status = "disabled";
99 }; 238 };
100
101 /*
102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
103 * configured as x4 or quad x1 lanes. One unit is
104 * x4/x1.
105 */
106 pcie-controller {
107 compatible = "marvell,armada-xp-pcie";
108 status = "disabled";
109 device_type = "pci";
110
111 #address-cells = <3>;
112 #size-cells = <2>;
113
114 bus-range = <0x00 0xff>;
115
116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
125
126 pcie@1,0 {
127 device_type = "pci";
128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
129 reg = <0x0800 0 0 0 0>;
130 #address-cells = <3>;
131 #size-cells = <2>;
132 #interrupt-cells = <1>;
133 ranges;
134 interrupt-map-mask = <0 0 0 0>;
135 interrupt-map = <0 0 0 0 &mpic 58>;
136 marvell,pcie-port = <0>;
137 marvell,pcie-lane = <0>;
138 clocks = <&gateclk 5>;
139 status = "disabled";
140 };
141
142 pcie@2,0 {
143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
221 };
222 }; 239 };
223 }; 240 };
224}; 241};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index f8bf25a20a71..a6661e3aea23 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -61,6 +61,227 @@
61 }; 61 };
62 62
63 soc { 63 soc {
64 /*
65 * MV78460 has 4 PCIe units Gen2.0: Two units can be
66 * configured as x4 or quad x1 lanes. Two units are
67 * x4/x1.
68 */
69 pcie-controller {
70 compatible = "marvell,armada-xp-pcie";
71 status = "disabled";
72 device_type = "pci";
73
74 #address-cells = <3>;
75 #size-cells = <2>;
76
77 bus-range = <0x00 0xff>;
78
79 ranges =
80 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
81 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
82 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
83 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
84 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
85 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
86 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
87 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
88 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
89 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
90 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
91 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
92 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
93 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
94 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
95 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
96 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
97 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
98
99 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
100 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
101 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
102 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
103 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
104 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
105 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
106 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
107
108 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
109 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
110
111 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
112 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
113
114 pcie@1,0 {
115 device_type = "pci";
116 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
117 reg = <0x0800 0 0 0 0>;
118 #address-cells = <3>;
119 #size-cells = <2>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
122 0x81000000 0 0 0x81000000 0x1 0 1 0>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 58>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <0>;
127 clocks = <&gateclk 5>;
128 status = "disabled";
129 };
130
131 pcie@2,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
139 0x81000000 0 0 0x81000000 0x2 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 59>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <1>;
144 clocks = <&gateclk 6>;
145 status = "disabled";
146 };
147
148 pcie@3,0 {
149 device_type = "pci";
150 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
151 reg = <0x1800 0 0 0 0>;
152 #address-cells = <3>;
153 #size-cells = <2>;
154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
156 0x81000000 0 0 0x81000000 0x3 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 60>;
159 marvell,pcie-port = <0>;
160 marvell,pcie-lane = <2>;
161 clocks = <&gateclk 7>;
162 status = "disabled";
163 };
164
165 pcie@4,0 {
166 device_type = "pci";
167 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
168 reg = <0x2000 0 0 0 0>;
169 #address-cells = <3>;
170 #size-cells = <2>;
171 #interrupt-cells = <1>;
172 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
173 0x81000000 0 0 0x81000000 0x4 0 1 0>;
174 interrupt-map-mask = <0 0 0 0>;
175 interrupt-map = <0 0 0 0 &mpic 61>;
176 marvell,pcie-port = <0>;
177 marvell,pcie-lane = <3>;
178 clocks = <&gateclk 8>;
179 status = "disabled";
180 };
181
182 pcie@5,0 {
183 device_type = "pci";
184 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
185 reg = <0x2800 0 0 0 0>;
186 #address-cells = <3>;
187 #size-cells = <2>;
188 #interrupt-cells = <1>;
189 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
190 0x81000000 0 0 0x81000000 0x5 0 1 0>;
191 interrupt-map-mask = <0 0 0 0>;
192 interrupt-map = <0 0 0 0 &mpic 62>;
193 marvell,pcie-port = <1>;
194 marvell,pcie-lane = <0>;
195 clocks = <&gateclk 9>;
196 status = "disabled";
197 };
198
199 pcie@6,0 {
200 device_type = "pci";
201 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
202 reg = <0x3000 0 0 0 0>;
203 #address-cells = <3>;
204 #size-cells = <2>;
205 #interrupt-cells = <1>;
206 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
207 0x81000000 0 0 0x81000000 0x6 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 63>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <1>;
212 clocks = <&gateclk 10>;
213 status = "disabled";
214 };
215
216 pcie@7,0 {
217 device_type = "pci";
218 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
219 reg = <0x3800 0 0 0 0>;
220 #address-cells = <3>;
221 #size-cells = <2>;
222 #interrupt-cells = <1>;
223 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
224 0x81000000 0 0 0x81000000 0x7 0 1 0>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &mpic 64>;
227 marvell,pcie-port = <1>;
228 marvell,pcie-lane = <2>;
229 clocks = <&gateclk 11>;
230 status = "disabled";
231 };
232
233 pcie@8,0 {
234 device_type = "pci";
235 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
236 reg = <0x4000 0 0 0 0>;
237 #address-cells = <3>;
238 #size-cells = <2>;
239 #interrupt-cells = <1>;
240 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
241 0x81000000 0 0 0x81000000 0x8 0 1 0>;
242 interrupt-map-mask = <0 0 0 0>;
243 interrupt-map = <0 0 0 0 &mpic 65>;
244 marvell,pcie-port = <1>;
245 marvell,pcie-lane = <3>;
246 clocks = <&gateclk 12>;
247 status = "disabled";
248 };
249
250 pcie@9,0 {
251 device_type = "pci";
252 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
253 reg = <0x4800 0 0 0 0>;
254 #address-cells = <3>;
255 #size-cells = <2>;
256 #interrupt-cells = <1>;
257 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
258 0x81000000 0 0 0x81000000 0x9 0 1 0>;
259 interrupt-map-mask = <0 0 0 0>;
260 interrupt-map = <0 0 0 0 &mpic 99>;
261 marvell,pcie-port = <2>;
262 marvell,pcie-lane = <0>;
263 clocks = <&gateclk 26>;
264 status = "disabled";
265 };
266
267 pcie@10,0 {
268 device_type = "pci";
269 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
270 reg = <0x5000 0 0 0 0>;
271 #address-cells = <3>;
272 #size-cells = <2>;
273 #interrupt-cells = <1>;
274 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
275 0x81000000 0 0 0x81000000 0xa 0 1 0>;
276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &mpic 103>;
278 marvell,pcie-port = <3>;
279 marvell,pcie-lane = <0>;
280 clocks = <&gateclk 27>;
281 status = "disabled";
282 };
283 };
284
64 internal-regs { 285 internal-regs {
65 pinctrl { 286 pinctrl {
66 compatible = "marvell,mv78460-pinctrl"; 287 compatible = "marvell,mv78460-pinctrl";
@@ -113,194 +334,6 @@
113 clocks = <&gateclk 1>; 334 clocks = <&gateclk 1>;
114 status = "disabled"; 335 status = "disabled";
115 }; 336 };
116
117 /*
118 * MV78460 has 4 PCIe units Gen2.0: Two units can be
119 * configured as x4 or quad x1 lanes. Two units are
120 * x4/x1.
121 */
122 pcie-controller {
123 compatible = "marvell,armada-xp-pcie";
124 status = "disabled";
125 device_type = "pci";
126
127 #address-cells = <3>;
128 #size-cells = <2>;
129
130 bus-range = <0x00 0xff>;
131
132 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
133 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
134 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
135 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
136 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
137 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
138 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
139 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
140 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
141 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
142 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
143 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
144
145 pcie@1,0 {
146 device_type = "pci";
147 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
148 reg = <0x0800 0 0 0 0>;
149 #address-cells = <3>;
150 #size-cells = <2>;
151 #interrupt-cells = <1>;
152 ranges;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &mpic 58>;
155 marvell,pcie-port = <0>;
156 marvell,pcie-lane = <0>;
157 clocks = <&gateclk 5>;
158 status = "disabled";
159 };
160
161 pcie@2,0 {
162 device_type = "pci";
163 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
164 reg = <0x1000 0 0 0 0>;
165 #address-cells = <3>;
166 #size-cells = <2>;
167 #interrupt-cells = <1>;
168 ranges;
169 interrupt-map-mask = <0 0 0 0>;
170 interrupt-map = <0 0 0 0 &mpic 59>;
171 marvell,pcie-port = <0>;
172 marvell,pcie-lane = <1>;
173 clocks = <&gateclk 6>;
174 status = "disabled";
175 };
176
177 pcie@3,0 {
178 device_type = "pci";
179 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
180 reg = <0x1800 0 0 0 0>;
181 #address-cells = <3>;
182 #size-cells = <2>;
183 #interrupt-cells = <1>;
184 ranges;
185 interrupt-map-mask = <0 0 0 0>;
186 interrupt-map = <0 0 0 0 &mpic 60>;
187 marvell,pcie-port = <0>;
188 marvell,pcie-lane = <2>;
189 clocks = <&gateclk 7>;
190 status = "disabled";
191 };
192
193 pcie@4,0 {
194 device_type = "pci";
195 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
196 reg = <0x2000 0 0 0 0>;
197 #address-cells = <3>;
198 #size-cells = <2>;
199 #interrupt-cells = <1>;
200 ranges;
201 interrupt-map-mask = <0 0 0 0>;
202 interrupt-map = <0 0 0 0 &mpic 61>;
203 marvell,pcie-port = <0>;
204 marvell,pcie-lane = <3>;
205 clocks = <&gateclk 8>;
206 status = "disabled";
207 };
208
209 pcie@5,0 {
210 device_type = "pci";
211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
212 reg = <0x2800 0 0 0 0>;
213 #address-cells = <3>;
214 #size-cells = <2>;
215 #interrupt-cells = <1>;
216 ranges;
217 interrupt-map-mask = <0 0 0 0>;
218 interrupt-map = <0 0 0 0 &mpic 62>;
219 marvell,pcie-port = <1>;
220 marvell,pcie-lane = <0>;
221 clocks = <&gateclk 9>;
222 status = "disabled";
223 };
224
225 pcie@6,0 {
226 device_type = "pci";
227 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
228 reg = <0x3000 0 0 0 0>;
229 #address-cells = <3>;
230 #size-cells = <2>;
231 #interrupt-cells = <1>;
232 ranges;
233 interrupt-map-mask = <0 0 0 0>;
234 interrupt-map = <0 0 0 0 &mpic 63>;
235 marvell,pcie-port = <1>;
236 marvell,pcie-lane = <1>;
237 clocks = <&gateclk 10>;
238 status = "disabled";
239 };
240
241 pcie@7,0 {
242 device_type = "pci";
243 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
244 reg = <0x3800 0 0 0 0>;
245 #address-cells = <3>;
246 #size-cells = <2>;
247 #interrupt-cells = <1>;
248 ranges;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0 0 0 0 &mpic 64>;
251 marvell,pcie-port = <1>;
252 marvell,pcie-lane = <2>;
253 clocks = <&gateclk 11>;
254 status = "disabled";
255 };
256
257 pcie@8,0 {
258 device_type = "pci";
259 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
260 reg = <0x4000 0 0 0 0>;
261 #address-cells = <3>;
262 #size-cells = <2>;
263 #interrupt-cells = <1>;
264 ranges;
265 interrupt-map-mask = <0 0 0 0>;
266 interrupt-map = <0 0 0 0 &mpic 65>;
267 marvell,pcie-port = <1>;
268 marvell,pcie-lane = <3>;
269 clocks = <&gateclk 12>;
270 status = "disabled";
271 };
272 pcie@9,0 {
273 device_type = "pci";
274 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
275 reg = <0x4800 0 0 0 0>;
276 #address-cells = <3>;
277 #size-cells = <2>;
278 #interrupt-cells = <1>;
279 ranges;
280 interrupt-map-mask = <0 0 0 0>;
281 interrupt-map = <0 0 0 0 &mpic 99>;
282 marvell,pcie-port = <2>;
283 marvell,pcie-lane = <0>;
284 clocks = <&gateclk 26>;
285 status = "disabled";
286 };
287
288 pcie@10,0 {
289 device_type = "pci";
290 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
291 reg = <0x5000 0 0 0 0>;
292 #address-cells = <3>;
293 #size-cells = <2>;
294 #interrupt-cells = <1>;
295 ranges;
296 interrupt-map-mask = <0 0 0 0>;
297 interrupt-map = <0 0 0 0 &mpic 103>;
298 marvell,pcie-port = <3>;
299 marvell,pcie-lane = <0>;
300 clocks = <&gateclk 27>;
301 status = "disabled";
302 };
303 };
304 }; 337 };
305 }; 338 };
306}; 339};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 2b60ee08ef9f..5695afcc04bf 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -59,6 +59,15 @@
59 }; 59 };
60 }; 60 };
61 61
62 pcie-controller {
63 status = "okay";
64 /* Internal mini-PCIe connector */
65 pcie@1,0 {
66 /* Port 0, Lane 0 */
67 status = "okay";
68 };
69 };
70
62 internal-regs { 71 internal-regs {
63 serial@12000 { 72 serial@12000 {
64 clock-frequency = <250000000>; 73 clock-frequency = <250000000>;
@@ -176,15 +185,6 @@
176 usb@51000 { 185 usb@51000 {
177 status = "okay"; 186 status = "okay";
178 }; 187 };
179
180 pcie-controller {
181 status = "okay";
182 /* Internal mini-PCIe connector */
183 pcie@1,0 {
184 /* Port 0, Lane 0 */
185 status = "okay";
186 };
187 };
188 }; 188 };
189 }; 189 };
190}; 190};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 02:07:34 -0400