MIPS: Loongson: Modify ChipConfig register definition

This patch is prepared for Multi-chip interconnection. Since each chip
has a ChipConfig register, LOONGSON_CHIPCFG should be an array.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7185/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

7 files changed, 28 insertions, 14 deletions

diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index f3fd1eb8e3dd..a1c76caa7436 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -249,8 +249,11 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 #define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
 
-/* Chip Config */
-#define LOONGSON_CHIPCFG0               LOONGSON_REG(LOONGSON_REGBASE + 0x80)
+#define MAX_PACKAGES 4
+
+/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
+extern u64 loongson_chipcfg[MAX_PACKAGES];
+#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
 
 /* pcimap */
 
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index 0c543eae49bf..dc592412f764 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -27,6 +27,8 @@ EXPORT_SYMBOL(cpu_clock_freq);
 struct efi_memory_map_loongson *loongson_memmap;
 struct loongson_system_configuration loongson_sysconf;
 
+u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
+
 #define parse_even_earlier(res, option, p)                              \
 do {                                                                    \
         unsigned int tmp __maybe_unused;                                \
@@ -77,6 +79,15 @@ void __init prom_init_env(void)
 
         cpu_clock_freq = ecpu->cpu_clock_freq;
         loongson_sysconf.cputype = ecpu->cputype;
+        if (ecpu->cputype == Loongson_3A) {
+                loongson_chipcfg[0] = 0x900000001fe00180;
+                loongson_chipcfg[1] = 0x900010001fe00180;
+                loongson_chipcfg[2] = 0x900020001fe00180;
+                loongson_chipcfg[3] = 0x900030001fe00180;
+        } else {
+                loongson_chipcfg[0] = 0x900000001fe00180;
+        }
+
         loongson_sysconf.nr_cpus = ecpu->nr_cpus;
         if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
                 loongson_sysconf.nr_cpus = NR_CPUS;
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
index f55e07aee071..a6b67ccfc811 100644
--- a/arch/mips/loongson/common/pm.c
+++ b/arch/mips/loongson/common/pm.c
@@ -79,7 +79,7 @@ int __weak wakeup_loongson(void)
 static void wait_for_wakeup_events(void)
 {
         while (!wakeup_loongson())
-                LOONGSON_CHIPCFG0 &= ~0x7;
+                LOONGSON_CHIPCFG(0) &= ~0x7;
 }
 
 /*
@@ -102,15 +102,15 @@ static void loongson_suspend_enter(void)
 
         stop_perf_counters();
 
-        cached_cpu_freq = LOONGSON_CHIPCFG0;
+        cached_cpu_freq = LOONGSON_CHIPCFG(0);
 
         /* Put CPU into wait mode */
-        LOONGSON_CHIPCFG0 &= ~0x7;
+        LOONGSON_CHIPCFG(0) &= ~0x7;
 
         /* wait for the given events to wakeup cpu from wait mode */
         wait_for_wakeup_events();
 
-        LOONGSON_CHIPCFG0 = cached_cpu_freq;
+        LOONGSON_CHIPCFG(0) = cached_cpu_freq;
         mmiowb();
 }
 
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index 1eed38e28b1e..a217061beee3 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -114,9 +114,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 
         clk->rate = rate;
 
-        regval = LOONGSON_CHIPCFG0;
+        regval = LOONGSON_CHIPCFG(0);
         regval = (regval & ~0x7) | (pos->driver_data - 1);
-        LOONGSON_CHIPCFG0 = regval;
+        LOONGSON_CHIPCFG(0) = regval;
 
         return ret;
 }
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
index 90962a3a1731..79ac694fe744 100644
--- a/arch/mips/loongson/lemote-2f/reset.c
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -28,7 +28,7 @@ static void reset_cpu(void)
          * reset cpu to full speed, this is needed when enabling cpu frequency
          * scalling
          */
-        LOONGSON_CHIPCFG0 |= 0x7;
+        LOONGSON_CHIPCFG(0) |= 0x7;
 }
 
 /* reset support for fuloong2f */
diff --git a/arch/mips/loongson/loongson-3/smp.c b/arch/mips/loongson/loongson-3/smp.c
index 1e8894020ea5..3c320e709e91 100644
--- a/arch/mips/loongson/loongson-3/smp.c
+++ b/arch/mips/loongson/loongson-3/smp.c
@@ -399,12 +399,12 @@ static int loongson3_cpu_callback(struct notifier_block *nfb,
         case CPU_POST_DEAD:
         case CPU_POST_DEAD_FROZEN:
                 pr_info("Disable clock for CPU#%d\n", cpu);
-                LOONGSON_CHIPCFG0 &= ~(1 << (12 + cpu));
+                LOONGSON_CHIPCFG(0) &= ~(1 << (12 + cpu));
                 break;
         case CPU_UP_PREPARE:
         case CPU_UP_PREPARE_FROZEN:
                 pr_info("Enable clock for CPU#%d\n", cpu);
-                LOONGSON_CHIPCFG0 |= 1 << (12 + cpu);
+                LOONGSON_CHIPCFG(0) |= 1 << (12 + cpu);
                 break;
         }
 
diff --git a/drivers/cpufreq/loongson2_cpufreq.c b/drivers/cpufreq/loongson2_cpufreq.c
index d4add8621944..9fa177206032 100644
--- a/drivers/cpufreq/loongson2_cpufreq.c
+++ b/drivers/cpufreq/loongson2_cpufreq.c
@@ -148,9 +148,9 @@ static void loongson2_cpu_wait(void)
         u32 cpu_freq;
 
         spin_lock_irqsave(&loongson2_wait_lock, flags);
-        cpu_freq = LOONGSON_CHIPCFG0;
-        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
-        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+        cpu_freq = LOONGSON_CHIPCFG(0);
+        LOONGSON_CHIPCFG(0) &= ~0x7;    /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG(0) = cpu_freq; /* Restore CPU state */
         spin_unlock_irqrestore(&loongson2_wait_lock, flags);
         local_irq_enable();
 }